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Concept Engineering Showcases Effective SoC Debugging Techniques

Concept Engineering Showcases Effective SoC Debugging Techniques
by Pawan Fangaria on 05-15-2014 at 10:00 pm

In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization… Read More


Quantom Dots and Semiconductors?

Quantom Dots and Semiconductors?
by Daniel Nenni on 05-15-2014 at 4:00 pm

Imagine life without science and great minds that made life worth living! It is personalities like Newton, Thomas Alva Edison, Graham Bell, Alexander, Michael Faraday who have made us realized the true potential of science.

Imagine what would have happened if Newton had not discovered gravity? It is due to gravity that earth revolves… Read More


PrEDAC Mixer

PrEDAC Mixer
by Paul McLellan on 05-15-2014 at 3:53 pm

This month’s EDAC mixer is once again at the Savvy Cellar in Mountain View (basicallly in the Caltrain station). It is on May 22nd from 6-8pm.

Get together with your fellow industry peers and insiders at the monthly EDAC Mixer, to the benefit of local charities. You don’t need to donate anything, you just show up and pay… Read More


STM FD-SOI Manufacturing Double Source: Samsung

STM FD-SOI Manufacturing Double Source: Samsung
by Eric Esteve on 05-15-2014 at 8:54 am

Let’s start with apologies: when guessing that SMIC would be the 2[SUP]nd[/SUP] source foundry for ST-Microelectronics 28nm FD-SOI, I was wrong. To be honest, if I had made the assumption that Samsung was this double source, I would have generated dozen of comments, calling me “crazy blogger”…for the best. Announcing Samsung… Read More


Atmel and the Arduino Zero

Atmel and the Arduino Zero
by Paul McLellan on 05-15-2014 at 7:00 am

As I wrote about last month, this weekend is the Maker Faire in San Mateo. If you are interested in the cutting edge of what people are getting up to outside of the corporate world, this is the place to go. You will see stuff that you will not hear about for a year or two when it finally goes mainstream.

Increasingly, there is a lot of electronics… Read More


Apache Design @ #51DAC Must See!

Apache Design @ #51DAC Must See!
by Daniel Nenni on 05-14-2014 at 8:00 pm

Register to hear industry experts from top semiconductor companies share their best practices that enable the next generation of high-performance, low power designs for mobile, automotive and other applications. Meet our technologists for in-depth presentations, case studies and demos on the industry’s leading simulation… Read More


Synopsys @ #51DAC Must See!

Synopsys @ #51DAC Must See!
by Daniel Nenni on 05-14-2014 at 11:00 am

Accelerating Innovation—that has been at the heart of Synopsys’ commitment to its customers for more than 25 years. As a leader in EDA and semiconductor IP, Synopsys’ software, IP and services help engineers address their design, verification, system and manufacturing challenges and accelerate their innovations. Since 1986,… Read More


Samsung Endorses FD-SOI!

Samsung Endorses FD-SOI!
by Daniel Nenni on 05-14-2014 at 9:59 am

This is probably one of the biggest stories we will cover this month, if not this year, absolutely. In partnership with STMicroelectronics, Samsung will manufacture 28nm FD-SOI chips for the fabless semiconductor community starting now. This proves without a shadow of a doubt that Samsung is serious about the foundry business.… Read More


Cadence @ #51DAC Must See!

Cadence @ #51DAC Must See!
by Daniel Nenni on 05-13-2014 at 3:00 pm

Cadence is excited to bring a full slate of demos, technical presentations, papers, and more to the Design Automation Conference (DAC) June 1-5, 2014, in San Francisco, CA. From our technical experts, you’ll learn tips and techniques from areas including low power, mixed signal, advanced nodes, signoff, verification, and IP,… Read More


Taming The Challenges of SoC Testability

Taming The Challenges of SoC Testability
by Pawan Fangaria on 05-12-2014 at 10:00 pm

With the advent of large SoCs in semiconductor design space, verification of SoCs has become extremely challenging; no single approach works. And when the size of an SoC can grow to billions of gates, the traditional methods of testability of chips may no longer remain viable considering the needs of large ATPG, memory footprint,… Read More