When the topic of hardware emulation comes up, thoughts of big iron customarily come to mind. However, hardware emulation has evolved significantly and now there are other important traits that distinguish the offerings in this area. For a very long period of time emulators provided primarily a method to accelerate gate level simulations. Advances in capacity and performance eventually allowed emulators to also be used for HW/SW co-verification.
According to Jean-Marie Brunet, Mentor’s Emulation Division Marketing Director, we now have reached the fourth age of emulation – the Application Age. The first three were ICE Age, Acceleration Age, and the Virtualization Age. Over recent years Mentor has been working on making their Veloce emulation platform useful for many new tasks. Moving it to the data center and allowing it to work in conjunction with rack mounted servers for tasks such as compilation has made using emulation a lot easier and faster.
They also made it possible for multiple users from around the world to share a single emulator, thus increasing the efficiency and cost effectiveness of their solution. However, to understand how their latest ‘age’ of emulation works we have to start thinking of the system as a platform, with hardware, networking and, most importantly, with an operating system – one that allows applications for performing specific tasks.
Once it is clear that emulation can serve as a general purpose accelerator for many design verification tasks, the range of potential applications for it expands dramatically. The Veloce emulators can already handle large gate counts, from 250M gates up to 2B gates in their top of the line offering, Double Maximus. Expanding the range of tasks these systems can accomplish should be a game changer.
A good analogy is the development of the cell phone. Having the first phones that allowed mobile calls was considered amazing in their time. But now we have come to see our phones as being capable of many more things we could not previously imagine. So it is for emulation.
Mentor’s strategy for emulation is to use it for ‘de-risking’ design. One of the three VeloceApps they just announced on February 25[SUP]th[/SUP] is for DFT. Instead of verifying test patterns using software based DFT simulations, now Veloce can be used to speed this up thousands of times, ensuring that DFT simulations are completed in seconds or minutes instead of days.
One of the other VeloceApps just announced is an optimizer that work on large multi-clock SOC emulation. This app recognizes design attributes that can slow emulation, improving emulation runtime. Mentor claims that in certain cases user can expect to see ~50% reduction in emulator runtime.
The third VeloceApp that was introduced in this announcement is for ICE. Traditionally is it hard to replicate errors in an ICE environment because of non-deterministic behavior. Through the use if this App, an entire ICE run can be captured so that there is 100% visibility. Then the engineer can use the replay data base to step though the bug or fault to identify its cause. Having this take place in software means more controllability and better debugging capabilities are available.
Also, in the latest Veloce OS release, OS3, there have been improvements in the gate level compile flow, making it more efficient. Another big performance improvement was made in reducing the processing time required to convert raw test run results into viewable waveforms. Mentor is expecting users to see a 2X improvement as a result of hardware and software enhancements.
The Mentor announcement includes other improvements in the Veloce emulation solution. The full announcement can be found here. Emulation has moved from being an exotic solution for a narrow range of verification tasks, to become an almost necessary element of any large SOC’s verification flow. Expanding the applications is a smart of way making emulation solutions even more useful and valuable.Share this post via:
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