Cadence Announces Quantus Next Generation Extraction

Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.

As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power integrity), there is a lot of emphasis on being scalable to large numbers of CPUs giving up to 5X faster performance for single and multi-corner extraction runs. A lot of emphasis has been put on getting best-in-class accuracy especially for FinFET processes. It is backwards compatible with the prior version of QRC in that it uses the same technology files and the results correlate. There is also a random walk field solver that allows correlation to be checked (obviously only on a tiny part of a design, field-solvers are not full-chip tools).

Cadence have also worked closely with TSMC to ensure that the results correlate with silicon. Quantus QRC is fully certified at TSMC for 16nm FinFET and technology files are already available. It is also the first extraction solution certified to support 3D-IC (TSV-based designs).

Quantus is integrated into the Encounter platform (so there is the same engine under the hood during implementation as there is during signoff, which reduces spurious ECO loops).

It is also integrated into the Virtuoso platform. The integration is tight, in that there is no stream in and out between the two tools and so the extracted view flow allows for faster circuit performance debugging. Quantus executes right from the Virutuoso UI. It handles all the things you would expect such as RF, substrate noise analysis, inductance extraction, powerMOS extraction, RC and RLCK reduction and more.

It turns out I know a lot more than you might expect about circuit extraction since in about 1983 I wrote VLSI Technology’s circuit extractor. It didn’t do anything especially clever, it ran a scan-line across the whole (flat) chip that might have as many as…wait for it…10,000 gates, identified the transistors and the interconnectivity. I didn’t even have to worry about lateral capacitance or even resistance. But we only had 10 MIPS of CPU power and a couple of megabytes of memory, so it was non-trivial to get good performance. Even though computers are several hundred thousand times faster (and you can have hundreds of them) I can appreciate that keeping both the accuracy and the performance up given how many things interact with everything else (especially in FinFET) is an achievement.

Customer experience at AppliedMicro and Open-Silicon validates that it scales to 100s of CPUs and does deliver both accuracy and much faster run times.

For example, on a 20nm design of 39M gates, running on 32 CPUs it runs in 6 hours versus 15 for plain old QRC for a speedup of 2.5X. If the CPUs are increased to 64 then the speedup is 4.3X, so close to the 5X. Other designs (see the table) get even bigger speedups.

So, in summary:

• 5 times faster, scalable to 100s of cores
• best-in-class accuracy, silicon proven
• in-design convergence to accelerate design closure
• fully qualified in TSMC 16FF

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