CEO Interview: Dündar Dumlugöl of Magwel

CEO Interview: Dündar Dumlugöl of Magwel
by Tom Simon on 12-19-2016 at 7:00 am

Magwel CEO Dündar Dumlugöl is well known from his days at Cadence, where I first met him, and for his more recent tenure at Magwel. At Cadence he led the team that first developed Spectre. He has come a long way from the start of his career at IMEC in Belgium. He and I had a chance to have a conversation recently where he offered insights … Read More


Experts Talk at Mentor Booth

Experts Talk at Mentor Booth
by Pawan Fangaria on 05-11-2015 at 7:00 pm

It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning… Read More


Calibre xACT Shakes Up 16nm and Below Extraction Game

Calibre xACT Shakes Up 16nm and Below Extraction Game
by Tom Simon on 05-09-2015 at 8:00 am

Mentor Graphics made a big announcement regarding SOC extraction at their User2User conference in San Jose during April. Before I get to the meat of the announcement, I’d like to reflect back on the early days of Calibre-DRC at Mentor. I was in Sales at Mentor around 1999, and Calibre-DRC was the new kid on the block. We had to go convince… Read More


On-Chip Power Integrity Analysis Moves to the Package

On-Chip Power Integrity Analysis Moves to the Package
by Tom Simon on 03-11-2015 at 1:00 am

Power regimes for contemporary SOC’s now include a large number of voltage domains. Rail voltages are matched closely to the performance and power requirements of various portions of the design. Indeed, some of the supply voltages are so low that the noise margins in these domains is exceedingly low. Higher voltage domains are… Read More


A Deeper Insight into Quantus QRC Extraction Solution

A Deeper Insight into Quantus QRC Extraction Solution
by Pawan Fangaria on 08-14-2014 at 7:00 pm

Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of … Read More


Cadence Announces Quantus Next Generation Extraction

Cadence Announces Quantus Next Generation Extraction
by Paul McLellan on 07-14-2014 at 7:00 pm

Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.

As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power… Read More


FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


Xilinx & Apache Team up for FPGA Reliability at 20nm

Xilinx & Apache Team up for FPGA Reliability at 20nm
by Pawan Fangaria on 03-17-2014 at 12:00 am

In this age of SoCs with hundreds of IPs from different sources integrated together and working at high operating frequencies, FPGA designers are hard pressed keeping up the chip reliability from issues arising out of excessive static & dynamic IR drop, power & ground noise, electro migration and so on. While the IPs are… Read More


Speeding SoC timing closure

Speeding SoC timing closure
by Paul McLellan on 01-12-2012 at 1:42 am

As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More