Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of extraction. It’s obvious, massive parallelism with several CPUs combined power is at work, which Cadence did with Tempus timing signoff solution and Voltus power integrity solution as well, but there are more things to read into why it appears to be the best solution positioned for signoff extraction.
For the parasitic extraction to be of signoff quality it needs to be silicon proven, which Quantus QRC Extraction Solution provides with best-in-class accuracy; being fully certified for the ultimate 16nm FinFET process of TSMC. A new high-performance ‘random-walk’ field solver, Quantus FS embedded in Quantus QRC enables it to accurately extract critical nets; benchmark on a 20nm design shows mean of -0.01 and standard deviation of 3.09 compared to field solver on 1000 random nets.
Time appears to be the scarcest at the time of signoff and tape-out. The Quantus QRC provides automated incremental extraction for functional ECOs (Engineering Change Orders), such as any routing change in EDI (Encounter Digital Implementation), directly through an integrated database, thus eliminating the need of time consuming full-flat extraction at the chip or block level with every change.
Supporting FinFET process means taking into account many new parameters such as fringe 3D capacitances from gates and fins, new capacitance components to fins from gate thickness, new resistances, external capacitances to M0/V0 MEOL (Middle End of Line) contacts and below M1 FEOL (Front End of Line) features like complex poly structures, raised source and drain, two-step M0 and multi-finger fins with varied pitched and widths. Also, litho bias, corner variations and mask shift variations in BEOL (Back End of Line) process and double patterning technology need to be considered. The increases in parameters resulting into bigger netlists, design size, interconnect corners (3x more corners with double patterning at 20nm and below) etc. impact post-layout simulation performance. This requires complex modeling for better accuracy and efficient and faster simulation runs. The Quantus QRC Extraction Solution has a robust 3D modeling framework which provides unmatched accuracy against foundry and ~2x smaller netlist. The tool provides ~2.5x faster simulation run and faster characterization of standard cells, SRAMs and IPs.
The tool provides unique functionalities required for different types of designs such as SerDes, IP/SRAM/bitcell characterization, memory, powerMOS, image sensors, custom/analog and RF designs. It has unique capabilities for substrate noise analysis (SNA) with a full 3D substrate model, extraction of inductance and analysis of parasitic impact on clock and long nets in designs at ~100GHz, support of Partial Element Equivalent Circuit (PEEC) method and mutual and self-inductance, RC and RCLK reduction that can reduce simulation time by an order of ~20x, and meshR (used for powerMOS) providing better accuracy for irregular or wide metal shapes (large grids being at the center of the die and fine grids near contacts, edges and corners) and higher speed of simulation using adaptive meshing technique which reduces the number of resistances. A 3DIC using TSVs can be extracted precisely with this tool.
The Quantus QRC is closely integrated with Virtuoso ADE environment which provides early visibility into parasitics at the schematic level through in-design extraction of partial layout which can be easily generated from Virtuoso ADE. This helps in better correlation between schematic and post-layout simulation, thus reducing design iterations and aiding in faster design convergence.
The Quantus QRC Extraction Solution is integrated with all P&R tools, Virtual Prototyping and analysis tools and Signoff tools. It’s the same extraction engine during the implementation and signoff that provides better correlation and faster design closure. The users while working in Encounter Digital Implementation System can gain single-click execution for all extraction models.
Coming back to massive parallelism, what’s special about it? The performance is linearly scalable with the number of CPUs increased, generally not common with other architectures. It’s scalable for multi-corner simulation runs as well; an icing on the cake is that the tool runs 2-3x faster in case of multi-corner simulation. The Cadence proprietary parallel architecture allows scaling to unlimited number of CPUs and machines as the SoC size increases, thus providing highest capacity and performance.
The Quantus QRC Extraction Solution is the best-in-class technology for parasitic extraction and analysis for analog, digital and AMS SoCs employing today’s advanced node technologies. Its in-design integration with both analog and digital platforms along with a state-of-science field solver provides silicon-proven accuracy with faster design convergence and better correlation. More details can be obtained from a whitepaperwritten by Hitendra Divecha, Product Marketing at Cadence. The whitepaper has details of encouraging benchmarks for various steps in the overall design process.