Tag: edi

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In-Design DFM Signoff for 14nm FinFET Designs

In-Design DFM Signoff for 14nm FinFET Designs
by Pawan Fangaria on 11-04-2014 at 4:00 pm
Categories: Cadence, EDA, Foundries

While FinFET yield controversy is going on, I see a lot being done to improve that yield by various means. One prime trend today, it must be, it’s worthwhile, is to pull up various signoffs as early as possible during the design cycle. And DFM signoff is a must with respect to yield of fabrication. This reminds me about my patents filed… Read More

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A Deeper Insight into Quantus QRC Extraction Solution

A Deeper Insight into Quantus QRC Extraction Solution
by Pawan Fangaria on 08-14-2014 at 7:00 pm
Categories: Cadence, EDA

Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of … Read More