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Cadence Completes Power Signoff Solution with Voltus-Fi

Cadence Completes Power Signoff Solution with Voltus-Fi
by Paul McLellan on 08-15-2014 at 7:01 am

You probably remember Cadence introduced Voltus towards the end of last year at their signoff summit. This was aimed at digital designers. Prior to that they had announced Tempus, their static timing analysis tool. More recently they announced Quantus QRC extraction. All of these tools that end in -us have been re-architected to take advantage of large server farms, able to use dozens or even hundreds of cores to handle the largest designs in reasonable speed. These tools are primarily focused on supporting large digital SoCs.

Last week Cadence announced Voltus-Fi to complete their power signoff solution. It is aimed at analog designs and extends the electromigration and IR drop (EMIR) analysis to analog. It provides best-in-class transistor-level EMIR accuracy, especially in advanced node FinFET processes. It uses Cadence’s patented voltage-based iteration method, which requires a smaller memory footprint and runs faster than the industry’s traditional current-based iteration method. Basically it is a transistor level EMIR tool with SPICE level accuracy especially targeted at the most advanced nodes.


As I said at the announcement of Voltus:of course, those tools work just fine in non-advanced nodes too, but at 20nm and 16nm there are FinFETs, double patterning, timing impacts from dummy metal fill, a gazillion corners to be analyzed and so on.

As you would expect, it is fully integrated with Voltus itself, to give a seamless flow for advanced mixed-signal designs that contain both digital and analog blocks. It is also leverages Quantus QRC for transistor-level parasitic extraction, the Spectre Accelerated Parallel Simulator and the Spectre Extensive Partitioning Simulator.


It is also fully integrated into the Virtuoso platform for analog and custom block design. EMIR results from Voltus-Fi can be displayed on the real physical layout for quick analysis, debugging and optimization.

All this integration and performance shrinks the power signoff closure cycle. Many designs are more constrained by power and integrity issues than they are by raw performance, not least many of the most advanced chips for mobile where battery life is one of the key features of a device that shows through all the way to the end user. Consumers might not know what microprocessor is in their phone but they certainly know how long the battery lasts before they need to recharge it. Many submarkets of the Internet of Things (IoT) are even more power critical and also typically involve mixed-signal designs incorporating analog blocks (and perhaps sensors too).

See also:
Signoff Summit and Voltus

More articles by Paul McLellan…


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