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EDA for Power Management ICs at DAC

EDA for Power Management ICs at DAC
by Daniel Payne on 06-13-2014 at 11:38 am

I first met Dundar Dumlugolat Barcelona Design back in 2004, so it was a pleasure to meet with him again at DAClast week and learn more about what his company Magwel has to offer IC designers of power management chips.


Q: What IC design challenges does Magwel help with?

Engineers are doing power management chips and need to optimize the on resistance, and switch currents. (Rdson, current density issues, EM, IR drop analysis). We mesh and calculate the non-uniform current flows in these power transistors.

Q: What do users of your tools see?

IC designers see the current densities show up as graphical hotspots (PTM-ET our 2nd product)

Another EDA tool called PTM analyzes the power/ground networks (similar to Redhawk), extracts the R in these large netlists, then calculates IR drop as a static analysis now.

Q: How has business been for you?

We’ve had in the past 12 months a 55% growth in product revenue, with strong growth expected again in this year.

Q: What type of ESD analysis tool do you have?

Our product is called ESDi and it competes with PathFinder from Apache/ANSYS (5 years old) and Calibre PERC from Mentor. ESDi checks the ESD network on a chip, like IO cells, then verifies that internal devices are protected from any ESD discharge event. 1-2Amp currents are possible in the HBM (Human Body Model), where there are pairs of paths from Ground through your path that goes through an ESD device. There’s a full simulation for each of the paths (could be hundreds or thousands), where the simulation is physics-based, like a SPICE simulation, where it actually finds new ESD weaknesses. Users of this tool are ESD engineers, and designers, like ON Semiconductor. This is a relatively new product for us, and we are seeing very high interest.

Q: How is ESDi different than Calibre PERC?

With a tool like Calibre PERC it requires some rule setups, but it doesn’t actually do any simulation, instead it’s a smart topology checker. It only finds old problems, but doesn’t identify new ESD problems.

Q: Why is electro-thermal simulation important?

Our electro-thermal simulator is called PTM-ET and it provides both static and dynamic thermal simulation for power devices that calculates the self-heating of these large devices. This tool does full-chip simulation for power management ICs. You can replace an ARM core with an abstraction and model it, or it could come from an HDL simulation or calculations, could be dynamic too. Am I meeting my thermal budget with all of these abstract heat sources, plus power devices (dynamically simulated)? PTM-ET can co-simulate in Spectre, so as the circuit simulates then device power goes into PTM-ET and calculates temperature rise which is then fed back into Spectre (similar to Gradient, now Agilent), so we simulate both electrical and thermal together simultaneously. PTM-ET will also pinpoint thermal run-away phenomena in the same engine. Self heating is calculated with this tool.

Q: How is PTM-ET different than Icepak?

The Icepak tool From ANSYS is only thermal analysis, it has no understanding of voltages and currents, so the accuracy of the answers are lacking compared to our approach.

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