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On-Chip Power Integrity Analysis Moves to the Package

On-Chip Power Integrity Analysis Moves to the Package
by Tom Simon on 03-11-2015 at 1:00 am

Power regimes for contemporary SOC’s now include a large number of voltage domains. Rail voltages are matched closely to the performance and power requirements of various portions of the design. Indeed, some of the supply voltages are so low that the noise margins in these domains is exceedingly low. Higher voltage domains are still imbued with tight power rail noise margins due to performance needs. In either case designers have good reason to be concerned with power integrity. If the dynamic operation of the chip causes power or ground excursions, chip operation could be imperiled.

EDA companies have been working on di/dt on-chip analysis solutions for a long time. When I was at Sequence around 2002, this was a hot and heavy area of product planning and development. Sequence was ultimately acquired by Apache, which has since become part of ANSYS. But the initiative that emerged back then is still going full force.

ANSYS has long has had a solid and commercially well accepted offering in this space – RedHawk. But as a recent white paper from ANSYS points out, looking at power integrity on the chip by itself, assuming ideal connections to the power pins, is not sufficient to ensure design success. The package plays a significant role in determining the power integrity of a design. The power grid is fed by numerous C4 bumps on the die. There is nothing ideal in power delivery through today’s flip chip packages.

ANSYS points out that the package nets need to be modeled individually, not lumped together or aggregated. The modeling should include full RLCK effects as well. The approach that ANSYS’s RedHawk-CPA, chip package analysis, uses is to extract the package using a 3D FEM extractor. A big benefit of this extraction based approach is that it yields highly accurate results in a SPICE netlist format, instead of an s-parameter that you would get from a full field solver. Field solvers are necessary in the RF and high frequency range, but for power integrity the extraction approach is fine, and offers real benefits.

S-parameter data have return path information embedded in them, so isolating power and ground issues is complicated. S-parameters are good in frequency domain analysis, but what is needed here is transient analysis, which RLCK models excel at. The RedHawk-CPA flow used in conjunction with RedHawk provides for dynamic or static analysis of power integrity in various modes of operation. The difference when package information is included is dramatic.

Reading in package data is made simple for the IC designer with the ability to import SIP, ODB++ and MCM formats. Bump net assignments are handled by reading in a PLOC file. Of course this can be modified manually as well. By working with actual bump impedance values and package level decaps, RedHawk-CPA affords more realistic voltage drop and dynamic power grid performance results than would be achieved with estimates or less rigorous analysis.

At the end of the process a chip level model for power grid analysis is created that the package designer can use to optimize the package.

There are some nice visualizations available after the analysis. I am including some below. The resulting data can be used to visualize voltage, current maps, or waveforms. It also supports near and far field EMI computations. This is where ANSYS’s multi physics expertise comes in.

SOC designs are operating with speed and power requirements that push them to the limit of present technology. The main side effect of this is that nothing can be designed without consideration of other elements of the whole system. To read more about RedHawk-CPA for including package information in your power integrity analysis download this white paper.

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