It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning at us. Also, IoT related developments in various segments are poised to grow at most of the technology nodes including 28nm. At the same time, the design sizes have grown to unprecedented levels. This has created major challenges in the design, verification and testing of SoCs. Multiple verification approaches have to be employed to verify an SoC. Also, reliability has become more vulnerable at lower technology nodes, thus needing ever more accuracy in the estimation of various parameters relating to reliability.
Overall, design completion time tends to increase without leaving any scope for that to increase because time-to-market has rather decreased. The only alternative is to find innovative and faster methods for design and verification closure. From the business perspective in technology, I see wafer costs increasing as we go down the nodes and the demand still being there for wafers at higher technology nodes. In such a scenario, capacity at all nodes along with yield improvement at lower nodes needs more resources and efforts.
DAChas been a perfect forum since more than half a century where industry experts from all walks of semiconductor ecosystem join together to discuss, exchange ideas, demonstrate products and innovations, and present in several sessions. This creates an amazing learning environment. EDA has been a core enabler for the semiconductor industry and we see a great involvement and participation from the EDA community in DAC.
When I looked at the program at Mentor’s booth, I found pretty good topics that will be discussed there. The topics in various sessions touch upon the burgeoning challenges in the semiconductor design industry and their solutions. There are many industry leaders and experts who would be talking at Mentor’s booth #1432.
There are interesting panel discussions by well known personalities in the semiconductor industry who would discuss from foundry, design as well as tools perspective for solving major issues that are appearing in the design, verification and fabrication.
June 8, 4:00 PM –Meeting Exploding Demand Throughout the Ecosystem
Panellists: Joe Sawicki (Mentor), Kelvin Low (Samsung), Prasad Subramaniam (eSilicon)
It will be interesting to know how fabless companies, foundries and tool providers can jointly address to move to 14nm and below and at the same time help maintaining capacity at all technology nodes.
June 9, 4:00 PM – Emulation – Why So Much Talk?
Panellists: Alex Starr (AMD), James Hogan (Vista Ventures), Lauro Rizzatti (Verification Consultant)
This will be a valuable session for verification engineers and managers. New ideas will flow about emulation driven verification that can fit into several modes including simulation acceleration, embedded software acceleration, transaction-based acceleration, and in-circuit emulation.
June 10, 4:00 PM – The IC Design Waterfall: How Advanced Design Techniques are Now a Requirement at Established Nodes
Panellists: Michael Buehler-Garcia (Mentor), TianShen Tang (SMIC), Thomas Riener (ams), Richard Wawrzyniak, Semico Research Corp.
In this panel, one can appreciate the advanced verification methodologies that are essential to be deployed to address the design complexity irrespective of its technology node.
Then there are technical sessions that present and demonstrate the solutions to many critical issues of today including reliability analysis, designing at advanced nodes, IoT design, verification, and customer case studies and so on. To mention a few which I liked –
- Ahmed Eisawy, “Reliability Analysis of Analog-Centric ICs for Automotive Applications”
- Matt Hogan, “Competing in Reliability Focused Growth Markets with Calibre PERC”
- Jeff Wilson, Joe Kwan, “DFM and Fill Update for Advanced Nodes”
- Karen Chow, “Meeting New Extraction Challenges at Advanced Nodes and Advanced Design”
- Tom Daspit, “Pyxis IC Station for IoT Applications”
- Gordon Allen, “Maximize your Bug-finding Productivity with the Visualizer Debug Environment”
- Srinivas Velivala, Tom Williams, “DRC-Clean Cell Design in 30 Minutes – Qualcomm’s Experience with Calibre RealTime”
- John Ferguson, Ofer Tamir, “How to Banish Waiver Worry from your Design Flow”
There are many other sessions from Mentor’s Verification Academy including specific presentations on UVM environment and debugging methods. Also there are sessions on power analysis, test coverage, agile evolution in SoC verification, and so on.
A complete list of sessions can be found at Mentor’s website here. Search for specific sessions has been made easy with different categories such as “Technical Focus Areas”, “Experts at the Booth”, “Partner Activities”, and “Experts in the Conference” and so on. Select particular sessions of your choice from different categories and register for them. Do not forget to register for “Networking & Luncheons”, Mentor is providing refreshments!
Pawan Kumar Fangaria
Founder & President at www.fangarias.com