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Keywords: FD-SOI, Cost, FinFET

Keywords: FD-SOI, Cost, FinFET
by Eric Esteve on 07-15-2014 at 4:21 am

How to synthesize a pretty good article Is SOI Really Less Expensive, and even more important the impressive amount of comments (56) generated? Let’s start with the initial article. Pretty good, but slightly biased, when you carefully dissect it, like I did in one of the comments (you can find it in-extenso at the end of this post). In short, if FD-SOI goes into large production level (remember that Samsung has just licensed the technology), this will generate a positive impact on raw SOI wafers, accounting for 9 to 10% of the fully loaded wafers, and not 15%, in the above mentioned article. The second point (not high production dependent) is even more important: the article compares FD-SOI offering 3 Vt with Bulk, offering also 3 Vt.

If you don’t really know the technology, you may think that that’s a fair comparison. Unfortunately, it’s not! FD-SOI library requires only using two Vt when using an equivalent library (optimizing the leakage current) on Bulk will require at least four Vt. FD-SOI processing will then require less mask level, impacting again the fully loaded wafer cost. That is, you pass from par (100% normalized price for each technology) to 100% for Bulk to be compared with 90% for FD-SOI 28nm. The industry consensus is that 28nm will stay for long, and is the preferred node for cost sensitive products (like low-end wireless application processor), thus a 10% cost difference is really important. Now, the question is: should a marketing campaign be based on cost only? As a former ASIC PMM, I strongly think that using cost as the unique argument is at first not enough and finally dangerous. Highlighting the differentiators is much efficient!

We have described in this post how to benefit from the Forward Body Bias (FBB) effect in FD-SOI to increase the performance, or decrease the power consumption at the same performance level (just take a look at the article to get the complete picture). The biasing capability is a real differentiator, and the reason is that you can’t use it with FinFET!

If you don’t trust me, just look at this article from Ed Sperling in SemiconductorEngineering: “IP and FinFet at Advanced Nodes” mentioning Bernard Murphy, CTO of Atrenta: “The standard MCU guys, when they want to dial down power, don’t want to mess with the architecture because that has ripple impacts on a lot of other areas. So they use biasing, which is a great way to reduce leakage. But that doesn’t work with finFETs, and if you still have a power problem with your MCU you have to change the architecture.”
This biasing differentiation lead to the probably most important feature coming with FD-SOI: lower power consumption. It can be ultra low-power if you design a SoC for mobile application, and it can be simply more power efficient (at the same performance level) if you design a high performance networking IC. Benefiting from lower power consumption will have a tremendous impact on chip packaging and cooling, and all along the chain on massive power consumption of a server farm.

So, why the SC industry did not jump into FD-SOI technology? We get the answer in this excellent comment from IanD:

At the point where it became clear that something had to replace planar bulk technology and the industry had to decide whether to go with bulk FinFET or FDSOI (or even SOI FinFET), several things happened to influence this. The first was Intel announcing FinFET (and how fantastic is was) at least a couple of years before anyone expected it to happen, which caused a bit of a panic reaction largely driven by customers screaming “We must have FinFET to stay competitive!”. Also at this point FDSOI — especially the UTBB substrate capability — was not really ready and seen as risky and expensive, and FinFET was seen as the safe option. There was also a concern about future scaling to 10nm and below on the assumption that EUV would be ready and that these would be mass-production low-cost processes, with FinFET seen as scaling better to 7nm and 5nm which would all follow on from 10nm at the usual rate. So the industry rushed towards FinFET, probably much faster than they would have liked to without Intel’s bombshell — which as has been said many times, was a good choice for them making x86 CPUs, but not so obviously for the rest of the industry.

Since then things have changed somewhat. Some of the disadvantages of FinFET have started to emerge when SoC designers have started to actually use it — remember there isn’t such a thing as a free lunch, and the good points of FinFET in some applications (high drive, high speed, high density) are also bad points in others (high power density, higher gate capacitance, worse hotspot and EM issues) since the two are inextricably linked. Process variability which was not a killer issue for Intel CPUs is an issue for most other applications, and unlike for FDSOI can’t be trimmed out with FinFETs. …
Nobody’s suggesting that TSMC are stupid, they made the right decision based on what their customers were claiming for and given the state of FinFET and FDSOI at the time. Whether this was right given what we know now can be debated for years — hindsight is a wonderful thing, isn’t it? — but at least it now seems that FDSOI will be available and supported by multiple suppliers and IP providers for those people who are working in application spaces where it is better than FinFET, so at least the choice is there. For sure FinFET will be dominant initially as the juggernaut rolls on, but if FDSOI delivers on its low-power promises it should attract an increasing share of the market for applications where this is the #1 priority.

Another comment (see below) is not very positive about people promoting FD-SOI, but I think it is very smart in pointing the reason why FDSOI was not successful in the past: uncertainty.

From: Kencweng
Stop beating around the bush. The major challenge in FDSOI is not the substrate cost, the design ecosystem or even the stupidness of curtain persons. According to the substrate providers, the cost of SOI will soon be reduced. Based on my personal experience, porting a physical IP to FDSOI is not that difficult as what people think. Designing a physical IP for FinFET is harder. The design ecosystems are not that much different. Granted, we are all smart engineers.

IMHO, it is the uncertainty or the unknown fact(s) associated with any “promising” or “innovative” technology that makes the adoption so difficult. Unfortunately, the groups of persons who have been promoting SOI either ignore this or have their own agenda. What do we expect us to do after observing the struggle of persons who have chosen SOI? The persons who stay with bulk seem to be more successful.

All I can say is good luck for all persons who are pushing for SOI. May they succeed this time!

Uncertainty is not a scientific, quantifiable feature, it’s human, but it’s real! This is why the latest information about FD-SOI “Samsung Endorse FDSOI” is also the most important for years. Put yourself into the decision maker shoes. You were previously being cautious about FD-SOI because of uncertainty. Don’t you think that the same person will change his mind after seeing the 2[SUP]nd[/SUP] larger and most performing SC player adopting this technology? Just leave a couple of quarters, the time to start consolidating an IP ecosystem and for Samsung to familiarize with the technology, and check for FD-SOI adoption, let say during 2015…

From Eric Esteve from IPNEST

The pricing comparison seems to be the result of a deep research, nevertheless we can make two comments about the Tables, applying for 28nm and 14 nm as well:

  • Starting Wafer Cost is over-evaluated for SOI wafers in full production
  • Mask Layers are under-estimated for Bulk in 28nm or FinFET in 14nm if you take into account the various Vt you need to implement (4 to 5 Vt) to offer the same latitude than FD-SOI (with 2 Vt only) in respect with the leakage current.

Wafer Cost
Since 2011, the
agreement is $500 (in 28nm) for a SOI wafer, and $130 for a bulk wafer. The ratio is 3.8, when the Table (28nm) indicates 3% vs 15%, or a 5 ratio. Moreover, the bulk wafer pricing is at the lowest, as the 28nm Bulk is in full production. It is not un-reasonable to foresee a price decline for SOI wafer, when FD-SOI will be in full production at both STM and Samsung! Instead of 3% (bulk) and 15% (FDSOI), we may use 3% and 9-10% when in full production, or 12% as of today… Let say that the cost impact for FDSOI in full production should be (-5%)!

Multiple Vt in 28nm
Inserting the same number of Vt (3) in the table for Bulk and FD-SOI is not accurate: FD-SOI offer consists of only 2Vts and wide leakage control/optimization is reached through the use of multichannel libraries allowing to accommodate from 24nm to 40nm channel length in the std-cells pitch. For the same leakage control, with bulk technology you would have to use 4 Vts. The same applies on bitcells where to get the same range of the FD-SOI offer, bulk technologies have to differentiate several specific implants, adding masks. Why using multiple Vt approach? FD-SOI technology allows in the std-cells pitch to accommodate multi-channel libraries with the Lpoly ranging from Lmin=24nm to 40nm. This gives a great control over leakage when optimizing for power an implementation. The 2 Vts offered by FD-SOI provide a control over leakage of 1/200x (RVT L=40nm being 1/200 of the leakage of LVT Lmin=24nm, the leakiest device). To get the same leakage control range in a bulk technology (that allows a much reduced multichannel range), you need to use 4 Vts in a SoC.
FD-SOI library requires only using two Vt when using an equivalent library (optimizing the leakage current) on Bulk will require at least four Vt. The bottom line is that we count more masks on FDSOI than needed (to be removed) and less masks on Bulk (to be added), the difference being 4 to 5 masks levels, or another (-5%)!
That is, you pass from par (100% normalized price for each technology) to 100% for Bulk to be compared with 90% for FD-SOI 28nm. The industry consensus is that 28nm will stay for long, and is the preferred node for cost sensitive products (like low-end wireless application processor), thus a 10% cost difference is really important.
The same argumentation applies for 14 nm technologies. Even if the decision to select FinFET is not purely based on cost, but on better performance or leakage behavior, a 10% cost difference may have a certain impact, when making the decision. Moreover, If we consider on the edge devices processed in 14nm, the unit price is expected to be high. If you remember, we have mentioned the Forward Body Bias (FBB) capability available with FD-SOI. FBB allow either decreasing power, either increasing performance (frequency) of the same chip. But in a wafer fab, the same device is not processed the same way: it can be Slow, Typical of Fast, and you know it after test. When dealing with high variability, you may end up losing some yield because of it. FD-SOI has FBB as a plus for playing with process compensation, to eventually recover slow parts.

If your application requires chips in the high range or performance, that means that you have to trash a part of the production… except if you use FBB to compensate. Thus, you can keep the chip price in the acceptable range, as you can increase the number of good die (in respect with the performance) per wafer… This cost impact is difficult to quantify, as it will depend on the unit price, the level of performance, but we know from Intel marketing for processors that it can be high.
To summarize, even if a few percent cost difference may look negligible, the aggregation of these “small” differences lead to a 10% difference on the processed wafer cost. 28 nm technology node is expected to stay the mainstream for very long, due to the Moore’s law interruption, especially for the high volume, cost sensitive devices like low-cost application processor. As far as I remember from my ASIC PMM days, a 10% difference is all but negligible, thus I suggest using the right wafer price from the beginning. The devices implemented in 14 nm are probably not cost sensitive, but rather chase for high performance and/or ultra-low power. But is it a reason for pricing FD-SOI 10% higher than it should be?

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