As power has become one of the most important criteria in semiconductor design today, I was wondering whether there is a standard set for the power verification for an overall chip. We do have formats evolved like CPF and UPF and there are tools available to check power and signal integrity (SI), however I don’t see a standard objective assessment of power and SI verification. It’s more of a subjective matter based on how much testing has been done.
A while ago I was reviewing Apache’s industry leading tools, RedHawk and PowerArtist, and that made me curious to know about what kind of procedures these tools may be using for power grid and SI analysis and verification. And, to my pleasant surprise, I found this whitepaperwhich provides a good level of detail about the step-by-step, ordered flow at various stages that systematically increases the coverage of power grid verification. By gaining high coverage and fixing detected weak points, it is assured that the design is free from any SI defect such as high noise or jitter and any timing path violation. The overall Apache solution internally uses several powerful utilities and tools to perform these steps. So, let’s see in brief what these are.
Early Analysis: At this stage, early power estimation is done at RTL level of the design by using Excel2IR utility and RPM (RTL Power Model) interface to RedHawk, thus reducing lengthy iterations later.
Design Input Check: RHE (RedHawk Explorer) verifies complete design data and reports missing data to be completed. At this stage, the simulation setting is also checked and corrected such as required frequency for a good capture of design power.
Design Weakness: Design extraction at this stage can detect missing vias, shorts, unconnected wires and instances. LVS checks connectivity and RedHawk checks quality of connections and detects high resistances (which can lead to Noise and Electromigration issues) to particular devices. High resistance connections are fixed at this stage to avoid wastage of time in debugging later.
Static Simulation: This is the first level of simulation which confirms the design to average power consumption and current. Parameters such as adequacy of metal density, number of pads and number of power gates, in case of low-power design, are determined.
Dynamic Simulation Guided Vectorless: Vectorless simulation is very important for verification coverage because it detects weak points with the help of RedHawk’s built-in engine. It considers each instance: function, toggle, timing overlap, power, frequency, and weak connection to the power grid. Package data is also included as it has high inductance and that can lead to high dynamic IR drop. Design related activity and power information is added to guide the simulation.
Dynamic Simulation Scan: This stage reflects the largest current peak consumed by the design in a dynamic simulation. All FFs receive the same clock frequency. The simulation can be done in vectorless mode when the ATPG information about the scan order is inserted into RedHawk.
Dynamic Simulation RTL VCD: Using RTL VCD can provide realistic switching scenarios, however is limited by specific vectors. A state propagation can provide more accurate power calculation. RedHawk’s internal state propagation engine generates a small size of VCD file.
Dynamic Simulation GL VCD: At this stage, simulation is very accurate and the VCD has true timing including propagation delay, switching time and toggle for every instance. Accurate APL (Apache Power Library), package information and fine time step make the simulation results close to silicon.
RedHawk along with its other powerful utilities performs all these tasks and builds verification coverage to gain significant confidence in power and SI reliability of a chip, package and board. RHE is a versatile utility in-built into RedHawk and works at all stages. Success criteria for a tape-out can be pre-set in RHE which can then work on satisfying those criteria. A detailed description on all these procedures can be found in the whitepaper. Happy read!!
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