Enabling Next Generation Silicon In Package Products

Enabling Next Generation Silicon In Package Products
by Kalar Rajendiran on 04-15-2021 at 10:00 am

System on Package Motivation AlphaWave IP

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More


Maximizing ASIC Performance through Post-GDSII Backend Services

Maximizing ASIC Performance through Post-GDSII Backend Services
by Kalar Rajendiran on 03-04-2021 at 6:00 am

Panel 1 Alchip – HPC ASIC Manufacturing Done Your Way 1030x579 1

ASICs by definition are designed to meet the respective applications’ requirements. ASIC engineers deploy various design techniques to maximize performance, minimize power and reduce chip size. But is there more that can be done after the GDSII is taped out? A recent press release from Alchip Technology dated Feb 4, 2021 claims… Read More


Samtec Lets You Learn from Home with a Great Webinar Lineup

Samtec Lets You Learn from Home with a Great Webinar Lineup
by Mike Gianfagna on 01-20-2021 at 10:00 am

Samtec Lets You Learn from Home with a Great Webinar Lineup

Work from home (WFH) has become a normal occurrence this past year. “Do you work from home?”  “Of course, where else?” Samtec is taking the whole work from home thing up a notch with a new webinar lineup for 2021. Back by popular demand, they are launching a new series of educational webinars. Started last year, the gEEk SpEEk Webinar… Read More


Trace Design for Crosstalk Reduction

Trace Design for Crosstalk Reduction
by admin on 06-25-2020 at 11:00 am

Trace Design for Crosstalk Reduction
Presented by: Scott McMorrow

Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined,

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Bridging the Gap Between Design and Analysis

Bridging the Gap Between Design and Analysis
by Mike Gianfagna on 02-20-2020 at 6:00 am

PCB design challenges

At the recent DesignCon 2020 in Santa Clara, Cadence introduced a new product, Sigrity Aurora. You won’t find a press release about this announcement. Rather, Brad Griffin, product management group director at Cadence, presented Sigrity Aurora in the theater at the Cadence booth. This one caught my eye and deserves some discussion.… Read More


Mentor Automating Design Compliance with Power-Aware Simulation HyperLynx and Xpedition Flow

Mentor Automating Design Compliance with Power-Aware Simulation HyperLynx and Xpedition Flow
by Camille Kokozaki on 02-25-2019 at 12:00 pm

High-speed design requires addressing signal integrity (SI) and power integrity (PI) challenges. Power integrity has a frequency component. The Power Distribution Network (PDN) in designs has 2 different purposes: providing power to the chip, and acting as a power plane reference for transmission-line like propagating … Read More


Chip, Package, System Analysis – A User View

Chip, Package, System Analysis – A User View
by Bernard Murphy on 08-16-2018 at 7:00 am

While I missed ANSYS (and indeed everyone else) at DAC this year, I was able to attend the ANSYS Innovation Conference last week at the Santa Clara Convention Center. My primary purpose for being there was to listen to a talk by eSilicon which I’ll get to shortly, but before that I sat through a very interesting presentation on the growing… Read More


"Ten-hut!" Attending the Signal Integrity Bootcamp

"Ten-hut!" Attending the Signal Integrity Bootcamp
by Tom Dillinger on 02-21-2017 at 12:00 pm

The engineering team for the design and analysis of a complex system consists of a diverse set of skills — with the increasing emphasis on both high-speed interface design and multi-domain power management, a critical constituent of the team is the group of signal integrity (SI) and power integrity (PI) engineers.

The training… Read More


DesignCon 2017 and Mentor Graphics

DesignCon 2017 and Mentor Graphics
by Daniel Nenni on 01-17-2017 at 7:00 am

It’s hard to believe but this is DesignCon #22 and being a Silicon Valley conference I have attended my fair share of them. This year it seems like high speed communications will take the lead followed by the latest on PCB design tools, power and signal integrity, jitter and crosstalk, test and measurement tools, parallel … Read More