PCB designers have been using manual routing for decades now, so when is it time to consider adding interactive routing technologies to become more productive? Manually routing traces to connect components will take time from a skilled team member and involves human judgement that will introduce errors. When a design change … Read More
PCB designers can perform pre-route simulations, follow layout and routing rules, hope for the best from their prototype fab, and yet design errors cause respins which delays the project schedule. Just because post-route analysis is time consuming doesn’t mean that it should be avoided. Serial links are found in many PCB designs,… Read More
Embedded computing developers face new design challenges implementing high-speed protocols like 100 GbE, USB4, PCIe 5.0, DDR4/5, and more. This webinar introduces fundamental signal integrity concepts like insertion loss, return loss, and crosstalk, and relates them to a case study of the connector design for the COM-HPC… Read More
Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More
Dan is joined by Al Neves, Founder and Chief Technology Officer at Wild River Technology. Al has 30 years of experience in design and application development for semiconductor products and capital equipment focused on jitter and signal integrity. He is involved with the signal integrity community as a consultant, high-speed… Read More
As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More
We all know signal integrity and power integrity are becoming more important for advanced design. Like package engineering, the obscure and highly technical art of SI/PI optimization has taken center stage in the design process. And the folks who command expertise in these areas have become the rock stars of the design team. I … Read More
In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been… Read More
ASICs by definition are designed to meet the respective applications’ requirements. ASIC engineers deploy various design techniques to maximize performance, minimize power and reduce chip size. But is there more that can be done after the GDSII is taped out? A recent press release from Alchip Technology dated Feb 4, 2021 claims… Read More
Work from home (WFH) has become a normal occurrence this past year. “Do you work from home?” “Of course, where else?” Samtec is taking the whole work from home thing up a notch with a new webinar lineup for 2021. Back by popular demand, they are launching a new series of educational webinars. Started last year, the gEEk SpEEk Webinar… Read More
