If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.
Gerhard Angst (center), Concept Engineering
Q: How many years has Concept Engineering been attending DAC?
We now have 15 years of participation in DAC, something that not many companies have been able to achieve.
Q: What is new for you company this year?
New for 2013 at DAC is: Upgraded parasitic package SPEF (improved DSPF, RSPF).
Q: Who is using your EDA tools?
A public list of companies includes names like: Oasys, Tabula, Magma, etc. (40 OEM customers), about 3 new per year.
Q: How is your company funded?
We are privately funded and profitable.
Q: When did you start Concept Engineering?
We started this company some 23 years ago.
Q: How is business in Germany?
The German economy is strong and stable for our EDA tools this year.
Q: What should I expect to see in the next year from Concept Engineering?
Expect to see support for the Verilog-AMS language and UPF.
In the next 12 months we continue to see the AMS design debug area growing, both at the RTL and transistor levels.
StarVision PRO: RTL, Gate and SPICE level debug
Q: What type of debug is automated with your tools?
Some pure DIGITAL debug, while our biggest market is SPICE users, and AMS is also growing.
Q: Do your EDA tools work with other vendors?
Yes, and we are also member of Cadence and Synopsys 3rd party programs.
Q: Can I use the visual results from your tool in other EDA flows?
Yes, for example you can export to Skill, then Skill creates an OA for Cadence users. Map to Cadence library. Uses the Symbols from the Cadence PDK.
Q: Where should I go to evaluate your EDA tools?
We have distributors worldwide with long term distributors for end-user tools, or contact the factory for Widget-level support.
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