IC Design for Implantable Devices Treating Epilepsy

I’m utterly amazed at how IC-based products are improving our quality of life by implantable devices. The modern day pacemaker has given people added years of life by electrically stimulating the heart. A privately-held company called NeuroPace was founded in Mountain View, California to treat epilepsy by using responsive neurostimulation. Their first product is called the RNS System (Responsive NeuroStimulation), and it is a programmable, battery-powered, microprocessor-controlled device that delivers a short train of electrical pulses to the brain through implanted leads.

I spoke with Dean Anderson, engineering manager at NeuroPace about their IC design approach.

Dean Anderson, NeuroPace

Interview

Q: What is your role at NeuroPace?

I’m an IC design manager working on the next generation of neuro-stimulators. We have mostly system and front-end engineers and contract the IC layout efforts.

Q: How did you get interested in IC design?

I’ve always been interested in DSP and bio-medical applications. Out of grad school I worked at a pace maker company, and then 12-14 years on very low-power embedded devices. Small size and low power are the big design challenges, along with FDA approval using clinical trials proving efficacy on patients. Once you submit data to the FDA then you have to await their decision, then it’s OK to sell into the American market.

Q: What is the IC design flow approach at NeuroPace?

All of our chips are mixed signal designs. We just taped out in December an AMS SoC. Our approach is more bottom-up, where we partition our design into sub-blocks, then implement each sub-block. Design follows the partitioning and system specification.

For the digital portion we prototype in an FPGA. We use Verilog for our digital design and verification of test-benches, and use both ModelSim (Mentor) and Incisive (Cadence).

Analog designs are simulated and may be placed into a test chip before the final AMS chip. Spectre (Cadence) is our SPICE simulator.

Schematic capture is with Cadence Virtuoso.

Integration adds the Analog and Digital blocks together. We need to do more simulation of the Analog and Digital blocks together. Interfaces between the blocks are made as simple as possible.

Q: What were your latest Chip specs?

It was about 8 million transistors, running at 5MHz to achieve nA levels. An idle chip consumes maybe 2 uA, while peak usage is 20 uA, turning on the radio raises us to mA levels. We are totally power-centric because of the long battery life we need for 5 years of operation, but the longevity depends on the needs of the patient. Our power supply is a lithium-based battery specially designed for implants. Our device is curved and is installed inside of a patient’s skull.

Our patients can go swimming because our device is sealed against the elements.

Q: When did you first start using EDA tools from Concept Engineering?

I started using their tools a few years ago at the pace maker company, GateVision Pro. It was the quickest way to navigate through large Verilog netlists. We continue to use this tool here at NeuroPace to navigate our digital and analog netlists.

StarVision PRO lets us visualize our AMS designs, and it’s more efficient to use this tool compared to Virtuoso.

Q: If you didn’t have StarVision, then what would you do instead?

We would have to manually look at netlists or buy something very expensive like Encounter, which is overkill. Encounter only shows gates and blocks, there’s no transistor-level to visualize, so it’s not as easy for us to use compared with StarVision.

Q: What about IP re-use?

A large part of our designs do re-use our own IP blocks. Some blocks we do buy IP for are memories. Microcontrollers are another IP block that we buy, and then integrate into our SoC.

Q: What foundries do you work with?

A: For the lowest-power applications we are restricted to foundries like On Semiconductor which is well-know for this industry.

Summary
NeuroPace has an AMS design tool flow for the implantable electronics market, and uses a variety of EDA tools from multiple vendors. Their very low-power requirements make for a very interesting design challenge.

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