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Testing ARM Cores – Mentor and ARM Lunch Seminar

Testing ARM Cores – Mentor and ARM Lunch Seminar
by Beth Martin on 07-08-2012 at 8:29 pm

If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.

The lunch seminar runs from 10:30-1:00 at the Santa Clara Marriott. The presenters are Richard Slobodnik of ARM, and Stephen Pateras of Mentor Graphics. They will describe the specific test solutions developed to cover memory and logic test for ARM-based designs. A newer feature is the shared bus interface where MemoryBIST controllers reside outside of the ARM core, and use the shared bus to test the memory inside the core. Blocks with a shared bus and with memories on the bus (memory clusters) have a functional interface to the bus (see the figure).

Sign up for this free ARM / Mentor Graphics Lunch Seminar now.

If you want to study up before, here are two relevant whitepapers from Mentor:
Memory Test and Repair Solution for ARM Processor Cores
High Quality Test of ARM® Cortex™-A15 Processor Using Tessent® TestKompress®

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