Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 11-06-2019 at 10:00 am

Mentor - A Siemens Business

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 10-02-2019 at 10:00 am

Mentor - A Siemens Business

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Seminar: Mentor Forum for Tessent DFT 2019 India

Seminar: Mentor Forum for Tessent DFT 2019 India
by Daniel Payne on 09-17-2019 at 9:00 am

Mentor - A Siemens Business

Overview

Test for the Autonomous Age

The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

  • Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning
  • Achieving high test quality and
Read More

Seminar: Low Power Verification Forum

Seminar: Low Power Verification Forum
by Daniel Payne on 09-12-2019 at 11:30 am

Mentor - A Siemens Business

Overview

Reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, milaero, mobile, automotive, consumer, IoT and many others. Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing… Read More


Solido Lunch and Learn Seminar: Variation-Aware Verification and Library Characterization Powered by Machine Learning

Solido Lunch and Learn Seminar: Variation-Aware Verification and Library Characterization Powered by Machine Learning
by Daniel Payne on 07-30-2019 at 11:00 am

Overview

The ever-demanding and expanding applications in automotive, high-performance computing, mobile, and IoT are the driving force behind the increasing complexity of today’s semiconductor designs. Because of this, design and verification methodologies that were “good enough” in the past, are no longer adequate … Read More


IJTAG for IP Test: a free seminar

IJTAG for IP Test: a free seminar
by Beth Martin on 03-14-2013 at 1:53 pm

What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538


If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More