Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 11-06-2019 at 10:00 am

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 10-02-2019 at 10:00 am

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Seminar: Mentor Forum for Tessent DFT 2019 India

Seminar: Mentor Forum for Tessent DFT 2019 India
by Daniel Payne on 09-17-2019 at 9:00 am

Overview

Test for the Autonomous Age

The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

  • Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning
  • Achieving high test quality and
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Seminar: Low Power Verification Forum

Seminar: Low Power Verification Forum
by Daniel Payne on 09-12-2019 at 11:30 am

Overview

Reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, milaero, mobile, automotive, consumer, IoT and many others. Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing… Read More


Solido Lunch and Learn Seminar: Variation-Aware Verification and Library Characterization Powered by Machine Learning

Solido Lunch and Learn Seminar: Variation-Aware Verification and Library Characterization Powered by Machine Learning
by Daniel Payne on 07-30-2019 at 11:00 am

Overview

The ever-demanding and expanding applications in automotive, high-performance computing, mobile, and IoT are the driving force behind the increasing complexity of today’s semiconductor designs. Because of this, design and verification methodologies that were “good enough” in the past, are no longer adequate … Read More


IJTAG for IP Test: a free seminar

IJTAG for IP Test: a free seminar
by Beth Martin on 03-14-2013 at 1:53 pm

What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538


If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More


Power and Reliability Challenges

Power and Reliability Challenges
by Paul McLellan on 10-23-2012 at 12:38 pm

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More


Testing ARM Cores – Mentor and ARM Lunch Seminar

Testing ARM Cores – Mentor and ARM Lunch Seminar
by Beth Martin on 07-08-2012 at 8:29 pm

If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.

The lunch seminar runs from 10:30-1:00… Read More


Jasper Asian Seminars

Jasper Asian Seminars
by Paul McLellan on 04-04-2012 at 1:38 am

Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.

This full-day tutorial will be given by technical experts for verification experts… Read More


Fast Track your SoC Design

Fast Track your SoC Design
by Paul McLellan on 08-17-2011 at 5:24 pm

Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

  • finding quality IP faster
  • accelerating IP integration and SoC assembly
  • handing off RTL successfully.
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