What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple portable descriptions that can be supplied with the IP itself. This creates an environment for plug-and-play integration, access, test, and pattern reuse of embedded IP that doesn’t currently exist.
It’s the first new standard designed specifically to deal with the growing amount of IP used in today’s complex designs, and I expect that it will see wide adoption in the industry.
This seminar from Mentor Graphics covers the key aspects of IJTAG, including how it simplifies the design setup and test integration task at the die, stacked die, and system level. You will also learn about IP-level pattern reuse and IP access with IJTAG. Are you wondering what you need to do to migrate your existing 1149.1-based approach to P1687? Yep, that’s covered in the seminar too.
Mentor offers a product, Tessent IJTAG, to automate some aspects of implementing P1687, which is described in the seminar. Tessent IJTAG automates design and test tasks, and reduces the length of an aggregated test sequence for all the IP blocks in an SOC. This translates directly into faster production test readiness, reduced test time, and smaller tester memory requirements.
All the examples used in the seminar are from actual industrial use cases (from NXP and AMD). The presenter is Dr. Martin Keim. He has the experience and technical chops to make this a very useful day for everyone involved.
*DFT managers, DFT engineers, DFT architects, DFT methodologist, IP-, Chip-, System-Design managers and engineers, IP-, Chip-, System-Test integrator, Failure analysis managers and engineers, system test managers, and system test engineers. Whew!Share this post via:
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