Fast Track to a reconfigurable ASIC design

Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex Logix is doing something to help.

Perhaps the offering Flex Logix is launching was motivated in part by ARM and their DesignStart program. Under ARM DesignStart, developers can get a Cortex-M0 processor core to evaluate for free, coupled with a “fast track” $40K license when the design is ready for production use. ARM recognizes that although their processor IP is widely fielded, there are a lot of new prospects coming in from these newer application segments looking for a low-end core who may not be able to afford a big up-front license hit. (It will be interesting to see if ARM expands this program beyond just the Cortex-M0 core.)

Flex Logix has decided to adopt the same Fast Track name for their introductory licensing program, with some different parameters but a very similar intent. We’ve described how the Flex Logix EFLX cores provide point reconfigurability with programmable logic that can be added into an ASIC design. There are two strong benefits to this, besides the BOM elimination of an external FPGA or use of an expensive programmable SoC from one of the FPGA vendors.

First is the idea of creating hardware-based acceleration units inside an ASIC without resorting to a fully C-programmable DSP core (and its associated IP licensing fees). EFLX tiles can be used standalone or configured into more powerful MxN arrays for DSP or logic processing. This is especially useful when requirements are soft early in a project, or when multiple customers have slightly different requirements. The logic in the EFLX tile can be updated easily, using techniques similar to FPGAs except with better interconnect density and fully integrated inside the ASIC.

We’ve also been hearing the theme that just taking a chip design into a foundry can be expensive. I’d add to this conversation the two recent webinar discussions we covered from Cortus and Open Silicon on the use of multi-project wafer (MPW) starts to get costs down for mid-volume designs. This may be one of the stronger value propositions for the Flex Logix approach. I speak from experience when I say that mid-volume design customers almost always expect customization. Instead of spinning N parts for N different customers, Flex Logix can help reduce the number of ASIC starts required to win multiple customers since the EFLX cores allow customization of a base design with reconfigurability. It can be as simple as tweaking an interface with a small piece of programmable logic, or something bigger such as changing out multimedia processing.

There are two parts to Fast Track. For free evaluation under NDA, Flex Logix is offering everything needed to get started with either an EFLX-100 core in TSMC 40nm ULP/LP or an EFLX-2.5K core in TSMC 28nm HPM/C. Customers get encrypted Verilog models, the EFLX Compiler with its timing files, LIB and LEF, plus the full datasheet and silicon validation report.

When ready to move to prototyping, a single EFLX core can be licensed for $50K under Fast Track. Flex Logix provides the full Verilog models, GDS-II and CDL, integration guidelines and assistance, the EFLX compiler with full timing files and bitstream generation, and test vectors. Again, this is all fully validated in TSMC 40nm or 28nm processes.

More information on Flex Logix Fast Track is available at their website.

The idea that one ASIC design with reconfigurable logic can support a range of requirements and potentially handle multiple customers without respins or additional design starts should be attractive to design teams operating on a budget. Flex Logix may also be helping change the ASIC business model when it comes to offering customization with possibilities such as field upgrades and upstream revenue. The Fast Track program lowers the barrier to get started with creating new ideas around EFLX cores.