Panther Lake design rules revealed, no HD cells

[Fred Chen]

Some key Panther Lake design rules were posted on X:

https://twitter.com/x/status/2025063020184174676

Minimum pitch 36 nm (7nm-class), density obviously helped by 5 tracks from backside rails.

 

[siliconbruh999]

I would like to point out few things

• - Intel has traditionally used HP Cells in their Products. Intel 10nm -> ADL,RPL,TGL Intel 4/3 -> MTL/ARL.​
• - The decision to use HP/HD is on design not on foundry for what characteristics they want.​
• ​
• As for whether Intel can do 32nm direct print or not remains to be seen cause they didn't put it in any other product yet.​
  • ​
• The article seems poorly written imo.​

 

[LLL0955]

So is the HD cell more difficult to fabricate than HP cell? Due to the smaller pitch dimensions?

 

[siliconbruh999]

So is the HD cell more difficult to fabricate than HP cell? Due to the smaller pitch dimensions?

yeah smaller dimensions are more work especially 32nm single print

 

[Erik F]

Given the power consumption and performance of PTL, I say they made a good design choice.

For customers, doesn't that mean they have a potentially chaper alternative (since it is less dense) for the same power/performance level?

 

[siliconbruh999]

Given the power consumption of PTL I say they made a good design choice. Doesn't that mean they have a chaper alternative for the same power/performance level?

What do you mean by this ?

 

[Erik F]

What do you mean by this ?

I mean, if 18A can achieve the same level of performance/pc with less manufacturing complexity, it should be a competititve alternative

 

[siliconbruh999]

Yeah but initial 18A PDKs had issues which caused the delay.

 

[NY_Sam2]