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Panther Lake design rules revealed, no HD cells
Some key Panther Lake design rules were posted on X:
Minimum pitch 36 nm (7nm-class), density obviously helped by 5 tracks from backside rails.
I would like to point out few things
- Intel has traditionally used HP Cells in their Products. Intel 10nm -> ADL,RPL,TGL Intel 4/3 -> MTL/ARL.
- The decision to use HP/HD is on design not on foundry for what characteristics they want.
As for whether Intel can do 32nm direct print or not remains to be seen cause they didn't put it in any other product yet.
The article seems poorly written imo.
So is the HD cell more difficult to fabricate than HP cell? Due to the smaller pitch dimensions?
So is the HD cell more difficult to fabricate than HP cell? Due to the smaller pitch dimensions?
yeah smaller dimensions are more work especially 32nm single print
Given the power consumption and performance of PTL, I say they made a good design choice.
Given the power consumption of PTL I say they made a good design choice. Doesn't that mean they have a chaper alternative for the same power/performance level?
What do you mean by this ?
What do you mean by this ?
I mean, if 18A can achieve the same level of performance/pc with less manufacturing complexity, it should be a competititve alternative
Yeah but initial 18A PDKs had issues which caused the delay.
Last edited: Today at 6:33 AM
Feels like the last point is nonsense the decision to use HP/HD lies solely on the product group and their needs
If Backside or GAA/RibbonFET are new sources of yield loss, then relaxing to 36 nm pitch looks understandable. That said, high defect density at 36 nm pitch has been noted publicly before by imec, Samsung, and even (indirectly) TSMC.
Feels like the last point is nonsense the decision to use HP/HD lies solely on the product group and their needs
I think the article want to point out that even under HP cell the yield is still not high, so the HD cell with smaller pitch may get worse.
It is interesting to see when we will find 18A HD cell? Maybe Nova Lake?
I think the article want to point out that even under HP cell the yield is still not high, so the HD cell with smaller pitch may get worse.
Well NVL is mix of 18AP/N2for compute tiles
If Backside or GAA/RibbonFET are new sources of yield loss, then relaxing to 36 nm pitch looks understandable. That said, high defect density at 36 nm pitch has been noted publicly before by imec, Samsung, and even (indirectly) TSMC.
I remember the issue being parametric not the D0 the D0 has been decent from what i know
I think the article want to point out that even under HP cell the yield is still not high, so the HD cell with smaller pitch may get worse.
Future Intel iGPUs, NPU (AI) type dies are possible candidates for 18A HD as they don't need to aim for maximum clock rates.
