Webinar: Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

Webinar: Maximize Performance Using FPGAs with PCIe Gen5 Interfaces
by Mike Gianfagna on 09-01-2020 at 10:00 am

Maximize Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

FPGAs are a popular method to implement hardware accelerators for applications such as AI/ML, SmartNICs and storage acceleration. PCIe Gen5 is a high bandwidth communication protocol that is a key enabler for this class of applications. Putting all this together presents significant demands on the FPGA for performance and … Read More


Fast Track to a reconfigurable ASIC design

Fast Track to a reconfigurable ASIC design
by Don Dingee on 04-25-2016 at 4:00 pm

Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More


Reconfigurable redefined with embedded FPGA core IP

Reconfigurable redefined with embedded FPGA core IP
by Don Dingee on 02-12-2016 at 7:00 am

On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety… Read More