FPGAs are a popular method to implement hardware accelerators for applications such as AI/ML, SmartNICs and storage acceleration. PCIe Gen5 is a high bandwidth communication protocol that is a key enabler for this class of applications. Putting all this together presents significant demands on the FPGA for performance and throughput. I had the opportunity to preview an upcoming webinar on this topic presented by Achronix. The specialized approach taken by the Achronix flattens many very difficult problems. They are truly able to maximize performance using FPGAs with PCIe Gen5 interfaces. I’ll provide some background on the webinar to whet your appetite. Stay tuned for the registration link, you’ll want to watch this one.
First, a bit about Achronix. They are an FPGA/embedded FPGA vendor that focuses on specialized, high performance architectures. Their Speedster7t FPGA family is optimized for high-bandwidth workloads and eliminates the performance bottlenecks associated with traditional FPGAs. The product family is built on TSMC’s 7nm FinFET process. You can learn more about the company from an interview Dan Nenni did with Robert Blake, the CEO of Achronix.
The webinar is presented by Kent Orthner, senior director, systems at Achronix. Kent has an easy to follow presentation style. He packs a lot of information into a webinar that’s only about 30 minutes long. Kent has a long history of hardware and software engineering leadership at Arteris and Altera, so he definitely inspires confidence.
To finish setting the stage, let’s take a look at PCIe Gen5. This protocol represents the latest performance level in a long history of this standard as shown in the figure below. This latest version also supports more embedded signal integrity technology features. Protocols such as Compute Express Link (CXL) and NVMe are built on the PCIe Gen5 physical layer specification. Gen 5 will continue to be backward compatible with prior versions and wide deployment in data center and networking applications is expected.
So, what is discussed about maximizing performance using FPGAs with PCIe Gen5 interfaces and why is it so important? The webinar goes into the details of three application areas, as summarized below.
- Compute acceleration – AI/ML seeing exponential increase
- AI applications, like autonomous vehicles, generate 4TB data per day
- AI/ML training models doubling in size every 3-4 months
- Enterprise workloads moving to cloud, accelerated by increasing number of workers from home
- CPUs can’t keep up; need heterogeneous compute with specialized acceleration hardware
- A network interface card (network adapter) that offloads processing tasks that the system CPU would otherwise handle
- SmartNIC performs any combination of encryption/decryption, firewall, TCP/IP, SDN, etc.
- Storage acceleration
- Using specialized hardware to reduce CPU load, and to improve throughput and latency to non-volatile storage devices such as hard drive arrays and flash memory.
- g., inline compression, encryption and hashing, erasure coding, deduplication, string/image search, database operations e.g., sort/join/filter
For each of these areas the challenges of using standard FPGAs as hardware accelerators are described. The details of the unique features of the Achronix architecture to address these challenges are also presented. You’ll have to watch the webinar for the whole story, but here are some bits of information: Special FPGA enhancements such as a custom-designed, configurable on-chip network system offloads the FPGA fabric and delivers high performance and low latency. This system also simplifies timing closure and floor planning. There is also an array of math blocks optimized for AI/ML as well as support for high-speed SerDes, 400G Ethernet, GDDR6 and, of course support for PCIe Gen 5.
The webinar presents three real applications of the technology:
- Data center acceleration – machine learning inference
- 400 Gbps SmartNiC
- Storage acceleration
The details and results presented for these three scenarios are substantial and impressive. You will truly learn how to maximize performance using FPGAs. There’s sure to be something in there that will get your attention. The webinar will be presented on Tuesday, September 15, 2020 at 10AM PDT. You can register for the webinar here.
Share this post via: