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WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido

WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido
by Daniel Nenni on 09-01-2020 at 2:00 pm

surecore solido webinar graphic 1 verification

After spending a significant amount of my career in the IP library business it was an easy transition to Solido Design. I spent 10+ years traveling the world with CEO Amit Gupta working with the foundries and their top customers. In fact, the top 40 semiconductor companies use Solido. IP companies are also big Solido users including custom SRAM maker sureCore.

In my experience the best EDA and IP information comes from users and that is the basis for this webinar. surecore is a long time user of Solido tools and presents some case studies based on that usage. I learned a lot preparing for this webinar and it was great to reconnect with Amit and Tony, two highly regarded experts in this field.

Bottom line: If you have SRAM in your low power design this is a must attend event, absolutely.

Registration here and get the replay if you cannot attend.

Addressing Verification Challenges in the Development of Optimized SRAM Solutions

On-chip memory makes up an increasingly large proportion of the area of modern SoCs, and consequently optimising memory IP to match the specific requirements of an application is a way to improve the power, performance and area (PPA) metrics of new SoCs.

In several recent customer projects SureCore has demonstrated significant improvements in area, speed, and/or power by combining customer application knowledge with SureCore’s memory expertise. Statistical verification is a critical feature of the development flow and exploiting the Solido tool suite enables a rapid exploration of parts of the design space that are otherwise hard to quantify.

In this webinar SureCore and Solido will explain how they have been able to deliver dramatic PPA improvements while ensuring design reliability.

SPEAKERS:
TONY STANSFIELD, CHIEF TECHNOLOGY OFFICER, SURECORE
Tony has over 35 years of semiconductor industry experience in a variety of technical roles. He started his career with the Inmos UK Memory and Graphics group, where he designed SRAMs and Caches for multiple Inmos products. He later joined HP Labs to work on high-speed programmable imaging datapaths, and was a co-founder and VP Hardware Architecture at Elixent, the company created to deliver custom Silicon IP based on that technology. Following the acquisition of Elixent by Panasonic, he was a key member of the team that integrated this technology into multiple generations of TV chipsets. Tony is cited as an inventor on 23 patents covering SRAM, CAM, low-power electronics, and programmable logic.

AMIT GUPTA, GM, MENTOR IC VERIFICATION SOLUTIONS SOLIDO
Amit is General Manager of the IC Verification Solutions Solido division of Mentor, a Siemens Business. Previously, he founded Solido Design Automation Inc. in 2005 and served as its President and CEO until its acquisition by Mentor in 2017. Solido is a leader in machine learning variation-aware design and characterization.

About sureCore Limited
sureCore is the Low Power leader that empowers the IC design community to meet their aggressive power budgets through a portfolio of innovative, ultra-low power memory design services and standard products. sureCore’s low-power engineering methodologies and design flows helps you meet your most exacting memory requirements with customized low power SRAM IP and low power mixed signal design services that create clear marketing differentiation. The company’s low-power product line encompasses a range of down to near-threshold silicon proven, process-independent SRAM IP.


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