The need to design low power devices is not new. However, the criticality of lowering the power consumption of chip designs has never been as important as it is now. In 1989, I purchased one of the first consumer cell phones produced by Panasonic. The battery was the size of a brick, but only about a third of the thickness. If the battery were half that size, it would not have mattered much to me since it was still like carrying a purse. Or sometimes I clipped it into a docking station under the passenger seat of my car. Today, in cell phones and a myriad of IoT devices, battery size is critical, as is the total runtime available on a single charge to the system. While battery technology is important, it is even more important to reduce the power required to operate a device. Founded in 2011 with just this focus in mind, sureCore Limited will be presenting at a SemiWiki Webinar Series event to discuss the technologies that they have available to assist chip designers and chip architects in substantially reducing chip power.
For at least the past 20 years, memory blocks have dominated the on-chip real estate. The larger area has also consumed the largest portion of the chip power budget. sureCore has developed an arsenal of low power memory IP services and products to enable designers to build customized low-power SRAM memory blocks – SureFIT™, PowerMiser™, and EverOn™. These are not simple memory compiler solutions as they integrate very advanced features supporting low power. For example, EverOn has been built to support DVFS (dynamic voltage and frequency scaling). sureCore’s “SMART-Assist” technology allows robust operation down to the retention voltage, critical in ‘keep-alive’ specifications.
Memory compilers have been used for a couple of decades now, though not all have been successful in their ability to deploy in low power processes. These tools are used to generate SRAM memory blocks over a huge number of memory configurations and memory specification options for a specific process. There is a need for them to be quite robust in the face of low voltage thresholds, process variation, and a large number of possible option choices. To do this, the memory architecture, as well as the generators, need to embed special knowledge beyond simply repeating bit cell patterns. There may be the use of self-timing chains or circuits tricks to get the memories to work based on the options selected. These designs seem to be built using engineering, science, – and art.
The event will be moderated by SemiWiki founder, Daniel Nenni. The presenter will be Paul Wells. Paul has worked in the semiconductor industry for over 30 years. He co-founded sureCore in 2011 and has kept them focussed on the market for low power embedded SRAM. His previous experience in design & management at several respected companies such as Pace Networks, Jennic Ltd., Plessey Semiconductors and Fujitsu Microelectronics, has enabled sureCore to build this broad yet focused portfolio of low power memory IP solutions while also offering a Low Power Mixed Signal Design Service.
This webinar, “The Brave New World of Customized Memory” will be held on Wednesday, August 28, 2019, from 10:00a m to 10:45 am PDT. To sign up for the webinar, register using your work email address HERE. A replay URL will be sent to all registrants in case you miss the live version.
sureCore Limited is an SRAM IP company based in Sheffield, UK, developing low power memories for current and next-generation, silicon process technologies. Its award-winning, world-leading, low power SRAM design is process independent and variability tolerant, making it suitable for a wide range of technology nodes. This IP helps SoC developers meet challenging power budgets and manufacturability constraints posed by leading-edge process nodes.