sureCore is the Low Power leader that empowers the IC design community to meet their aggressive power budgets through a portfolio of innovative, ultra-low power memory design services and standard products. sureCore’s low-power engineering methodologies and design flows helps you meet your most exacting memory requirements with customized low power SRAM IP and low power mixed signal design services that create clear marketing differentiation. The company’s low-power product line encompasses a range of down to near-threshold silicon proven, process-independent SRAM IP.
Low power design has become THE critical issue for SoC developers. Many applications demand reduced power consumption in the form of both lower standby power and substantial cuts in dynamic power as the trend towards “always-on” accelerate. Innovative Artificial Intelligence, IoT, wearables, medical, mobile, automotive and networking products all require sureCore’s power optimizing technologies and capabilities. sureCore low power design capabilities and standard products are silicon-proven, process independent, variability tolerant and features market leading dynamic & static power consumption.
Today’s emerging markets aren’t playing by yesterdays rules… design or otherwise. SoC architects developing cutting edge artificial intelligence, imaging, machine learning, wearable, and IoT devices can no longer make do with standard memory IP to deliver lower and lower power targets. Their designs are ahead of the game. They demand application specific power and performance; targets that demand “out-of-the-box” thinking, targets that deliver market leading energy efficiency.
When developers need extraordinary Ultra-Low Power Memory IP they turn to SureFIT™, sureCore’s application-centric custom memory design service to deliver on their unique design and PPA requirements. Memory tuned to their low-power needs. Memory tuned to deliver disruptive innovation. Memories that are optimised, verified, characterised and ready for integration.
SureFIT™ creates bespoke memory solutions tailored to meet application needs, hitting both functional and power targets. Achieving competitive power advantage when all developers have access to the same standard SRAM IP is challenging. SureCore can architect and implement single instances or compilers to deliver clear market advantage. Practical examples include multi-port (1W/8R) and multi-megabyte solutions for networking and imaging devices. Design expertise covers Bulk, FDSOI and advanced FinFET nodes. Silicon prototyping and full temperature characterisation mean SureFit solutions are robust and high yielding. Multiple test chips and a modular test system have been developed.
sureCore’s Low Power SRAM IP has been developed for leading-edge devices demanding long battery life and minimal operating and stand-by power consumption. PowerMiser™ products have been realized in both 28nm FDSOI and 40ULP BULK CMOS manufacturing processes.
In the 28FDSOI process this Low Power macro supports a wide operating voltage range from 0.7v to 1.2v where it demonstrated dynamic power savings exceeding 50% of current commercial instances. The IP has also demonstrated leakage power savings ranging from 38% to 21%, depending on operating conditions, while incurring between 5-10% area penalty. Similar power savings are achieved in 40ULP.
The compilers support capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.
PowerMiser™ delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques have the added benefit of virtually eliminating performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are offered.
sureCore’s Single Port Ultra Low Voltage (ULV) SRAM IP is silicon-proven on 40ULP BULK CMOS process and provides up to 80% savings in dynamic power consumption and an up to 75% reduction in static power.
The memory operates down to a record-setting 0.6V across process, voltage and temperature delivering an impressive operating voltage range from 0.6V to 1.21V. It provides an unprecedented 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V, opening new capabilities for cutting edge wearable and Internet of Things applications.
The ULV compiler supports synchronous single port SRAM with operating voltages ranging from 0.6 to 1.21 volts and memory capacities ranging from 8Kbytes to 576Kbytes with maximum word lengths of 72bits.
EverOn™ meets the challenges posed by dynamic voltage and frequency scaling (DVFS). Built using high-density foundry bit cells to reduce area, a single supply rail implementation eases integration.
sureCore’s “SMART-Assist” technology allows robust operation down to the retention voltage. Further architectural innovations include subdividing the memory into up to eight banks, which in conjunction with enhanced sleep modes, provide greater system level flexibility. As well as operating in peripheral power off, light and deep sleep modes, each bank can also be independently controlled for active or in light sleep, deep sleep or power off modes. These power saving modes provide greater flexibility to tailor product performance around operational needs and extend battery life.
CHIEF EXECUTIVE OFFICER
Paul has worked in the semiconductor industry for over 25 years including two years as Director of Engineering for Pace Networks where he led a multidisciplinary, 70 strong, product development team creating a broadcast quality video & data mini-headend. Before this, he worked for Jennic Ltd as VP Operations, successfully building the team from scratch as the company transitioned to a fabless model. Prior to this, he was responsible for the engineering team and before that he led a team for Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.
Woz Ahmed is EVP Corporate Development at Imagination Technologies. He previously worked for Imagination from 2004 to 2016, initially in business development, taking Imagination into China, Taiwan and Korea, and later ran M&A and other corporate projects as a VP. Woz most recently worked in the early-stage ‘deep tech’ space as a consultant to venture capital firms. He has previously held marketing management roles at Hitachi (now Renesas), ARC (now part of Synopsys) and Avnet. He began his career in customer engineering with companies including IBM and National Instruments. He has a B.Eng degree in Electronics and Computing from Kingston University, an MBA from Henley and attended the Private Equity Programme at the University of Oxford’s Said Business School.
PROF. ASEN ASENOV
Asen Asenov (FIEEE, FRSE) is a founder and CEO of Gold Standard Simulations (GSS) Ltd. GSS is the leader in physical simulation of statistical variability, statistical compact model extraction and generation technology and statistical circuit simulation. The GSS customers include three of the largest foundries, two of the most influential IDMs, a fabless company and three design IP startups. As a James Watt Professor in Electrical Engineering and Leader of the 30 members strong, Glasgow Device Modelling Group, Asenov directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices. Asenov has more than 620 publications and more than 170 invited talks in the above areas.
Mark is a commercial board level Finance Director with considerable experience working in a financial and commercial environment with particular focus on scaling SME’s to a trade sale. He has held a variety of senior financial positions at Samsung, APW Inc, Invensys Plc, NXP and Jennic and lately as CFO for technology startups Secure Thingz, Faradion and Additive Manufacturing Technologies. Mark is a member of the Institute of Chartered Accountants in England and Wales and has a Bsc. (Hons) in Finance and Accounting.
Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 40 years gaining experience as a senior executive and board director in electronic design automation, intellectual property, semiconductor equipment, material science and IT companies. Currently, Jim serves on several private companies’ board of directors. Additionally, Jim serves as a strategic advisor to several private and public companies.