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CEO Interview: Paul Wells of sureCore

CEO Interview: Paul Wells of sureCore
by Daniel Nenni on 10-16-2020 at 6:00 am

Paul Wells SemiWiki 1What brought you to semiconductors? 
As a kid I was interested in electronics and early personal computers. I went on to graduate from Manchester University in 1986, the birthplace of the modern computer, studying Computer Engineering where for my final year project I designed a gate array using Ferranti Electronics technology (1.2um!). After seeing the devices work first time, I was so enthused I went to work for them – they later became Plessey and then GEC Plessey (GPS). Joining Fujitsu I then became a logic designer using a new language called Verilog and an early version of design compiler. We developed a Speech Processor chip in 0.8um technology for a GSM chipset. Latterly I moved into the highly successful ASIC team as a physical design engineer supporting customers all over Europe and Israel – the 90’s were an exciting time as everything went digital. I joined my first start-up, Jennic, in 2000 where after a few iterations we transitioned to a fabless model designing and supplying wireless microcontrollers targeting the Zigbee standard. Here I built and led the operations team to deliver evaluation kits, modules and packaged devices to our end customers. A brief sojourn into digital TV followed where I spent 2 years working for Pace Networks managing a team of 70 to develop a mini headend (The MultiDweller) distributing HD video and data over cable networks. Following this I co-founded sureCore in 2011 with support from a tech savvy investor.

What is the sureCore company backstory?
After leaving Pace Networks in 2010 I was introduced to an investor keen to capitalise on the technology developed by a Glasgow University spinout called “Gold Standard Simulations” (GSS) led by Prof. Asen Asenov – a world leading expert on silicon process variability. Working with GSS highlighted the challenges of SRAM design for sub-40nm nodes – the industry was demanding increased on-chip SRAM but the density and power characteristics were no longer scaling at the same rate due to process variability. My colleagues in the industry confirmed that the underlying SRAM architecture hadn’t changed in over ten years. At sureCore we started to explore various architectural enhancements that could manage variability and cut power consumption. Working closely with ST we developed a test chip in 28FDSOI that showcased our technology by demonstrating power savings in excess of 60%. We were later able to prove that our circuit techniques were as applicable to both Bulk CMOS and FinFET processes.

What range of products do sureCore develop and what is their USP?
Our principal focus is on low power and low voltage SRAM. We have a product family called “PowerMiser” that typically delivers 50% dynamic power savings and about 20% static power savings compared to competitive offerings. Our “EverOn” family enables the SRAM to be directly interfaced to the logic without the need for level shifters and can operate from the process Vnom all the way down to the bit cell retention voltage. This is facilitated by our patented “SMART-Assist” technology. We have compilers for a range of nodes from 40nm to 22nm. We have also developed a range of low voltage register files that can similarly operate at extremely low voltages – allowing architects the capability to scale performance as the application requires and make significant power savings.

We also offer a custom memory development service called “sureFIT” where we work closely with our customers to understand their application and jointly come up with a memory specification that aligns with usage requirements and delivers an optimal power profile. For many customers seeking to deliver power optimised solutions, for example, in the medical, IoT or AI spaces then this service can help deliver truly differentiated products.

Why is SRAM power such a big deal?
The last ten years has seen a dramatic rise in the quantity of embedded SRAM on chip. For multi-processor devices integrating SRAM made sense as pulling code and data from off-chip DRAM had huge power and timing penalties. Over the last few years AI developers similarly looking for power optimisations have been driven to integrate many Mbytes of on-chip SRAM. Other application spaces like AR and Networking have comparable demands. Some market researchers estimate that SRAM occupies up to 70% die area for some applications and whilst this is not true across the board the underlying trend is clearly upwards. SRAM provides the fastest most efficient access to data, however, the power consumed contributes significantly to the overall consumption, in some cases limiting the maximum performance and in others meaning expensive package selection to ensure adequate thermal dissipation. Cutting SRAM power consumption is an area whose time has come and for which sureCore technology is ideally suited.

Does sureCore only focus on SRAM or are there other areas when you bring value?
Over the course of many years developing low power SRAM we have developed a range of low  power design methodologies and know-how that enable us to rapidly port between process nodes. We have also invested heavily in statistical and parametric verification capabilities as well as timing/power characterization. Some of our customers exploit these skills to help augment their own teams.

What can be done to optimize SRAM for particular applications?
Our optimizations are pretty much focused on power – whether that be dynamic or static. Power has become the critical issue for our industry whether to prolong battery life or to reduce power dissipation for thermal or cost reasons. For battery powered applications then it is all down to the usage profile. For those that spend most of their time asleep then clearly leakage is critical. For others in the medical space like hearing aids then not only is leakage important but also dynamic power. The capability to operate across a wide voltage range can yield spectacular power benefits. At sureCore we have developed a “tool-box” of power saving techniques that can be applied to any application. Early engagement by way of a feasibility study allows us to explore a variety of potential architectures that could suit the customers need. Once this is understood then a full implementation program can be scoped.

What customer problems have you solved thus far?
One customer we worked closely with needed a large multi-Mbyte memory subsystem for an AR application. Building this from off-the-shelf SRAM proved untenable from a system power budget perspective. By creating a custom SRAM instance and integrating it into a low voltage interconnect fabric meant power savings of over 40% could be achieved compared to a standard implementation. Also contributing to the power efficiency was an understanding of access patterns meaning that an intelligent access controller could keep most SRAM instances asleep until an access was due. This was implemented in a 16nm FinFET process.

Another customer in the networking space, also targeting 16nm, needed a 1-Write, 8-Read memory. By undertaking an architectural exploration we were able to demonstrate that the optimal solution was a double pumped implementation based on a custom 1-Write, 4-Read bit cell. The 8 reads being delivered by 2 reads per port per cycle. Not only did this meet area requirements it also delivered power savings of 60%.

What does the next 12 months have in store for sureCore?
The 16FF node is starting to be seen as a highly power efficient alternative. Although initially developed for high performance applications both density and leakage characteristics are making it increasingly attractive for a range of medical and wearable applications. The company is currently engaged with a tier-1 customer keen to exploit both our SRAM and register file technologies in 16FF. Previous projects have demonstrated that sureCore technology scales well to FinFET nodes and delivers significant power savings compared to competitors. By adopting our technology the customer will be able to deliver genuinely differentiated products with dramatic improvements in battery life. We intend to capitalize on this engagement and make it available across a range of advanced process nodes and foundries. Never has our industry needed a low power SRAM alternatively more desperately. We at sureCore intend to fill that gap.


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