3rd Party Semiconductor Intellectual Property Market Update

3rd Party Semiconductor Intellectual Property Market Update
by Richard Wawrzyniak on 05-12-2021 at 6:00 am

IP Market

The 3rd Party Semiconductor Intellectual Property (IP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures that the entire electronics market has undergone, … Read More


Making Full Memory IP Robust During Design

Making Full Memory IP Robust During Design
by Daniel Payne on 08-28-2020 at 10:00 am

64Mb SRAM example, memory IP

Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More


Rapid growth of AI/ML based systems requires memory and interconnect IP

Rapid growth of AI/ML based systems requires memory and interconnect IP
by Tom Simon on 11-07-2019 at 6:00 am

Artificial intelligence and machine learning (AI/ML) are working their way into a surprising number of areas. Probably the one you think of first is autonomous driving, but we are seeing a rapidly growing number of other applications as time goes on. Among these are networking, sensor fusion, manufacturing, data mining, numerical… Read More


WEBINAR: The Brave New World of Customized Memory

WEBINAR: The Brave New World of Customized Memory
by Randy Smith on 08-08-2019 at 10:00 am

The need to design low power devices is not new. However, the criticality of lowering the power consumption of chip designs has never been as important as it is now. In 1989, I purchased one of the first consumer cell phones produced by Panasonic. The battery was the size of a brick, but only about a third of the thickness. If the battery… Read More


Succeeding with 56G SerDes, HBM2, 2.5D and FinFET

Succeeding with 56G SerDes, HBM2, 2.5D and FinFET
by Daniel Nenni on 03-17-2017 at 4:00 pm

eSilicon presented their advanced ASIC design capabilities at a seminar last Wednesday evening. This event was closed to the press, bloggers and analysts, but I managed to get some details from a friend who attended. The event title was: “Advanced ASICs for the Cloud-Computing Era: Succeeding with 56G SerDes, HBM2, 2.5D and FinFETRead More


CEO Interview: Alan Rogers of Analog Bits

CEO Interview: Alan Rogers of Analog Bits
by Daniel Nenni on 03-06-2017 at 7:00 am

It has been incredible to watch the Semiconductor IP market grow from millions to billions of dollars during my career in Silicon Valley. In fact, more than half of my professional experience involves IP so when I talk about what it takes to be successful it is certainly worth a listen.

In my opinion the key ingredient to a successful… Read More


eSilicon Demonstrates Potent Memory IP Evaluation Platform

eSilicon Demonstrates Potent Memory IP Evaluation Platform
by Tom Simon on 11-18-2016 at 4:00 pm

With memories taking up in some cases over 50% of the area of many ASIC designs, their selection and implementation can affect everything from power and timing to the choice of packaging. As a result, the process of deciding among all the options for ASIC memories becomes time and energy intensive. Memory selection even affects … Read More


Webinar on Revolutionary Changes in SOC IP Access

Webinar on Revolutionary Changes in SOC IP Access
by Tom Simon on 10-22-2016 at 7:00 am

Knowledge is power, and I’ve seen the trend over time of people getting more and deeper access to knowledge as each year goes by. I remember, as a student in high school back the in 70’s, the first time I wanted to buy stock in a company. You could only get a quote by calling a broker or visiting the broker’s office. Today you can get real … Read More


OTP @ 2013 Common Platform Technology Forum

OTP @ 2013 Common Platform Technology Forum
by Daniel Nenni on 01-06-2013 at 9:00 pm

Sidense will be exhibiting at the Common Platform Technology Forum in Santa Clara, California on February 5, during which time they will be discussing their one-transistor, one-time programmable (1T-OTP) memory IP products. Based on their patented 1T-Fuse™ bit cell, Sidense antifuse-based 1T-OTP macros offer a secure, reliable,… Read More