WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 524
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 524
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
)
            
cs558723743 serdes ad hs serdes phys ad 800x100px Customsize1 High Quality
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 524
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 524
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
)

HSPICE Users Talking about Their Circuit Simulation Experience

HSPICE Users Talking about Their Circuit Simulation Experience
by Daniel Payne on 02-28-2012 at 4:46 pm

HSPICE users gathered in January 2012 at the HSPICE SIG(Special Interest Group) to talk about their experiences using this circuit simulator for a variety of IC and signal integrity issues. I wasn’t able to attend in person however I did watch the video and wanted to summarize what I heard:

[TABLE] cellpadding=”3″ cellspacing=”3″ style=”width: 700px”
|-
| valign=”top” |
| valign=”top” | Tony Todesco Event Emcee
SMTS Design Engineer, Graphics Silicon Engineering Group
AMD

|-

[TABLE] cellpadding=”3″ cellspacing=”3″ style=”width: 700px”
|-
| valign=”top” |
| valign=”top” | Johann Nittman
Signal Integrity Engineer
Cavium Networks

Using HSPICE for High-speed SERDES Channel Design
|-

Johann worked at DEC on the Alpha CPU, Compaq, HP, Intel. At Cavium they design network service processors (NSP) that use high-speed serial interfaces:

  • PCIE Gen 1 at 2.5Gbps, Gen 2 at 5Gbps
  • D/R/XAUI at 3.125 and 6.25 Gbps
  • Serial Rapid IO at 1.5 to 5Gbps
  • Interlaken at 6.25Gbps
  • Coming soon: Octeon and Neuron to support 10Gbps
  • 3GHz system clocks in use now

On the 10Gbps designs we see more insertion loss:

How to offset the loss? With compensation. Setup for the 10Gbps channel design and measurement were shown along with the BP connectors. From this channel design we can then measure S-parameters.

HSPICE doesn’t support the Impulse Response function so we use instead tools from Debussy:

The blue waveform on the bottom is the result from Matlab and shows good agreement with measurement.

We measured the impulse response of two SERDES channels, an old and newer trace:

We need better results at the connectors. We need a 3D Field Solver to estimate characteristics of connectors.

We were able to model the equalization using HSPICE and simulate it:

De-emphasis is also designed and simulated with HSPICE:

Mostly give customers encrypted HSPICE models, although starting to work with AMI models as well.

  • SERDES channel characterization can be simulated with HSPICE
  • Each application requires a different netlist, chance of introducing errors. Want a GUI and schematic editor to do TDR by mouse-click.

[TABLE] cellpadding=”3″ cellspacing=”3″ style=”width: 700px”
|-
| valign=”top” |
| valign=”top” | Liping Li
Sr. Member of the Technical Staff
Altera

28nm MOSFET Aging Modeling and Simulation Using HSPICE MOSRA
|-

Reliability Analysis – RA, a joint program between Altera/TSMC/Synopsys. As each technology node scales smaller the electric field continues to raise which causes aging issues:

High K metal gate helps reduce leakage effects in 45nm node. All designs using 45nm need to have a signoff for BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection) effects:

NMOS devices have little Gm shift, but most Vt shift. PMOS devices have both Vt and Gm shift.

Your circuit simulator needs to take these effects into account for highest accuracy.

We use the MOSRA approach on a regular netlist and add just two new statements to add Reliability Analysis and Print results:

We use both HSPICE and HSIM to do MOSRA circuit simulations and compare the pre-stress and post-stress results:

There is good correlation between the BTI model results and silicon:

HCI simulated results also match silicon measurements:

On our FPGA designs we see that the recovery effect does change timing by 20%, so it’s important to include this effect:

Output buffers are effected by HCI as a function of temperature and frequency:

  • Both HCI and BTI effects can be modeled with HSPICE and are accurate to silicon measurements.
  • Simulating with MOSRA in both HSPICE and CustomSim worked well in our 28nm process.
  • You need to simulate with MOSRA at 28nm to get accurate timing and current.

[TABLE] cellpadding=”3″ cellspacing=”3″ style=”width: 700px”
|-
| valign=”top” |
| valign=”top” | Randy Wolff
Manager, Signal Integrity R&D Group
Micron

Simulating IBIS 5.0 Power-aware Models Using HSPICE
|-

IBIS (I/O Buffer Information Specification) is at v5.0 and is supported in HSPICE 2010.12. IBIS models are easy to get from component vendors and simulate much faster than full-transistor level netlists.

Here’s what you can see in an IBIS 3.2 model:

This model is signal-centric, not much info on IDD/ISS currents.

IBIS 5.0 adds currents that were missing earlier:

With IBIS 5.0 you can now see currents in your power supplies even before the output switches:

Now in IBIS 5.0 you can model Vgs versus Ids:

I wanted to simulate a DDR3 environment as shown below:

> PART 2 >


Comments

0 Replies to “HSPICE Users Talking about Their Circuit Simulation Experience”

You must register or log in to view/post comments.