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Synopsys Accelerates Innovation on TSMC Advanced Processes

Synopsys Accelerates Innovation on TSMC Advanced Processes
by Mike Gianfagna on 05-15-2024 at 10:00 am

Synopsys Accelerates Innovation on TSMC Advanced ProcessesWe all know that making advanced semiconductors is a team sport. TSMC can innovate the best processes, but without the right design flows, communication schemes and verified IP it becomes difficult to access those processes. Synopsys recently announced some details on this topic. It covers a lot of ground. The graphic at the top of this post will give you a feeling for the breadth of what was discussed. I’ll examine the announcement and provide a bit more information from a conversation with a couple of Synopsys executives. Let’s see how Synopsys accelerates innovation on TSMC advanced processes.

The Big Picture

Advanced EDA tools, silicon photonics, cutting edge IP and ecosystem collaboration were all touched on in this announcement. Methods for creating new designs as well as migrating existing designs were also discussed.

Sanjay Bali, vice president of strategy and product management for the EDA Group at Synopsys had this to say:

“The advancements in Synopsys’ production-ready EDA flows and photonics integration with our 3DIC Compiler, which supports the 3Dblox standard, combined with a broad IP portfolio enable Synopsys and TSMC to help designers achieve the next level of innovation for their chip designs on TSMC’s advanced processes. The deep trust we’ve built over decades of collaboration with TSMC has provided the industry with mission-critical EDA and IP solutions that deliver compelling quality-of-results and productivity gains with faster migration from node to node.”

And Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC said:

“Our close collaboration with Open Innovation Platform (OIP)® ecosystem partners like Synopsys has enabled customers to address the most challenging design requirements, all at the leading edge of innovation from angstrom-scale devices to complex multi-die systems across a range of high-performance computing designs. Together, TSMC and Synopsys will help engineering teams create the next generation of differentiated designs on TSMC’s most advanced process nodes with faster time to results.”

Digital and Analog Design Flows

It was reported that Synopsys’ production-ready digital and analog design flows for TSMC N3P and N2 process technologies have been deployed across a range of AI, high-performance computing, and mobile designs.

To get access to new processes faster, the AI-driven analog design migration flow enables rapid migration from one process node to another. Also discussed was a new flow for TSMC N5 to N3E migration.  This adds to the established flows from Synopsys for TSMC N4P to N3E and N3E to N2 processes.

Interoperable process design kits (iPDKs) and Synopsys IC Validator™ physical verification run sets were also presented. These capabilities allow efficient transition of designs to TSMC advanced process technologies. Using Synopsys IC Validator, full-chip physical signoff can be accomplished. This helps deal with the increasing complexity of physical verification rules. It was announced that Synopsys IC Validator is now certified on TSMC N2 and N3P process technologies.

Photonic ICs

AI training requires low-latency, power-efficient, and high-bandwidth interconnects for massive data sets. This is driving the adoption of optical transceivers and near-/co-packaged optics using silicon photonics technology.  Delivering these capabilities requires ecosystem collaboration.

Synopsys and TSMC are developing an end-to-end multi- die electronic and photonic flow solution for TSMC’s Compact Universal Photonic Engine (COUPE) technology to enhance system performance and functionality. This flow spans photonic IC design with Synopsys OptoCompiler™ and integration with electrical ICs utilizing Synopsys 3DIC Compiler and Ansys multiphysics analysis technologies.

Broad IP Portfolio N2 and N2P

Design flows and communication strategies are critical for a successful design, but the entire process is really enabled by verified IP for the target process. Synopsys announced the development of a broad portfolio of Foundation and Interface IP for the TSMC N2 and N2P process technologies to enable faster silicon success for complex AI, high-performance computing, and mobile SoCs.

Getting into some of the details, high-quality PHY IP on N2 and N2P, including UCIe, HBM4/3e, 3DIO, PCIe 7.x/6.x, MIPI C/D-PHY and M-PHY, USB, DDR5 MR-DIMM, and LPDDR6/5x, allows designers to benefit from the PPA improvements of TSMC’s most advanced process nodes. Synopsys also provides a silicon-proven Foundation and Interface IP portfolio for TSMC N3P, including 224G Ethernet, UCIe, MIPI C/D-PHY and M-PHY, USB/DisplayPort and eUSB2, LPDDR5x, DDR5, and PCIe 6.x, with DDR5 MR-DIMM in development.

Synopsys reported this IP has been adopted by dozens of leading companies to accelerate their development time. The figure below illustrates the breadth and performance of this IP portfolio for the TSMC N3E process. 

SILICON PROVEN SYNOPSYS IP ON TSMC N3E

The Backstory

I was able to speak with two Synopsys experts –  Arvind Narayanan, Executive Director, Product Management and Mick Posner, Vice President, Product Management, High Performance Computing  IP Solutions.

Arvind Narayanan
Arvind Narayanan

I know both Arvind and Mick from my time working at Synopsys and I can tell you together they have a very deep understanding of Synopsys design technology and IP.

Arvind began by explaining how seamlessly Synopsys 3DIC Compiler, OptoCompiler, and the Ansys Multiphysics technology work together. This tightly integrated tool chain does an excellent job of supporting the TSMC COUPE technology. A well-integrated flow that is solving substantial data communication challenges.

It’s difficult to talk about communication challenges without discussing the growing deployment of multi-die strategies.  In this area, Mick explained that there is now an integration of 3DIC Compiler with the popular UCIe standard. This creates a complete reference flow for die-to-die interface connectivity.

Mick Posner
Mick Posner

Arvind touched on the roles DSO.ai plays in the design migration process. For the digital portion, the models and knowledge built in DSO.ai for a design allows re-targeting of that design to a new process node with far less learning, simulation and analysis.  For the analog portion, the circuit and layout optimization capabilities of DSO.ai become quite useful.

Mick said he believes that Synopsys has the largest analog design team in the world. After thinking about it a bit, I believe he’s right. It is a very large team across the world working in many areas. Mick went on to point out that the significant design work going on at advanced nodes across that team becomes a substantial proving ground for new technology and flows. This is part of the reason why Synopsys tools are so well integrated.

To Learn More

You can access the full content of the Synopsys announcement here. In that announcement, you will find additional links to dig deeper on the various Synopsys technologies mentioned. And that’s how Synopsys accelerates innovation on TSMC advanced processes.

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