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High Sigma Yield Analysis and Optimization at DAC

High Sigma Yield Analysis and Optimization at DAC
by Daniel Payne on 06-02-2014 at 7:20 pm

When I hear the phrase “high sigma” I think of the EDA vendor Solido, however at DAC on Monday I visited another EDA company called MunEDAthat has several products of interest to transistor-level IC designers. I was able to speak with three different people from MunEDA and here’s what I learned.


Q: What are the sigma categories today for IC designers looking to achieve high reliability?

Pete Hansen (ex Solido) – there are three categories for high reliability: 0-3 Sigma using traditional Monte-Carlo, high-sigma with 3-6 sigma (where Solido lives), then ultra-high 6-9 sigma (where MunEDA lives).

Q: When was MunEDA founded?

Harald Neubauer – we founded the company in 2002, and it was a spin-out from Technical University of Munich, and our professor helped to start company.

Q: Who was your first customer?

Dr. Frank Schenkel – co-founder of the company, PhD in statistical analysis and optimization. 2002 was the founding year. I’m the CTO and run engineering. We had four founders and I started here straight from University. Our first customer was Infineon, and they used the University tool then requested that a start-up company continue to support it.

Q: I’ve heard about Solido and their approach to high sigma yield analysis, how is your approach different?

At Solido they have a high sigma analysis tool, and it’s really their only tool. It uses a smart sampling technique, and is therefore limited to about 6 sigma results and less, and has not been proven beyond 6 sigma.

We have:

  • circuit analysis & verification
  • circuit & schematic porting
  • circuit modeling
  • circuit sizing plus optimization.

Q: Tell me more about your circuit analysis and circuit sizing.

We use the worst case distance algorithm (WCD), something started outside of EDA, and it’s a very solid mathematical approach. We have a gradient approach and we find that optimal point in the fastest amount of time. WCD started out in civil engineering for construction challenges, then electrical engineering adapted it.

Q: What is your product name?

Our entire tool suite is called WiCkeD(Worst Case Distance), and then there are multiple tools within it to choose from. High Sigma is just one type of our analysis. With our analysis you use your own SPICE simulator: Spectre, Eldo, HSPICE, GoldenGate, BDA, FineSim, UltraSim, XA. Yield optimization is another type of tool where you start by selecting the design parameters for optimization: L and W for MOS devices, and active area for BJT. Operating parameters are PVT (Process, Voltage, Temperature). The IC designer chooses which devices should be optimized, then our yield optimizer goes off and changes the parameters to reach your optimal netlist.

Q: How do I run an optimization?

Start with a netlist, then we analyze the design to see if it’s good enough, if not then we do yield optimization (W, L values auto changed to provide higher yield), we don’t change the topology at all, and we don’t use a sampling approach. We want to limit changes so that the layout parasitics change the least. Optimization run time is limited by waiting for your SPICE simulator to return results.

Most optimizations are run on pre-layout netlists, although the approach can also be run on post-layout. Having the fewest W, L changes reduces the amount of iterations required and allow convergence.

Q: Does the foundry have to supply anything special for your analysis?

Depending on the type of analysis that you need, foundries deliver enough info in their standard models to allow MunEDA to do analysis.

Q: Have you published at conferences?

Yes, MunEDA has published info about their approach for conferences.

Q: How would I do an evaluation of your tools?

Within a few weeks an evaluation can be performed to use the MunEDA tools. A field AE can help train you to use the tool, and figure out which methodology to use (which statistical approach). With Monte Carlo they can see the yield numbers but need some education to understand what the results mean.

An optimizer needs a phase margin, or power consumption, slew rate, frequency, jitter, something tangible to measure to determine if it’s been optimized. Designer adds a .MEASURE statement, then optimizer reads that value. Optimizer runs sensitivity analysis. DC, transient, frequency analysis runs. Optimization results are typically numerical, and you can see the graphical results of performance. Waveforms can be saved from a Monte Carlo analysis.

Q: What customers do you have?

Q: What platform do you run on?

Runs on Linux. Launch all of the SPICE simulation runs using SSH hosts or LSF.

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