Analog IP Design at Moortec

Stephen Crosher started up Moortec in the UK back in 2005 with the help of his former Zarlink co-workers and they set to work offering AMS design services and eventually created their own Analog IP like the temperature sensor shown below:

We spoke by phone last week about his start-up experience and how they approach AMS design.

Interview

Q: How many people are on your IC design projects?
A: From 11-15 people depending on the project.

Q: What does Moortec offer? Who are your customers?
A: Custom design services and analog IP. Large UK and European semi companies (think graphics chips and CPU components).

Q: What type of analog IP do you design?
A: We’ve designed an embedded temperature sensor, PLL and crystal oscillator IP at first.

Q: Describe the background of your IC designers.
A: Our team members have both digital and analog experience.

Q: Where would the temperature sensor IP be used?
A: The temperature sensor is used in several industries: auto, telecom and consumer. This IP is used for most advanced silicon like 65nm, 40nm, 28nm. They basically need to manage thermal run away issues, because current rises with increased temperature so the system will take activity like reduce clock speed, or turn on a fan. This is a growing problem for all kinds of IC designs. An FPGA company could place this on the die, or place several of them around their chips. A temperature sensor IP block can be used during burn-in phase for reliability testing. The digital output makes it an easy IP block to work with.

Q: How could a temperature sensor IP help my packaging decision?
A: If you wanted to change packaging for lower cost and use plastic then a temperature sensor would be used to monitor the die temperature and confirm that you are still in spec. The sensor tells you how the heat is really being dissipated.

Q: For EDA tools, what are you using?
A: We use Synopsys tools like Custom Designer for schematics and layout, and HSPICE for circuit simulation. Custom Simand XA are also used for larger circuit simulation runs like the complete temperature sensor IP.

Q: Why do you use XA for circuit simulation?
A: Speed, because XA will run in 20 minutes on a design while HSPICE would take 15 hours instead. Temperature readings can be in 8 ms per reading.

Q: For backend verification, what tools are used and why?
A: On DRC/LVS we’re using Synopsys IC Validator at the smallest nodes, then Hercules for older 65nm and above. 28nm and below with IC Validator.

Q: Which foundries are you using?
A: Well, the foundries are determined by the customer and design project itself. We are using the iPDK from TSMC in our Synopsys Custom Designer flow.

Q: Are there any issues using iPDK?
A: Not all foundries support iPDKS which can limit our consulting work a bit, but it has not been a problem so far. TSMC leads with iPDK, so now other foundries are adopting it (GF, XFAB, TowerJazz).

Q: How solid is Custom Designer?
A: We think that it’s a pretty solid tool, and the features are equivalent to others (Cadence Virtuoso). We’ve also used Tanner EDA tools a bit.

Q: For configuration management of your IC designs, what do you use?
A: At Zarlink we used ClioSoft SOS, so it was our first choice to use at Moortec also. ClioSoft is used inside of the Custom Designer menus, making it easy to checkin and checkout schematics and layout. The GUI interface is intuitive to use (other freeware tools used Subversion, but gave up on it). The embedded integration makes it look like another feature in Custom Designer.

Q: With ClioSoft what was the learning curve to use the methodology?
A: For training a new user the learning is under an hour to get up to speed.

Q: To setup ClioSoft what is involved?
A: For ClioSoft we have an SOS server setup and then define projects. Our design projects are all in one physical location.

At Zarlink we used ClioSoft in the multi-site capacity. UK, San Diego, Sweden: all synchronized.

Now with VPN tools it is easy to have SOS setup in one location, instead of using multi-site SOS.

Q: What process nodes do you design at?
A: Most of our IP work is done at 65nm, 40nm, or 28nm.

Q: When you release IP to a customer, how do you manage that process?
A: We use Custom Designer plus SOS for IP delivery and we need tight control on our data and how we send a release to a customer. Releasing a temperature sensor IP we tag the entire environment for that release, allowing us to wind back to that exact environment (makes debug easier). We tag our releases for the temperature sensor with a version number like v1.2

Q: Is the release process different for full chip?
A: At the chip level we can tape out to a foundry and freeze/tag the entire design environment. If we need to go back to that tapeout we can easily do it.

Q: How large are your design databases?
A: Our design databases are reasonable in disk size, and we have a methodology to allow us to populate just the parts of the database each designer needs.

Q: What is the time required for your IC projects?
A: Typical design projects can be from 2 months to 10 months, it really depends on the performance and size. A project could be one person up to several designers.

Q: What would you like to change with your IC design environment?
A: iPDK availability is very important for us, so more companies joining will ensure an easier time for us to make our IP work on more fabs.

Q: Does iPDK help you port designs to new nodes?
A: Yes, we’ve designed our temperature sensor at 65nm, 40nm then 28nm all at TSMC. We could use iPDK at each node, then run a script to quickly move between nodes (thank you Synopsys). We still had to do much simulation and tweaking before meeting the specs.

Q: Have you used any cloud computing for IC design?
A: The concept of the Cloud for HSPICE or XA would be interesting, but we haven’t pursued it yet.

Q: What has EDA support been like for you?
A: Support from both SNPS and ClioSoft has been very good for us.

Q: Tell me about the hardware used for your EDA tools.
A: We are running Linux on RedHat and have a farm of machines with multi-core processors.

Q: For your analog IP – how do you define testability?
A: We use test chips to fully characterize the analog performance. We define a good test strategy through simulation. On the temperature Sensor our parts can be tested using the trim interface. The core analog is precision analog.

Q: How does noise factor into your design methodology?
A: During design we do inject some supply noise into our analog IP, also input signal noise, to see how robust it is.

Q: How do you make your designs robust?
A: During design we run monte-carlo simulations to determine if our design is centered.

Summary
Moortec uses EDA tools from multiple vendors to deliver analog IP and design services all the way down to the 28nm node. iPDK allows them to mix and match EDA tools then target foundries like TSMC, GLOBALFOUNDRIES, Tower-Jazz and XFAB.

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