With the adoption of the 32/28 nm process node, some significant new challenges in digital routing arise—including complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion transistor) designs. To meet quality, time-to-market, and cost targets, design teams must adopt new routing technologies that can solve for multiple design objectives within the scope of required tool capacity, memory footprint, and runtime.
A router must be flexible and robust to effectively deal with the growing DRC/DFM rule count and complexity at sub-nanometer nodes. To ensure optimization of all design parameters across all process and operational modes and corners, the router should be multi-mode, multi-corner (MCMM) aware. The router should also have signal integrity (SI) costing native to the routing kernel, to enable dynamic and incremental MCMM SI analysis. Incremental, on-the-fly extraction, polygon-based DRC analysis, and MCMM timing analysis are also essential to make quick decisions on issues such as wire spreading and rerouting critical nets.
Another key requirement for 28nm routing is the support for all of the DFM requirements including recommended rules, pattern matching, redundant vias, wire spreading and widening, timing-aware metal fill, and sophisticated non-default rules (NDRs). Finally, because of the growing design sizes, routers need to use multiple cores and CPUs and physical memory very efficiently. The requirements of a routing system for 28 nm are illustrated in Figure 1.
Figure 1. A convergent routing flow for advanced-node designs.
Nanometer Routing Challenges and Solutions
The primary challenges at 28 nm that require new routing technologies include:
• Growing number of DRC/DFM rules and rule complexity
• Poor estimates for global route resources
• Disconnected physical signoff and engineering change order (ECO) iterations
• Huge design sizes and long runtimes
Growing DRC/DFM Requirements
Design rules and DFM requirements correct for the manufacturing defects (parametric, systematic, and random) that occur when trying to print sub-wavelength features. The number of design rules has roughly doubled between the 90 nm and 28 nm nodes, and model-based DFM analysis is becoming mandatory. In addition to the mandatory DRC, for 28 nm foundries also provide “recommended rules” – soft rules that improve yield. Although the recommended rules are discretionary, if these rules are not honored by the router it can have a direct impact on the design yield.
The routing engines should support all the complex 32 nm and 28 nm design rules and at the same time control the impact on runtime. One method is to use algorithms that intelligently minimize the number of operations performed during routing. The router should make use of the full DRC/DFM models during all stages of routing for better accuracy and to minimize violations that need to be fixed during post route optimization and signoff. The DRC engine should use polygon shapes rather than edge-to-edge checks, which enables complex 28 nm rules to be represented and adhered to effectively.
In addition to the default hard rules, the router should also support recommended rules and corresponding rule priorities. Automatic routing repair should be performed based on the priority as defined by the foundry or the user to ensure the best DFM score.
Global Routing Estimation
Before creating detailed routes, routing tools perform a ‘global routing’ step to estimate the available routing resources. These global routing estimates must be accurate, which means more than simply counting the number of routing tracks across the chip that meet minimum spacing requirements. Some routing engines use only a subset of the foundry design rules in a simplified form for global routing, and invoke the full set of DRC rules only for detail, or final routing. The result is poor correlation between early estimates and final routing results and ultimately, routing closure problems.
A timing- and congestion-aware 3D global router is best at estimating routing layer resources. The global router should use the complete set of DRC/DFM rules, including recommended rules, to avoid intractable DFM problems that typically are found as late-stage surprises. The router should use new modeling technologies to ensure that the resources consumed by vias, stacked via patterns, blockages, and staggered macros are accounted for when calculating resource availability.
Efficient Physical Signoff and ECO Iterations
Another key challenge at 28 nm is a result of the traditional decoupling of the routing and the signoff verification engines. Typically, a router uses simplified DRC and DFM models to provide the optimal trade-off between runtime and accuracy during routing. Once the implementation is complete, the GDSII layout is verified using signoff-quality DRC/DFM models and Standard Verification Rule Format (SVRF) rule decks. For previous nodes, this worked adequately because the number of violations discovered at signoff was relatively low.
Designers are also finding that DFM techniques, including metal fill/CMP, litho, and critical area analysis, are starting to affect the traditional design metrics like timing, power, and signal integrity. These challenges are made worse by the fact that there is no automated way to repair the DRC/DFM violations, and the traditional flow requires the transfer of huge ASCII files between the implementation and signoff environments, which slows the design process. In summary, the design-then-verify flow that has worked in the past is increasingly unmanageable and unpredictable.
Advanced IC designs need the physical signoff engines to be directly integrated in the place and route environment to natively perform SVRF-based DRC and DFM analysis. Access to the actual signoff engines running golden SVRF rule decks is the key to the effectiveness of the platform. This ensures that all manufacturability issues are addressed without introducing new ones, and without degrading the performance of the design. It significantly speeds up the manufacturing signoff process, and delivers higher quality results with faster time to market.
Capacity and Turn-Around-Time
A routing solution must also have an extremely efficient and scalable data model to handle huge design sizes. The number of operations the router must perform at 28 nm is nearly four times more than what was required at the 65 nm node. One technique for maintaining the routing runtime is a method for clustering and filtering rules. Rather than applying each rule separately, a more intelligent tool can detect rule commonalities and group them for more efficient processing.
Another performance factor is the efficient use multiple CPUs. Figure 2 illustrates the speedup that can be achieved for different CPU configurations when the router architecture has a very efficient data model and is built for maximum parallelism.
Figure 2. Routing speedup with Multi-CPU runs using the Mentor Graphics’ Olympus-SoC place and route system.
Advanced process node designs face a raft of significant routing challenges due to the increased number and complexity of DRC/DFM requirements, increased design sizes, and multiple design goals. Routers for 28 nm must offer a flexible and powerful architecture to address these concerns and achieve optimal QoR across all design metrics in the shortest time.
— By Alexander Volkov, Principle Technologist, Mentor Graphics Place and Route Division.
For more information about Mentors Graphics’ routing technology, see the whitepaper “Routing Technology for Advanced-Node IC Designs“.