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WP_Term Object
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1257
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1257
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0

The Big Three Weigh in on Emulation Best Practices

The Big Three Weigh in on Emulation Best Practices
by Mike Gianfagna on 08-18-2020 at 10:00 am

Emulation Best Practices

As software content increases in system-on-chip and system-in-package designs, emulation has become a critical enabling technology for the software team. This technology offers software developers the opportunity to verify their code in against a high-fidelity model of the target system that actually executes fast enough to run real application software scenarios. The opportunity for system validation, performance improvement and power reduction with an emulation approach are substantial and often deliver the margin of victory for complex projects. So, the opportunity to hear the big three weigh in on emulation best practices is not to be missed.

Of course, I’m referring to Cadence, Mentor and Synopsys as the big three and they presented at one of SemiWiki’s Best Practices webinars. Hearing the perspective of all three in one webinar is quite a treat. The webinar will be aired on Tuesday, August 25, 2020 from 10:00 AM – 11:00 AM PDT. I highly recommend you register for this webinar.

You will be treated to a series of thoughtful overviews on the topic by some truly world-class speakers. The background on the presenters deserves a bit detail.

Shantanu Ganguly presented for Cadence. He is the lead for the Systems and Verification Group’s product engineering organization. He is responsible for product definition, new technology deployment, and engagement management for all verification technologies. Prior to Cadence, he led emulation and verification applications at Synopsys. He also spent about 11 years at Intel, including work on the ATOM SoC design. He led SoC physical design and tapeout at Qualcomm and was a CAD manager and Sun Microsystems and Motorola Semiconductor. Shantanu  began his career as a consultant at Bell Labs working on layout verification automation. He holds a Bachelor of Technology degree from the Indian Institute of Technology, Kharagpur and a PhD in computer engineering from Syracuse University.

Jean-Marie Brunet presented for Mentor, a Siemens Business. He is the senior marketing director for the Emulation Division. He has been with Mentor for 15 years. Prior to that, he led applications engineering and design services at Silicon Design Systems, was a director of engineering at Micron Technology, director of product development at Music Semiconductors and business development manger at Cadence. His career began at ST. He holds an MS/EE degree from Institut supérieur d’électronique et du numérique.

Melvyn Goveas presented for Synopsys. He is the emulation lead system architect there. Before joining Synopsys, he worked at Intel where he drove emulation and simulation acceleration technology development and application to enable validation shift-left across multiple business groups and helped advance the state-of-the-art in the industry. He holds an MS and BS degree in electrical and computer engineering from the University of Texas at Austin.

With a cast like this, there’s a lot to learn about emulation best practices. I’ll just give you a few highlights from each presentation. You really need to see the webinar for yourself to get the full benefit.


Shantanu spent some time discussing the various usage scenarios for emulators. He pointed out there isn’t one platform that is best suited for every scenario. The type of regression or debug you plan to accomplish will influence the configuration and utilization of your platform and the way you handle the data. He gave many example applications and how to approach them. Shantanu then provided the details of an example design flow. He also explored the various components of the Cadence verification platform.


Jean-Marie began with an overview of the latest emulation best practices. He touched on topics such as power profiling and analysis under real workloads with real-world examples running during the discussion. He also discussed the strategy and benefits of the Mentor + Siemens autonomous vehicle PAVE360 digital twin program. Jean-Marie also discussed the specific verification needs of 3DICs and how emulation can address those needs.


Melvyn started his presentation with a story about his first emulation project on the first commercial emulator over 30 years ago. Things have clearly changed a lot. He then looked at how emulation has advanced over the years, taking into account the various standards that have influenced the use models. He also discussed the underlying technology used in emulators and how changes there unlocked new opportunities.

The webinar also has some great Q&A sessions. What I’ve presented here is a small portion of the content presented by three very accomplished technologists. As I’ve mentioned, the opportunity to hear the big three weigh in on emulation best practices is not to be missed.

I encourage you to experience the entire event by registering for the webinar here.

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Cadence on Automotive Safety: Without Security, There is no Safety

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