Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform there was a presentation from John Park, Methodology Architect at Mentor Graphics called –A Platform for the CoWoS Reference Flow.
There are six issues that EDA tools need to help automate for 3D-IC designs:
- Planning, assembling and optimizing interposer-based designs
- P&R support for TSV, microbumps, silicon interposer redistribution layer (RDL) and signal routing
- Multi-die integration and the need for a 3D-IC cockpit
- New extraction challenges and modeling of silicon interposers and through silicon vias (TSVs)
- Test infrastructure insertion to support test access to die test features within the package
- Testing TSVs, interposers and inter-die connections, and reusing die patterns after packaging
The CoWoS reference flow at TSMC has several pieces shown below in grey, with detailed issues shown in red:
Mentor offers technology in the box called Custom Design using full-custom layout and routing with the Pyxis tool.
To implement CoWoS requires the following steps:
Floor plan / APR
Olympus-SoC is the Mentor tool that automates routing for the interposer using microbumps and C4 bumps.
The DRC (Design Rule Checking), LVS (Layout Versus Schematic) and RCX (Resistance, Capacitance eXtraction) tasks are handled with Calibre from Mentor.
TSV (Through Silicon Vias) can be modeled in three ways:
- Single TSV models
- Pro: easy to integrate into a flow, sufficient for low density TSVs
- Con: not adequate for high density, high frequency designs
- Compact parameterized TSV models
- Pro: can account for some interactions, faster than a field solver
- Con: cannot account for all interactions
- Field solver based TSV extraction
- Pro: highest accuracy
- Con: Slower run time, integration
Design For Test
Under the Tessent name Mentor has several technologies:
- Test Compression
- Netlist editing
- IEEE P1687 (IJTAG) for test control interface
- Memory BIST for the wideIO RAM
- Scan switch network with RPCT
- Logic die to logic die interconnect tests
- Logic die to memory die JEDEC-based interconnect tests
- Contactless IO leakage test
This is an area under development right now at Mentor, so stay tuned for new ways to do CoWoS co-design. It will be interesting to see how the PCB and IC worlds are either converged or integrated.
IC – Package – PCB Co-Design Cockpit
TSMC has partnered with Mentor and Cadence to create a platform for the CoWoS reference flow. I’m eager to see how first silicon works on the test chip.