WP_Term Object
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 424
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 424
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 1

Electromigration (EM) with an Electrically-Aware IC Design Flow

Electromigration (EM) with an Electrically-Aware IC Design Flow
by Daniel Payne on 11-03-2012 at 4:05 pm

Electromigration (EM) is a reliability concern for IC designers because a failure in the field could spell disaster as in lost human life or even bankruptcy for a consumer electronics company. In the old days of IC design we would follow a sequential and iterative design process of:

  • Size the transistors on a schematic
  • Layout the transistors and route the interconnect
  • Extract the parasitics
  • Run EM analysis
  • If the EM limits for interconnect are violated then return to step 1 or 2, repeat as needed

    David White and Akshat Shah from Cadence wrote an article in EE Times last week that examines this sequential approach and then shows an electrically-aware IC design flow for EM that takes less time.

    EM Overview

    Figue 1: Open Circuit Failure

    Figure 2: Short Circuit Failure

    These opens and shorts in metal layers of an IC are caused when current flows and the electrons collide with metal atoms. Failure is related to the current per unit area, and as the metal atoms are moved from their lattice position it will degrade the interconnect as the resistance increases.

    EM limits can be reached in the metal interconnect, or in the vias connecting metal layers. The metal interconnect width, length, height and resistivity all play a part in determining its EM limit. EDA tools for EM analysis have to take all of these complex factors into account.

    EM Example
    Here’s an MOS device layout that has been analyzed and then colorization added to show EM passing in Green to EM failing in Red:

    Figure 3: An MOS device failing EM limits

    This failure was caused by where the large interconnect reached the MOS device. By changing the routing of the interconnect to be in the middle of the MOS device the EM limits are safely met:

    Figure 4: An MOS device passing EM limits

    Electrically-Aware EM Flow
    Here’s a new flow that calculates EM viability as the interconnect is incrementally made or modified:

    Figure 5: Electrically-aware IC design flow

    An IC designer could use this flow in three ways:

    • Manually IC layout
    • Assisted EM feedback while performing IC layout
    • Automatic EM enforcement

    With this electrically-aware IC design flow you will see the interconnect and vias colorized in passing (Green) or failing (Red) colors as shown in figures 3 and 4. A designer could manually re-route or re-size a wire then see the results of EM analysis interactively, instead of using a batch process.

    In the assisted flow the tool flags all EM violations and offers suggestions to fix each one, which can then be approved.

    The old style of batch-oriented IC design and EM analysis is just to slow to converge in enough time, so the newer approach of incremental and interactive EM closure is a welcome relief in creating reliable electronic products, quickly.

    Further Reading
    We’ve blogged over 20 articles on electromigration (EM), just type “electromigration” into the Advanced Search field.

  • 0 Replies to “Electromigration (EM) with an Electrically-Aware IC Design Flow”

    You must register or log in to view/post comments.