WP_Term Object
(
    [term_id] => 159
    [name] => Mentor, a Siemens Business
    [slug] => mentor-graphics
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 503
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 503
    [category_description] => 
    [cat_name] => Mentor, a Siemens Business
    [category_nicename] => mentor-graphics
    [category_parent] => 157
    [is_post] => 1
)

Mentor Extends Verification Offering!

Mentor Extends Verification Offering!
by Daniel Nenni on 03-14-2016 at 12:00 pm

With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better to use independent VIP that is used by multiple IP vendors because you REALLY know it will work?


I had this discussion again at DVCon amongst the masses and the consensus was that independent VIP is preferred, to which I wholeheartedly agree with but quite often VIP is bundled in with the IP if the vendor has both. In fact, that type of bundling seriously thinned the independent VIP herd which was quite apparent at the exhibit hall this year. The other crushing competitive force is the integration of VIP into the mainstream verification cycle including emulation.

For further clarification I met with Mark Olen and Jason Polychronopoulos from Mentor’s Verification Division. Mark and Jason are both very interesting men and very approachable so if you have any questions for them put it in the comment section and I will make sure you get a response.

Mark and Jason were at DVCon to push the availability of the:

First entirely native UVM SystemVerilog memory verification IP library for all commonly used memory devices, configurations, and interfaces. Mentor is adding over 1600 memory models to theMentor[SUP]®[/SUP] Verification IP(Mentor VIP) library that already supports over 60 commonly used peripheral interfaces and bus architectures. As a result, Mentor becomes the first company to supply ASIC and FPGA SoC designers with a complete UVM SystemVerilog verification IP library that covers the breadth of their peripheral interface, bus protocol and memory device needs. Providing the complete library in one consistent industry-standard format reduces the time it takes for engineers to set up verification runs, so they can focus on verifying unique, high-value parts of their designs.

“The vast majority of ASIC and FPGA project teams have moved to standard UVM SystemVerilog verification methodology, and until now have been unable to find a universal VIP library that supports bus protocols, peripheral interfaces, and memory devices, all in native UVM,” says Mark Olen, Mentor Graphics product marketing manager, Design Verification Technology Division. “Judging from initial adoptions of our new memory VIP library, it’s easy to see why verification IP is one of the fastest growing sub-segments in the functional verification market, now exceeding $110 million in annual spending, according to the Electronic Design Automation Consortium.”

We went through the slides, which they were nice enough to give me so you can find them HERE. The key takeaway from our discussion is two-fold for me: First and foremost Mentor is the leader in verification and VIP is now an integral part of that. Second, Mentor does not compete with their IP partners so not only do they have an early and intimate relationship with ARM, Northwest Logic, PLDA, etc…, Mentor also offers truly independent IP verification.

Again, post questions in the comment section and I will make sure they are answered, absolutely.