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July 13, 2022January 11, 2023

Silicon Catalyst Angels Turns Three – The Remarkable Backstory of This Semiconductor Focused Investment Group

Silicon Catalyst Angels Turns Three – The Remarkable Backstory of This Semiconductor Focused Investment Group
by Mike Gianfagna on 07-13-2022 at 8:00 am
Categories: Semiconductor Services, Silicon Catalyst

The Silicon Catalyst Angels investment group recently announced the completion of three years of operation. There are great statistics associated with the organization and its financial results. This includes an over 4X increase in members since inception and an impressive list of investments. One of the noteworthy attributes of the Silicon Catalyst organization is its ability to build a collaborative ecosystem to nurture the startups in the incubator. Silicon Catalyst Angels has a similar DNA, which is quite unique in the investment community. Read on to better understand the remarkable backstory of this semiconductor focused investment group.

The Angel group is a separate corporate entity from Silicon Catalyst, with membership by accredited investors that have deep strategic and operational experience from their many years in the semiconductor industry. You can learn more about Silicon Catalyst on SemiWiki. Recently, I had the opportunity to explore the history and accomplishments of Silicon Catalyst Angels with some of its leadership. I was able to speak with Pete Rodriguez, CEO of Silicon Catalyst, and the board of directors at Silicon Catalyst Angels, a rather impressive team. What follows is a summary of our discussion.

The Beginning

Pete explained that when he joined Silicon Catalyst in 2017 the organization was focused on helping to craft a strong business plan for the early-stage companies in the incubator. Another goal was to provide In-Kind Partner services to remove the immediate use of scarce funds for EDA and TSMC shuttles. As is the case, the need for working capital to cover the operational costs of startups is always front and center – true then and even more so in today’s markets.

Early in the history of Silicon Catalyst, there were 20 investment groups (institutional and corporate VCs) in their ecosystem. Among them was Sand Hill Angels. Laura Swan, one of the partners at Silicon Catalyst, was also part of Sand Hill Angels, as were several other partners at Silicon Catalyst and its advisor network. Building on the procedures developed by the established Silicon Valley investment groups, Sand Hill Angels and Band of Angels, in early 2019 the board of managers at Silicon Catalyst decided to create an angel investment group, based on the plan that was developed by Richard Curtin, one of the managing partners at Silicon Catalyst. Silicon Catalyst Angels (SCA) investment group was then launched in July 2019, as a separate corporate entity, to enable accredited investors to help fund the semiconductor startups.

The SCA board of directors includes Amos Ben-Meir as president, a long-time member of Sand Hill Angels, bringing deep investment experience, with over 200 angel investments under his belt. Additional board members include Raul Camposano and Michael Joehren, along with Laura Swan, as VP of operations. The deal flow was initially targeted to hear pitches from the companies in the Silicon Catalyst Incubator but has now expanded to selectively invite other semiconductor startups not currently in the Incubator. These organizations pitch for seed funding from Silicon Catalyst Angels members. With low membership investment commitments and low annual dues, the Silicon Catalyst Angels investment group was off and running.

Building Momentum

The initial challenge was to attract new members to the investment group. The feeling was that many of the technology investors in the Silicon Catalyst ecosystem didn’t get involved with other angel groups because the fees and investment requirements were too high and, most importantly, they would rarely see a semiconductor company as a candidate, the area that this community knew a lot about. The laser focus of the Silicon Catalyst Angels group on semiconductor investments seems to have paid off. While most of the investments have been for Silicon Catalyst incubator companies, startups outside the organization have approached Silicon Catalyst Angels because of its reputation as being semiconductor savvy. This becomes another avenue for the startups to explore joining the incubator, as well as to pursue seed funding.

As any savvy investor understands, whether in semis or elsewhere, due diligence is key. With the extensive semiconductor industry expertise of the members, the Silicon Catalyst Angel group uniquely offers a level of drill-down to assist in de-risking potential investments.

The syndication of investments by angel groups is a potent strategy that is rare elsewhere, but common for Silicon Catalyst Angels. At present, this group has made multiple rounds of investments in 12 companies, with an above-industry-average IRR. The investments from the syndication of these SCA deals are an even greater dollar amount – heavily leveraging the investor ecosystem to the benefit of the startup.

Laura Swan, VP of business operations at Silicon Catalyst Angels, provided additional perspective on this during her time at Sand Hill Angels, prior to joining Silicon Catalyst. As an “outsider” at that time, there were several reasons to join a deal associated with Silicon Catalyst and its angel investment group:

Laser-focus on semiconductors, a complex and difficult subject to master for an investment team who typically looks at software deals
Silicon Catalyst’s advisor network further reduces risk
The Silicon Catalyst In-Kind Partner program delivers substantial monetary value, reducing the amount of investment capital needed and increasing investment leverage

All members of Silicon Catalyst Angels also get access to the Angel Capital Association, a highly respected and valuable resource to help educate angel investors and to ensure that industry best practices are well understood by its members.

Thanks to the chip shortage and responses at the political level, such as the CHIPS Act, semiconductors have become more mainstream and more widely known. It turns out Silicon Catalyst Angels is at the epicenter of this renewed interest.

What’s Next?

We also touched on the type of deals being looked at by Silicon Catalyst Angel members. To borrow from the Silicon Catalyst tagline, it’s about what’s next. And Silicon Catalyst Angels sees the very newest ideas which suggest what’s next. As an R&D solutions architect at Renesas Electronics, Silicon Catalyst Angels board member Michael Joehren was able to offer an industry view. The group is seeing far more measurement technology that leverages MEMS advances. Generally, the focus is on the blending of biotech and healthcare with a dose of high-performance bandwidth for information delivery.

Michael explained that while there is continued interest in things like glucose meters, semiconductor-assisted measurement is expanding. Chemical analysis for air quality is a good example. There are many new standards in this area and vast networks of sensors are the only practical way to achieve compliance. Raul Camposano, another board member, explained that materials research is focused on other areas such as battery design. He also offered that the ability to literally print molecules takes massive compute capability that drives a lot of new work as well, with interesting investment opportunities at the intersection of life sciences and semiconductors.

I concluded my discussion with a “crystal ball” question. What impact will the current financial climate have on the future of semis and the associated technology? There was a lot of perspectives offered, but the general feeling was that the semiconductor industry is cyclic in nature. We are just experiencing another cycle. Yes, and now there are geopolitical aspects to also consider. At the end of the day, the growing combination of semiconductors and life sciences will continue to drive innovation, growth and the opportunity for financial and social gain.

So, there’s a bit of the remarkable backstory of this semiconductor focused investment group. There are exciting times ahead. If you’re interested, to learn more about membership details or for startups looking to pitch, contact Silicon Catalyst Angels.

July 13, 2022July 13, 2022

3D Device Technology Development

3D Device Technology Development
by Tom Dillinger on 07-13-2022 at 6:00 am
Categories: Events, Foundries, Intel Foundry

The VLSI Symposium on Technology and Circuits provides a deep dive on recent technical advances, as well as a view into the research efforts that will be transitioning to production in the near future. In a short course presentation at the Symposium, Marko Radosavljevic, from the Components Research group at Intel, provided an update on the development status of 3D device fabrication, in a talk entitled “Advanced Logic Scaling Using Monolithic 3D Integration”.

Although there are significant challenges yet to be addressed, Marko provided a compelling perspective that 3D device topologies will be the successor to the emerging gate-all-around (nanosheet/nanoribbon) device. This article summarizes the highlights of Marko’s presentation.

Introduction

Marko provided a brief recap of recent process technology developments that have led to the current FinFET devices, and to the upcoming GAA topology. The first figure below lists these device scaling features, while the next figure illustrates a cross-sectional view of the FinFET and GAA device stack. (Four vertical nanosheets are illustrated, for the adjacent nFET and pFET devices.)

The GAA topology improves upon the device leakage current control compared to the “tri-gate” surface of the FinFET. (Additional process engineering steps are typically integrated to reduce the substrate surface leakage current for the device gate material between the bottom of the lowest nanosheet and the substrate.)

Also, as depicted in the figure below, the GAA lithography and fabrication offer some flexibility in the width of the nanosheets in the stack. Unlike the quantized width of the FinFET device (w=(2*h)+t), designers will have greater flexibility in optimizing circuits for specific PPA goals.

The figure above also highlights some of the GAA process challenges, specifically the steps which are unique compared to FinFET fabrication:

- an initial Si/SiGe epitaxial stack
- partial recessed etch of the sacrificial SiGe, exposing the ends of the Si layers for epitaxial growth of the source/drain nodes

FinFETs also use selective epitaxy to expand the S/D nodes – yet, the fins are already exposed on either side of the gate. The GAA device requires a very precise lateral etch of the interspersed SiGe layers to expose the Si surfaces prior to S/D epitaxy.

- removal of the remainder of the sacrificial SiGe to “release” the nanosheet surfaces (supported by the S/D epi)
- precise deposition of the gate oxide and surrounding gate metal on all nanosheet surfaces

Note in the figure above that multiple metal gate compositions will be deposited to provide different workfunction surface potentials, for different device Vt thresholds.

3D Devices

With that background, Marko shared the graphic below, indicating that the next process roadmap device evolution would be to 3D stacked nanoribbons, leveraging the process development experience gained in the lateral pFET and nFET device fabrication. The 3D stacked devices are typically denoted as a “CFET” (complementary FET) structure.

The figure below provides illustrations of how vertical device stacking could have a significant area scaling factor compared to lateral nanosheet layout, both for a logic cell and an SRAM bitcell (a 1-1-1 device configuration for the transfer gate-pullup-pulldown in the 6T cell).

The figure below expands upon the logic inverter layout above, to show the devices in cross-section. Note the presence of buried power rails (BPR) providing VDD and VSS to the devices. Also, note the significant aspect ratios required for contact etch and metal fill.

CFET R&D Initiatives

Actually, there are two very distinct approaches being evaluated for fabrication of CFET devices – “sequential” and “monolithic” (or self-aligned).

- sequential 3D stacking

The figure below illustrates the sequential process flow. The bottom devices are fabricated first, followed by the bonding of a (thinned) substrate for fabrication of the top devices. An oxide dielectric layer is deposited and polished on the starting substrate for the bonding process and to serve as the electrical isolation between the devices. The presence of the bottom devices constrains the thermal budget available for top device fabrication.

Of particular interest to researchers is that this approach offers the opportunity to utilize different substrate materials (and potentially different device topologies) for the two device types. For example, the figure below shows a (top) pFET fabricated using a nanosheet device in a Ge substrate with a (bottom) nFET using a FinFET structure.

In the example above, the pFETs in the Ge nanosheets would be fabricated using a starting stack of Ge/SiGe layers, with SiGe again serving as the sacrificial support for source/drain growth and nanosheet release. This technology option would leverage the higher hole mobility in Ge compared to Si.

The bonding dielectric thickness separating the two device layers is a key process optimization parameter – a thin layer reduces parasitic interconnect resistances and capacitances, yet needs to be defect-free.

- self-aligned monolithic 3D stacking

The figures below illustrate a cross-section of a monolithic self-aligned CFET structure, and a high-level process flow description. (The SiGe layer in the middle is sacrificial.)

Two key process steps unique to the monolithic vertical device structure that are highlighted in the figure above are the distinct nFET and pFET S/D epitaxy growth and the gate workfunction metal deposition.

The figure below illustrates S/D epitaxial growth process for the two device types. The top device nanoribbons receive a blocking layer prior to the bottom device S/D epitaxial growth. Then, this blocking layer is removed, the ends of the top nanoribbons are revealed, and the top device S/D epitaxy is grown. The figure also includes a confirmation that the p-epi and n-epi regions did not receive dopants from the other epitaxial growth step.

The figure below depicts the sequence for gate metal deposition. Metal initially deposited on both device types is subsequently removed for subsequent deposition of a different workfunction gate metal for the second (top) nFET.

Experimental data illustrating the range of multiple Vt device characteristics for monolithic nFETs and pFETs is shown below.

Although CFET device technology promises continued improvements in PPA over the upcoming nanoribbon process nodes, a key consideration will be the ultimate cost of the CFET device topology. Marko presented the following cost estimate comparisons, part of a collaboration with IC Knowledge LLC. The category breakdowns are: lithography, deposition, etch, CMP, metrology, and other. Note that the CFET examples include a BPR distribution, opening up additional cell tracks for signal routing. The major contributors to the sequential CFET cost difference are the wafer bonding and separate top device processing.

In total, the PPAC benefits of CFET fabrication look compelling, over though the total CFET process cost is higher. (A more challenging tradeoff is whether the flexibility afforded by sequential CFET device fabrication with different substrates will warrant the additional cost.)

Summary

Although process development challenges remain to be solved, a CFET device process roadmap appears to be a natural extension to the nanoribbon devices soon to achieve production status.

At the recent VLSI Symposium on Technology and Circuits, Intel presented both their R&D results and experimental data from other researchers demonstrating a compelling PPAC benefit. The longevity of FinFET devices will have lasted a little more than a decade through seven process node generations, as depicted below.

To date, roadmaps for nanoribbon devices depict (at least) two nodes.

The benefits of CFET devices and the leverage of nanoribbon fabrication (and modeling and EDA infrastructure) expertise may result in a shorter longevity for nanoribbons.

-chipguy

Also Read:

Intel Foundry Services Puts PDKs in the Cloud

Intel 4 Deep Dive

An Update on In-Line Wafer Inspection Technology

July 12, 2022September 11, 2022

What’s New With Calibre at DAC This Year?

What’s New With Calibre at DAC This Year?
by Daniel Payne on 07-12-2022 at 9:00 am
Categories: EDA, Events, Siemens EDA

When I worked at EDA vendors and attended DAC, one of the most popular questions asked in the booth and suites was simply, “What’s new this year?” It’s a fair question, and yet many semiconductor professionals are so focused on their present project, using their familiar methodology, that they simply aren’t aware of all of the industry changes, and specifically EDA tool updates. I was made aware of several changes to the popular EDA tool family called Calibre RealTime and Calibre Recon from Siemens EDA, announced this week at DAC, so here’s my take on them.

What’s Changed

In the past two decades of semiconductor design we’ve moved beyond the simple EDA requirements of getting a cell, block and chip to be DRC clean, LVS clean and DFM ready with dummy fill. In leading-edge process nodes the types of analysis and number of foundry rules have just exploded, and IC masks started using Double Patterning (DP), Multi-Patterning (MP) and finally EUV.

Complexity Changes over Time

Calibre RealTime Custom

The earliest Design Rule Check (DRC) and Layout Versus Schematic (LVS) tools were designed to be run in batch mode, so engineers submitted their jobs, went to lunch, then in the afternoon viewed the errors and communicated with the layout designers on what and where to fix each violation. Sounds too labor intensive and time consuming.

In recent years the new idea of running these DRC and LVS checks live, while the layout designer was working on the physical design came into vogue, bringing along a more efficient methodology, saving time by having near instant feedback, instead of waiting for a batch job to finish in a queue. The big question with a real time running of DRC has always been, “Are these checks approved by the foundry, and are they complete or just a reduced subset of the rule checks?”

The new productivity feature with Calibre RealTime Custom is that it now automatically tracks DRC across multiple regions, so that multiple edits can be fixed, tracked and checked simultaneously. This enables a team-approach to reaching DRC clean in real time possible, and the benefit is saving precious time. Oh, and the checks are signoff-quality too.

Calibre RealTime Digital

Design For Manufacturing (DFM) requires that the IC surface be more planar, instead of having hills and valleys, so adding dummy fill was a starting point for automating. Advanced nodes down to 3nm require more than dummy fill, and now Calibre RealTime Digital supports in-design fill by using the Calibre Yield Enhancer SmartFill, so designers enjoy a foundry signoff fill by using the design cockpit. It’s a faster way to be DFM ready.

Calibre nmDRC-Recon

Alex Tan blogged earlier about Calibre Recon here, and it’s a way to reduce the number of DRC checks and violations, in order to pinpoint the biggest layout issues first. The new feature with Calibre nmDRC-Recon when using Calibre RealTime Digital is that you can “gray-box” out some of your cells and blocks that are still works in progress, while still checking DRC for all the connections to adjacent blocks and even the upper-level metal layers. Fast feedback, earlier.

Calibre nmLVS-Recon

Finding a fixing interconnect shorts using Calibre LVS was blogged by Tom Dillinger earlier. What’s new with Calibre nmLVS-Recon is that you can run short isolation (SI) mode several times per day, instead of waiting overnight for results. Designers continue to use the same design inputs and foundry rule decks as before, so it’s simple to learn and get running with earlier results.

Summary

Calibre has quite a broad family of tools, where each one is optimized for a specific physical verification or reliability task. What started out as only a batch-oriented EDA tool, has now blossomed into interactive versions that provide earlier feedback and faster times to a clean IC design and layout. New features have been added and announced at DAC this year, so the automation benefits just keep growing to tackle all of the new process node complexity increases. The Calibre tools also work inside of your favorite IC layout, design and physical implementation tools, while providing a consistent UI experience, so go ahead and mix-and-match vendors.

If you attend DAC this year in San Francisco, then make your way over to the Siemens EDA booth, it’s #2521, located on the second floor. Ask the experts in the booth, “So, what’s new this year?”

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July 12, 2022July 18, 2025

Intelligently Optimizing Constrained Random

Intelligently Optimizing Constrained Random
by Bernard Murphy on 07-12-2022 at 6:00 am
Categories: AI, EDA, Synopsys

“Who guards the guardians?” This is a question from Roman times which occurred to me as relevant to this topic. We use constrained random to get better coverage in simulation. But what ensures that our constrained random testbenches are not wanting, maybe over constrained or deficient in other ways? If we are improving with a faulty methodology our coverage may seem strong while in fact being incomplete. Synopsys VCS supports an ML-based capability called Intelligent Coverage Optimization (ICO) to answer precisely this question.

What’s wrong with my CR testbench?

Constrained random methods require constraints that we define. Constraints are a practical but coarse and very low-level way to attempt to map the boundaries of intended functionality. Brilliant though we may be, we are imperfect, which can lead to coverage problems. In the figure above the green circle represents the testing space we intend to generate. The yellow circle graphs the space CR can generate given the constraints we have defined. The misalignment between the two indicates multiple TB issues. As a result, some part of the test space we should cover, we can’t reach (missing stimuli). Some regions in which we will generate tests that do not correspond to intended behavior (illegal stimuli). Even within the overlap, some parts of the space we may be cover too well (over bias). And some parts may be under generated or not at all (under bias).

Our attempts to better cover design testing themselves need exposing these issues early on and rectify them wherever possible. Which is the purpose of ICO – to help you build better testbenches for coverage optimization.

How ICO works

This capability is built into the constraints solver in VCS and uses machine learning (specifically reinforcement learning) to improve stimulus quality for better coverage. In the course of this optimization it will also expose testbench bugs. There’s a lot of detail in the link below on controlling this analysis and reviewing results. My main takeaways are that the analysis does not require recompilation and can be reviewed post-run in text or HTML tables, or in Verdi.

Malay Ganai (Synopsys Scientist) who presented the technology shared a mobile user experience with ICO, comparing non-ICO and ICO analysis directly. The user found 30% more testbench bugs with the ICO analysis and importantly found an RTL deadlock which could not be found with non-ICO analysis. Moreover, they were also able to reduce regression time from 10 days to 6 days for the same functional coverage. Other users report finding critical bugs earlier (thanks to better stimulus coverage), finding more bugs faster and reducing regression times significantly.

AMD experience

AMD presented a more detailed summary of their findings using ICO, comparing also with non-ICO runs. They confirmed that they consistently find ICO covers more tests with the same number of seeds. In one striking example, ICO-based analysis was able to reach the same coverage as non-ICO in 15 regressions versus 23. That’s quite a convincing differentiating value with ICO.

AMD also gave a talk on improving testbench quality. This comes down to analysis diagnostics for skewed distributions, together with root cause analysis. They used ICO features to resolve under constraints, over constraints and to fix constraint inconsistencies. An example might be declaring a constraint variable as int when it should be a more limited bit-width, allowing far too wide of a range in randomization, thus affecting coverage and runtime.

ICO guards the testbench guardians. The testbench measures and helps optimize coverage for the design while ICO measures and helps optimize coverage for the testbench.

You can watch the SNUG presentations for both talks HERE . Register with a SolvNet Plus ID and search for ‘Early Use-cases of VCS ICO (Intelligent Coverage Optimization)’ by Malay Ganai and ‘Accelerate Coverage Closure and Expose Testbench Bugs using VCS ML-Driven Intelligent Coverage Optimization Technology’ by AMD.

July 11, 2022July 18, 2025

Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption

Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption
by Kalar Rajendiran on 07-11-2022 at 10:00 am
Categories: IP, Security, Synopsys

dwtb q222 security aes xts fig1.jpg.imgw .850.x

A recent SemiWiki post covered the topic of protecting high-speed interfaces in data centers using security IP. That post was based on a presentation made by Dana Neustadter at IP-Soc Silicon Valley 2022 conference. Dana’s talk was an overview of various interfaces and Synopsys’ security IP for protecting those interfaces. As a senior product marketing manager for Security IP, Dana has now written a technical bulletin that dives into the details of memory security. This post is based on a review of that bulletin.

Technology – A Double-Edged Sword

Many of us have seen (or heard of) the Steven Spielberg movie “Catch Me If You Can” starring Leonardo DiCaprio. The movie is based on the real life of Frank Abagnale who turned into a con artist at a very young age. While the movie may have taken some Hollywood liberties, it is true that Frank committed lots of crimes until he was caught and served time. His crimes included simple things such as writing fraudulent checks, to impersonating an airline pilot and even a resident doctor. After serving time, he reformed and has been serving the FBI for many decades, helping prevent white-collar crimes and/or catching criminals.

A few years ago, Frank Abagnale appeared on the Google Tech Talks series and gave a talk to a technology audience. An audience member asked Frank if he felt he would be able to successfully commit all the crimes in the current technology era. To the audience’s surprise, Frank said it is much easier now than it was four decades ago. Frank went on to explain that while technology offers more things, faster, cheaper and easier to use, these aspects also make it easier for a smart criminal.

The technology world’s challenge is to offer security solutions that work seamlessly with advanced products without compromising on performance, ease of use and flexibility among other requirements. Factors such as laws and regulations, changing nature of security threats, a growing attack surface and standards evolution are all placing the spotlight on security solutions.

Encryption at the Heart of Memory Security

Preventing security breaches involves many steps, but encryption is always at the heart of the solution. If data is encrypted, even if someone gets their hands on the data, they cannot do malicious things using the encrypted data. While security solutions need to be hard to break, it is also critical for the encryption/decryption process to be quick and easy. Naturally, encryption algorithms have been getting a lot of attention over the decades.

Characteristics of a Good Memory Security Solution

A good memory security solution needs to support not only the latest interfaces but also utilize minimal additional chip/board real estate and execute with very low latency. AES-XTS, or as it is sometimes referred XTS-AES, is the de-facto cryptographic algorithm for protecting the confidentiality of data-at-rest and in-use on storage devices.

It is a standards-based symmetric algorithm defined by NIST SP800-38E and IEEE Std 1619-2018 specifications. By design, it allows for pipelined architectures that can scale in performance to Terabits per second (Tbps) bandwidth. And its Ciphertext Stealing (CTS) mode provides support for data units with sizes that are not divisible by the 16-byte block size of the underlying AES cipher.

While it is one thing to have a standardized algorithm, it is yet another thing to deploy an optimized implementation of the same algorithm. The implementation needs to not only use minimal area and work at low latency but also support all key sizes and seamless context switching for a high number of changing contexts. And in particular for deployments in North America, the implementation should be certifiable to at least FIPS 140-3 Level 2, if not Level 3 for more security sensitive applications.

Synopsys’s Ultra High-Performance AES-XTS IP for HPC

Synopsys Ultra High-Performance AES-XTS Cryptographic IP core (see block diagram below) possesses the above characteristics while providing the flexibility needed to adjust to SoC designs’ specific use cases.

Some key benefits of integrating Synopsys’ standards-compliant AES-XTS crypto cores include:

High performance, low latency IP with efficient support for varied data traffic
Scalable throughput from 128 to 4096 bits/cycle, achieving bandwidths beyond 4 Tbps
Efficient encryption and decryption with 256-bit and 512-bit AES-XTS key sizes
Latency as low as 4 cycles
One tweak per cycle pre-computation
Seamless message interleaving, key setup, and key refresh for up to 64K cryptographic contexts
Multi-clock domain support
Dedicated secure key port
Area, latency, performance, and maximum frequency optimization options
FIPS 140-3 certification ready
Path for seamless full-duplex inline memory encryption integration with memory interface controllers
Support for the latest memory interfaces generations DDR4/LPDDR4 and DDR5/LPDDR5

Click here for accessing the whole technical bulletin. Synopsys offers a number of highly configurable security IP solutions. For more details, refer to the security IP product page.

July 11, 2022July 15, 2022

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?
by Kalar Rajendiran on 07-11-2022 at 6:00 am
Categories: Agnisys, EDA, Events

Whether it is fully autonomous driving, or wrinkle-free fabric, or ambient energy harvesting for powering electronic devices, each industry is chasing after its respective ultimate goal. For the semiconductor design industry, its goal is the capability to generate complete chip or IP in executable format from a high-level behavioral description. It is interesting to note that many decades ago, when schematic capture was the predominant way of specifying designs, many companies had special projects to work on behavioral language compilers. Of course, even a very complex chip in those days was much, much simpler than even the simplest chip of today.

Those were the days when EDA tools were developed in-house at IDMs and ASIC companies. The third-party EDA industry as we know today was in its nascent stage. The primary motivation for the IDMs and ASIC companies was to get the chip to production as quickly as possible. This meant that the special projects didn’t get the full-fledged investment and attention. Just as the chip complexities started growing rapidly, HDLs such as VHDL and Verilog started gaining fast traction. And of course, the third-party EDA industry started burgeoning as well. All the wonderful RTL-level tools from the EDA industry have come in handy to implement even the most complex of chips today.

Of course, the above progress has put a strain on a couple of areas. One is the manual conversion of the high-level specification of a design to VHDL or Verilog. And the other is the amount of effort/time taken for verification. Is there a way to kill two birds with one stone?

Has the time arrived? Can a tool be developed that can auto-generate RTL, SystemVerilog Assertions (SVA), UVM testbench/tests, C/C++ driver code, and documentation for an entire IP block or chip? If this tool deploys correct-by-construction methodology, wouldn’t that reduce the time and effort needed for verification? Or would it? Agnisys claims it would. Can we make that leap of faith? Even in the traditional flow using time-tested layout tools, layout is verified against the netlist using a LVS verification tool. Bring your questions to their booth at DAC 2022. Agnisys will be showcasing a demo of a tool that they have been building using crowdsourced inputs and trials.

The company says that this tool is the next step in its ever-increasing solution for specification automation. With register automation well established some years ago, Agnisys turned their attention next to sequence automation for both SystemVerilog/UVM and C/C++. They released a technology called iSpec.ai, available at https://www.ispec.ai, that deploys machine learning (ML) techniques to auto-convert English assertions into proper SVA. It can also convert SVA into English and convert English to a programming sequence. Agnisys created a library of IP for standard functions that generates the design, UVM testbench and tests, C/C++ code, and documentation. They even created a tool to connect the IP blocks together at the top level of an SoC automatically.

Agnisys’ vision is to fully automate specification to implementation across design and verification, software, and device drivers. With register automation, verification automation, and interconnect automation under their belt, they are now seeking to expand specification automation to cover complete IP cores. The idea is for a system architect to create a specification and then press a button to generate the entire IP in an executable format. The spec could cover state machines, datapaths, and more in addition to registers. The output of this tool is to include the RTL code, the UVM verification environment and testbench/tests, C/C++ driver code, and documentation. Anyone developing an IP, FPGA, ASIC, or SoC will find this capability of interest.

Sounds too good to be true? The only way to find out is to visit them at DAC, see their demo, ask questions, poke holes, and see if their story can hold water. Here are a couple of screenshots from the demo.

The tool capability may have to mature over time just as all of today’s greatest tools had to go through their own maturation process based on customers’ feedback. You can learn more about Agnisys here.

Given Agnisys’ track record, you can expect to see something interesting at their booth. So go check them out at booth number 2512 at DAC 2022 in San Francisco.

Also Read:

ISO 26262: Feeling Safe in Your Self-Driving Car

DAC 2021 – What’s Up with Agnisys and Spec-driven IC Development

AI for EDA for AI

July 10, 2022November 15, 2022

Interface IP in 2021: $1.3B, 22% growth and $3B in 2026

Interface IP in 2021: $1.3B, 22% growth and $3B in 2026
by Eric Esteve on 07-10-2022 at 10:00 am
Categories: IP, IPnest, Semiconductor Services

If you want to remember the key points for Interface IP in 2021, just consider $1.3B, 22%, $3B. Interface IP category has generated $1 billion 300 million in 2021, or 22.7% year to year growth, thanks to high runner protocols PCIe, DDR memory controller and Ethernet/SerDes. Even more impressive is the forecast, as IPnest predict the category to weight $3 billion in 2026. Also interesting in this category is the battle of two strategy models, Synopsys “One-Stop-Shop” and “Stop-For-Top” for Alphawave IP.

IPnest Forecast Interface IP Category Growth to $3B in 2026

The beginning of the 2010 years has been dominated by the wireless mobile, and a large part of interface IP revenues were generated in this market segment. High-end mobile was still dynamic in the end of 2010, and in the 2020 include many interface IP, like LPDDR5X, MIPI camera/display interfaces, PCIe 3 / 4, UFS 3.1, eUSB and USB 3.1/DP, but the data-centric segments like HPC, datacenter, AI or storage are booming and sustaining the growth in protocols like DDR memory controller (DDR5, LPDDR5, HBM), PCIe and CXL (PCIe 5 adoption in datacenter when automotive and mobile are still using PCIe 3 / 4) and Ethernet/SerDes (112G SerDes design starts in 2021 have been significant).

Ten years ago, “One-Stop-Shop” model was the mantra for IP vendors, and the strategy has been extremely beneficial for Synopsys, enjoying 55.6% market share in interface IP category. If we look at the other vendors following the “One-Stop-Shop” model, it’s more questionable. Cadence with 14% or Rambus with 3.4% market share have not been as successful as Synopsys. To benefit from this model, you need to support almost all protocols, by definition, but you also need to be the leader, with #1 revenues in every supported protocol. That we have seen since 2005, is that a small size vendor can survive and grow only if he can put a strong focus on the supported IP protocol. If the same vendor tries to support five, six or more protocol, as “One-Stop-Shop” model require, the risk of failure will be very high.

Alphawave IP, created in 2017 by a team of SerDes experts, has develop DSP based PAM4 112G and generated IP revenues of $89 million in 2021 or +102% YoY growth, after +75% in 2020. It’s an excellent example of the new strategy model, “Stop-For-Top”. The IP vendor is concentrating on very demanding product, targeting bleeding edge protocol and technology node, thanks to a strong engineering team. Alphawave IP has been “lucky”, as they are providing interconnect IP to an industry who is moving fast to become more and more data-centric and need to compute always more data, store it and interconnect these data at system level (PCIe and CXL) or long range, via Ethernet. Lucky to be at the right place at the right time, but the engineering team excellence is not luck based, it’s the result of long experience in SerDes design.

It can be interesting to compare the ROI generated by the two models… We can notice that both strategies can lead to success, as illustrated by Synopsys adopting the “One-Stop-Shop” model, with interface IP revenues ($727 million in 2021) and dominant market share of 55.6%, when Alphawave IP has been impressively fast to reach almost $100 million in IP revenues.

As usual, IPnest has made the five-year forecast (2022-2026) by protocol and computed the CAGR by protocol (picture below). As you can see on the picture, most of the growth is expected to come from three categories, PCIe, memory controller (DDR) and Ethernet & D2D, exhibiting 5 years CAGR of resp. 22%, 21% and 19%. It should not be surprising as all these protocols are linked with data-centric applications! This forecast predicts top 5 interface IP protocol to pass the $2.5B mark in 2026, or 2.5 multiplication factor in 5 years. It’s a 18.6% CAGR for 2026 to 2021 high-end interface IP revenues…

This is the 14^th version of the survey, started in 2009 when the Interface IP category market was $250 million (in 2021 $1306 million), and we can affirm that the 5 years forecast stayed within +/- 5% error margin! IPnest predict in 2022 that the interface IP category in 2026 will be in the $3000 million range (+/- $200), and this forecast is realistic.

If you’re interested by this “Interface IP Survey” released in June 2022, just contact me:

eric.esteve@ip-nest.com .

Eric Esteve from IPnest

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July 10, 2022March 26, 2023

ASML- US Seeks to Halt DUV China Sales

ASML- US Seeks to Halt DUV China Sales
by Robert Maire on 07-10-2022 at 6:00 am
Categories: China, Lithography, Semiconductor Advisors, Semiconductor Services
6 Comments

-If you can’t beat them, embargo them
-It has been reported US wants ASML to halt China DUV tools
-US obviously wants to kill, not just wound China chip biz
-Is this embargo the alternative to failed CHIPS act?
-Hard to say “do as I say, not as I do”- but US does anyway

First EUV ban now DUV ban? Are process & yield tools next?

News reports suggest that the US government wants the Netherlands government to prevent ASML from even shipping DUV tools to China.

Reuters – ASML shares fall on report US wants to restrict sales to China

It seems as if the US just wants an outright ban on all lithography tool sales to China. We would image that it is likely that the US has contacted both Nikon and Canon who also make DUV tools but not the more advanced EUV tools as just banning ASML would be pointless.

A ban on both DUV and EUV tools would put China back in the stone age of chip manufacturing somewhere in the 1990’s at .25 micron and worse.
This is not an attempt to hobble China’s chip industry, its an attempt to kill it outright. They would be all but out of business….China 2025 would become China never never land.

It suggests that a ban of US produced semi equipment is not far behind

If you are going to an litho equipment, you might as well ban process tools, such as those made by Applied Materials and Lam and yield management tools like those sold by KLA.

Maybe China could get its act together and develop a half baked DUV tool or buy tools on the secondary market but stopping associated yield management tools and process tools would be the coup de grace for China’s chip efforts.

“Do as I say, Not as I do” is hard to support when its an outright ban

We think its obviously quite hard for the US to make the case to the Netherlands to halt all sales to China when the US continues to sell billions of dollars of tools to China which is the number one market and fastest grower for US semiconductor tool makers. Its beyond hypocritical. Its almost laughable.

Obviously stopping the sales of litho tools will be the most effective but you should lead by example and halt your tool sales as well….no reason not to.
Obviously its a bit more palatable to hurt a foreign company than US companies that spend millions lobbying in Washington.

You could make the case that the drive laser in EUV tools which comes from former Cymer in San Diego borders on military technology for high power lasers but you can’t make the same case for DUV as “military grade”. The US obviously has some left over leverage from approving the Cymer sale in the form of some non public veto power.

Collateral impact of CHIPS Act failing?

In a note we had written not too long ago we suggested that if the CHIPS Act fails that the US would resort to sanctions and embargoes on China to get similar results at little to no cost. We can basically kill off the US’s primary competition in the chip space for near zero dollars without having to spend to bolster the US industry…all it takes is some sanctions and embargoes. Kinda like how organized crime deals with the competition, they sleep with the fishes.

Semiconductor supply and demand is a zero sum game

Investors and many others seem to forget that the semiconductor industry is a global zero sum game. Meaning that if China can’t produce chips needed by the world then they will be produced elsewhere…in Taiwan, Japan, the US, Europe etc;.

The world will still turn and we will still get the next generation of chips for our iPhones and AI driven electric cars.

In addition ASML will still get to sell all the litho tools it can make. If ASML can’t sell their litho tools to China there will be other non China chip makers waiting in line to take up the slack, buy the litho tools and churn out chips at a slightly higher cost than China would have.

Little to no impact

The bottom line is this has little to no impact on ASML’s long term strength or success. The only thing that will happen is that the shipping address of ASML’s tools will change. Any competition ASML was going to have from locally made litho tools in China was going to happen anyway.

Process tools are easier for China to duplicate but still very difficult so we don’t see a lot of fall out for AMAT or LRCX any time soon. KLA is next after ASML in terms of complexity and difficulty to copy.

Is likely very good for the US as we won’t become entirely dependent on China like we are for pharmaceuticals, solar panels and LEDs…which are industries they took over.

The Stocks

ASML’s stock was off 7% on the news, which is a gross over reaction of a knee jerk by those investors who don’t understand the concept of the zero sum game of the chip industry and the fact that ASML will just sell the same tools to other countries with hardly a missed beat.

They still have a monopoly. That’s not changing. People still need to move down the Moore’s Law curve. That’s not changing either. There is no other game in town…… end of story.

Other stocks were off in sympathy to ASML which was also a bit of an over reaction. Obviously investors continue to look for bad news in any story. Not much bad news here…probably more positive for the US (and other countries) chip industry in the long run…..

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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Podcast EP93: The Unique Role of EMD Electronics to Enable Technology Advances Across Our Industry

Podcast EP93: The Unique Role of EMD Electronics to Enable Technology Advances Across Our Industry
by Daniel Nenni on 07-08-2022 at 10:00 am

Dan is joined by Dr. Jacob Woodruff, Head of Technology Scouting and Partnerships with EMD Electronics, where he works to find and advance external early stage and disruptive technologies in the semiconductor and display materials space. Dr. Woodruff is an experienced technologist, having managed global R&D groups developing semiconductor deposition materials at EMD Electronics. Previously at ASM, Jacob led ALD process technology teams, and at SunPower and Nanosolar he managed R&D labs and developed processes for solar cell manufacturing. He holds a Masters in Materials Science and Engineering and a PhD in Physical Chemistry from Stanford University.

EMD Electronics has recently joined as the newest Silicon Catalyst Strategic Partner, details can be found at https://siliconcatalyst.com/silicon-catalyst-welcomes-emd-electronics-as-newest-strategic-partner, with a focused search for startups developing innovative electronic materials required for next-generation semiconductor devices.

Dan discusses the structure and focus of EMD Electronics with Jacob. The company’s primary areas of research and innovation and the far-reaching impact their work has across a large part of the semiconductor value chain are explored.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

July 8, 2022January 17, 2024

CEO Interview: Barry Paterson of Agile Analog

CEO Interview: Barry Paterson of Agile Analog
by Daniel Nenni on 07-08-2022 at 6:00 am
Categories: Agile Analog, CEO Interviews, IP

Barry Paterson is the CEO of UK-based analog IP pioneer, Agile Analog. He has held senior leadership, engineering and product management roles at Dialog Semiconductor and Wolfson Microelectronics. He has been involved in the development of custom, mixed-signal silicon solutions for many of the leading mobile and consumer electronics companies across the world. He has a technical background in Ethernet, Audio, Haptics and Power Management and is passionate about working with customers to deliver high quality products. He has an honours bachelor degree in electrical and electronic engineering from the University of Paisley in Scotland.

Agile Analog had a funding round of $19 Million last year. What was the key USP that investors liked? We have a disruptive technology called Composa™. This is an internal tool that enables us to automatically generate analog IP solutions to exactly meet customer specifications on their specific process technology.

What makes Agile Analog’s approach so different to existing analog solutions?

Until now, analog IP was typically custom designed or ported from a different process node. We re-use our tried and tested analog IP circuits that are within our Composa library. This enables us to build a customer solution using our IP for a specific process node taking into account exact customer requirements of Power, Performance and Area. Effectively, the design-once-and-re-use-many-times model of digital IP can be applied to analog IP for the first time.

What are the benefits of your new approach to the customer?

First, the analog IP circuits in the Composa library have been extensively verified and used in previous designs. The verification is automated and applied to every build of the IP core. Second, our Composa automated approach creates bespoke analog IP solutions in a fraction of the time that it would normally take develop them using tradition analog design methodologies. Third, we enable customers to license and integrate analog IP into their products allowing them to focus on faster time to market and differentiation within their market.

You have used the phrase process-agnostic in a recent press release. What does that mean for customers?

Composa can simply regenerate an analog IP solution using the PDK selected by a customer. This may be on a different process technology, for example when switching to a different foundry or taking advantage of advances in process technology to improve their products. This allows customers to select the optimum process technology and capacity options they want to use without being constrained by the analog IP. Historically the availability of analog IP has been a constraint in process selection. Our aim at Agile Analog is to remove that constraint.

Why is analog IP becoming so important?

There is a huge demand for analog ICs, that has been estimated to be valued at 83.2 billion USD in 2022 according to IC Insights’ 2022 McClean Report. We aim to address this space by making it very easy to integrate the functions of these discrete analog ICs onto the main SoC to reduce overall BOM costs, complexity, size and power consumption.

The drive to integrate analog functionality into System on Chip solutions is increasing as consumers expect a better user experience and more functionality. Some customers of Agile Analog have been exclusively been focused on digital products and now have a need to integrate some external analog functionality. This is where our foundation IP can be used. Other customers are developing devices that have increasing amounts of inputs and outputs to sensors and the real world. This invariably requires analog signals and the conversion to and from the digital domain. In this case, our data conversion IP is an ideal solution. In addition to data conversion, there is also a need to optimise power conversion to address the supply requirements of internal and external features. This is where Agile Analog’s power conversion IP can be deployed. Finally, for some customers, they need a system solution where the integration of several analog IP cores interfaces directly to their digital cores. For this, we offer a number of bespoke subsystems.

What IP do you offer?

We are building up our portfolio of foundation IP building blocks which provide some of the basic analog housekeeping that customers require. We also offer data conversion IP that includes a number of ADCs and DACs. In the power conversion space, we have LDOs and voltage references and we have future plans for buck and boost converters. Running alongside those IP cores, we want to build IP subsystems for IoT and wearables that will look like digital blocks to an EDA system to make it easy to drop them into the digital design flow. Customers can review our current IP portfolio on our website at agileanalog.com

I hear that you are moving to new larger offices, why is that?

As the Agile Analog team has grown, we have a requirement to find a larger office with more space for collaboration and innovation. We looking forward to moving into a significantly larger office at the iconic Radio House building in the heart of Cambridge, UK. This will enable us to scale to over a hundred staff as we grow. Our new office will be our global headquarters and has been designed with collaboration and team networking in mind. We will continue to have a hybrid working model with a large number of staff working from both from home and at the office so that geography is not a barrier to recruitment of top analog engineers as well as the software and digital engineers that we also need.

So are you actively recruiting now?

Yes, we have just started a major recruiting drive with the aim to increase our engineering head count by over 50%. We are looking for a number of engineers across multiple domains. If there are analog design engineers that want to work on advanced process nodes, developing different IP cores and using our latest Composa technology then they should look at the latest vacancies on our website.

Why do you think analog engineers would beat a path to your door?

Engineers always like a challenge and to be doing something different. Our approach to analog IP is completely different and is revolutionising the way that the vital analog interfaces are being incorporated into next generation semiconductors. We are working on multiple IP cores and multiple processes therefore we offer the opportunity to build experience in many exciting areas.

https://www.agileanalog.com/contact

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