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Daniel is joined by Nagesh Gupta, CEO of llmda.ai. Nagesh has built a career spanning multiple aspects of system design and development at companies including Hewlett-Packard, Cadence, Xilinx, and Lattice Semiconductor. He is also a serial entrepreneur. Nagesh founded Taray, Inc., which developed memory interface generators for Xilinx designs and was later acquired by Cadence. He also founded Auviz Systems to accelerate Vision/ML algorithms for data center and embedded applications; Auviz was acquired by Xilinx. About two years ago, Nagesh founded llmda.ai. His expertise spans startup development, product management, product development, plus chip and hardware system design.
Dan explores the foundation and key focus of this unique company with Nagesh, who describes the many issues he has seen in his career caused by incorrect or outdated design assets. Nagesh explains the significant impact these kinds of problems can have on the success of complex system design projects. He then describes the unique approach llmda.ai has taken to ensure all design assets are consistent and up-to-date. Nagesh explains how llmda.ai uses an agentic AI platform to deliver consistent and accurate information of all types across the entire development flow.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Dr. Daniel Schall is CEO and Co-Founder of Black Semiconductor. He holds a PhD in graphene optoelectronics from RWTH Aachen University. His work has shaped integrated photonics for over a decade, driving innovation in chip-to-chip communication. As co-founder of Black Semiconductor, his focus is on rethinking current solutions and forging new possibilities in the semiconductor industry.
Tell us about your company?
Black Semiconductor is a deep-tech start-up addressing a fundamental bottleneck of chip-to-chip communication with a new electronic-photonic production technology which will enable AI to scale. We will accomplish this with integrated graphene photonics technology—Black Semiconductor IGP™. FabONE, our 300mm facility designed to integrate electronics and photonics in a single production flow with graphene, will be operational by the end of 2026. It will be the first of its kind in the industry. Founded in 2020 in Germany, we have grown to 140 people representing 30 nationalities—a team with decades of fab, engineering, and technology experience. We inspire the world to re-thinking computing.
What problem is Black Semiconductor solving and why hasn’t it been solved before?
The bottleneck in computing used to be inside the chip. Now it’s between them.
Today’s systems weren’t built to deliver what we demand from AI compute. And it’s not a because the chips themselves aren’t powerful enough (they are) the problem is they can’t communicate fast enough with each other.
For fifty years, the answer was the same: make transistors smaller. That compounding produced ten million billion times more computing power than the first electronic computers. But scaling has reached its limits and the industry’s response has been to split computation across multiple chips. And that’s where a barrier lives: chip-to-chip connection, and especially copper interconnects. They are slow and bleed energy as heat. Today’s data centers are already connecting to power sources measured in hundreds of megawatts. This is the output of a nuclear power plant. It’s not a sustainable trajectory.
One solution has already emerged with increasing adoption: photonics. The industry understands the advantages of using optical signals to transmit data between chips. The challenge has been doing it in a manufacturable way, at production scale, and at viable cost. That’s where integrated graphene photonics enters the picture, and that’s where Black Semiconductor starts.
What is Black Semiconductor IGPTM technology and why does graphene specifically make it possible?
Graphene has one property that makes it uniquely suited to this application. It’s also the same property that made it fail everywhere else people tried.
When graphene was first isolated, the assumption was that we’d finally found the material for single-atom transistors. It was a genuine disappointment when we had to admit that wasn’t going to work. But the same property that ruled it out for transistors (the absence of a gap in the band structure) turns out to be precisely the advantage for broad-band photonic properties. The thing that made it fail in one application made it uniquely suited to this one.
Conventional semiconductor materials absorb only specific wavelengths of light. Graphene absorbs any wavelength across a broad spectrum. It responds to optical signals at extremely high speeds. And because it’s carbon, integrating it onto a silicon wafer is compatible with existing semiconductor manufacturing processes.
Black Semiconductor IGPTM technology (IGP stands for integrated graphene photonics) is the platform we’ve developed to bring this to production. It integrates electronic and photonic functionality on a single device, on a single wafer, and it’s produced in one manufacturing flow. An electronic, photonic integrated circuit with graphene doing both the modulator and photodetector function natively.
Some performance numbers: Black Semiconductor IGPTM technology enables at least 100x system scaling compared to current copper-based interconnects. Production cost is a fraction of current alternatives.
The reason this hasn’t been done before is that integrating graphene at production scale required solving a set of process engineering problems that took years of research to crack. That research is what we’re founded on, and the pilot fab we are building this year, FabONE, is where it becomes manufacturable.
What is FabONE? And what makes it different from any other semiconductor fab in the world?
FabONE is the world’s first scalable 2D manufacturing facility designed specifically to integrate electronics and photonics in a single production flow, on 300mm wafers, using graphene.
That configuration does not exist anywhere else. Located in Aachen, Germany, there is no other fab in the world set up to do what FabONE will do with 2D materials.
The equipment in FabONE will be off-the-shelf semiconductor standard from tier-1 tool providers. The facility design and cleanroom are being built with Exyte, one of the world’s leading semiconductor facility specialists. At the beginning of this year, construction for the manufacturing floor started through this partnership.
What makes FabONE unique is the process architecture that connects each of these tier-1 tools. The specific configuration of each piece of equipment, the process flows, the material handling — everything has been designed around the requirements of 2D material (graphene) and photonic device manufacturing. That is proprietary, and it has never been done before at scale. Our pilot production is on track for 2027 while optimizing processes to transition to volume production by 2029.
You acquired Applied Nanolayers in 2025. What does that bring to Black Semiconductor, and why was the timing important?
Applied Nanolayers, now called Black Semiconductor Netherlands (BNL), brings more than ten years of expertise in industrial graphene production. Bringing that capability in-house was a deliberate decision timed to FabONE.
When we said we would build the first 300mm graphene photonics fab in the world, our material supply chain became a strategic and technical decision. The quality, consistency, and process compatibility of the graphene layer is fundamental to device performance. We developed own production methods before the acquisition, but the ANL team had solved most of the problems we were working on. Having that wafer-scale fabrication capability inside the company, is critical for a successful technology development. It was an opportunity for both sides because the now-BNL-team had a very clear chance to transition the technology to volume production in a top-notch environment.
The BNL team brings a deep expertise in graphene process engineering that is not available elsewhere in the industry. That knowledge, integrated with our process team, is part of what makes the FabONE build credible at the pace we’re executing it.
We acquired the company when we secured FabONE as a facility. The integration is running in parallel with the facility build, so by the time pilot production begins in 2027, the material supply chain is internal, optimised, and fully under our process control.
What’s already in motion at Black Semiconductor and what can we expect to see throughout 2026 and 2027?
2026 is the year the facility is finished. 2027 is the year it produces chips.
In 2026, construction started on the manufacturing floor at FabONE and tool move-in begins in the second half of the year. In early 2027, FabONE begins development and subsequently pilot production operations. By 2029, our target is volume production.
The data from our 200mm demo-wafer runs is coming in. Once the pilot line is fully running, this is where you’ll see the learning cycle pace accelerate. Each process run feeds the next, and the cycles compress fast. That’s one of the things people underestimate about getting a fab operational. Getting the equipment in is indeed a big step, but what the equipment lets you learn is where we make leaps toward scale.
On the system side, integration work is starting now. We expect the technical results and the system-level evidence in 2028 and this is the year we begin to move toward volume production, with full capacity in 2029. 2028 is when you’ll be able to see what we’re doing come together as a manufacturable technology, built to the standard the industry knows, but with 2D materials.
Embedded systems programs rarely fail because of a lack of execution capability. They fail because critical engineering documentation drifts out of alignment over time and distance. Simply put, the team is correctly following the wrong instructions. This includes requirements, architecture, implementation, verification, hardware bring-up, firmware, and customer documentation. Local correctness does not guarantee lifecycle coherence.
llmda.ai will soon present an important webinar on this topic. The company delivers the AI fabric for embedded systems development, and the webinar will explore the dimensions of this important problem and how to bring all engineering artifacts back into focus. Below are some details of what the webinar will cover. A registration link is coming as well. As you read through this, you will realize engineering documentation is a critical source of truth – do you know if it’s accurate?
The webinar will be presented by Hal Conklin, chief commercial officer for llmda. Hal recently joined the company and brings a rich portfolio of accomplishments. Some of these include VP of sales at Arm, VP of sales and marketing at Carbon Design Systems, CEO and co-founder at BlueSteel Solutions, founder and VP of sales and marketing at CLK Design Automation, and VP of sales at Chrysalis Symbolic Design.
Hal began his career in channel marketing at Cadence. These and other experiences provide Hal with a deep understanding of embedded system design and the challenges that need to be overcome to achieve success.
Some of the Topics Covered
Hal will begin by explaining the critical importance of accurate engineering documentation. Topics covered here will include:
Deterministic Correctness: 100% alignment to source implementation details.
Source Traceability: Linking every spec to its original engineering artifact.
Repeatability: Consistent output across revisions and publishing pipelines.
Collaborative Governance: Structured review, approvals, and secure access controls.
Structured Outputs: Native support for Word, PDF, DITA, and ReST formats.
He will also discuss some of the challenges presented by general AI approaches. Generic LLMs are great to generate a first output, but they cannot be relied upon for production quality without significant added effort. He will explore this topic in some detail, describing the risks of generic AI and the benefits of purpose-built solutions such as those offered by llmda.ai.
He will then describe the llmda technology stack and how it provides the foundation for the llmda Agentic Consistency Platform. You will learn a lot about the risks and pitfalls of generic AI approaches. The graphic below summarizes some of the core architectural differentiators and cost realities associated with the llmda approach.
Core architectural differentiators and cost realities
Hal will then provide a live demonstration of llmda Spectra™, the first hardware-grounded agentic AI tool that compiles technically accurate documentation directly from engineering artifacts.
You will see the product in action so you can begin to understand its impact on documentation accuracy and overall system design quality and predictability.
To Learn More
This webinar treats a critical item for system design success, how to ensure you are building the right system from the start. If complex system design is part of your world, this webinar is a must-see event. It is being presented as a collaboration between llmda.ai and SemiWiki and will be held on June 16, 2026, at 10AM Pacific Time. You can register for the webinar here. Engineering documentation is a critical source of truth, and this webinar will help you know if it’s accurate.
Alchip Technologies reported improved financial results for the first quarter, reflecting continued momentum in advanced artificial intelligence (AI), high-performance computing (HPC), and custom ASIC demand. The company cited stronger customer engagement in leading-edge semiconductor designs and accelerating tape-out activity driven by hyperscale AI infrastructure deployments.
First quarter revenue increased sequentially and year-over-year as customers expanded investments in custom silicon solutions optimized for AI training, inference acceleration, networking, and data center applications. Management noted that demand for advanced-node ASIC development remains robust, particularly for 5nm and 3nm technologies, where Alchip continues to strengthen its engineering and backend integration capabilities.
The company’s gross margin improved during the quarter due to a more favorable product mix and higher contributions from advanced-node projects. Operating income also increased as engineering utilization rates improved and customers accelerated program execution schedules. Alchip indicated that stronger project visibility and increasing non-recurring engineering (NRE) revenue contributed positively to profitability.
Management emphasized that the AI semiconductor market continues to evolve rapidly, creating opportunities for specialized ASIC providers capable of delivering optimized power efficiency, memory bandwidth, and system-level integration. Unlike merchant silicon solutions, custom ASIC platforms enable hyperscale cloud providers and AI system developers to tailor architectures for specific workloads while reducing total cost of ownership and improving performance per watt.
During the quarter, Alchip expanded collaboration with several customers targeting AI accelerators, networking processors, and advanced packaging implementations. The company highlighted increasing adoption of chiplet architectures and high-bandwidth memory (HBM) integration as major technology trends influencing next-generation ASIC development. These technologies are becoming increasingly important as semiconductor designers seek to overcome scaling limitations and improve compute density for large AI models.
Alchip also continued to invest in advanced packaging and backend design services, including support for 2.5D and 3D integration technologies. Management stated that complex heterogeneous integration is now a central requirement for many HPC and AI applications due to escalating compute demands and memory bandwidth requirements. The company believes its expertise in design implementation and manufacturing coordination positions it well within the rapidly growing AI silicon ecosystem.
From a regional perspective, North American customers remained the largest contributor to revenue, driven primarily by cloud infrastructure and AI-related programs. The company also reported increased engagement from Asian customers pursuing custom accelerators and networking devices for enterprise and telecommunications applications.
Industry-wide semiconductor inventory normalization also contributed to improved operating conditions compared to prior quarters. While some consumer-oriented semiconductor markets remain mixed, AI infrastructure spending continues to support strong investment across advanced foundry nodes and packaging technologies. Alchip noted that long development cycles and increasing complexity in advanced semiconductor programs are creating higher barriers to entry, favoring companies with proven execution capabilities at leading-edge process technologies.
The company reaffirmed its long-term strategy focused on advanced ASIC design, backend implementation, and turnkey manufacturing support. Management expects AI-driven semiconductor demand to remain a primary growth catalyst throughout the year, particularly as hyperscale operators expand deployment of generative AI infrastructure. Increased capital spending on AI servers, networking, and accelerator platforms is expected to sustain demand for customized silicon solutions.
Alchip further indicated that customer interest in 3nm development programs continues to increase as advanced process economics improve and performance requirements intensify. The transition toward smaller process geometries enables higher transistor density, lower power consumption, and improved compute performance, all of which are critical for modern AI workloads.
Looking ahead, the company expects continued growth in tape-out activity and engineering engagements tied to AI and HPC applications. Management acknowledged that geopolitical uncertainty and semiconductor supply chain dynamics remain factors to monitor; however, demand visibility for advanced-node programs remains strong.
With AI infrastructure investment accelerating globally, Alchip believes the semiconductor industry is entering a sustained period of demand for custom silicon innovation. The company’s improved first quarter results underscore the growing importance of ASIC providers in enabling next-generation AI compute architectures and advanced data center deployments.
As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and dies to be connected with high bandwidth and low latency while avoiding the complexity and cost of full silicon interposers. As designs become increasingly sophisticated, however, packaging success depends not only on manufacturing technology but also on robust design methodologies and ecosystem collaboration.
At the forefront of this effort is Intel’s collaboration with Synopsys, which provides the EDA tools necessary to address the growing challenges of advanced package design, analysis, and verification. Together, Intel and Synopsys are enabling designers to maximize the benefits of EMIB while reducing development risk and accelerating time-to-market.
EMIB technology allows silicon bridges to be embedded directly within the package substrate, creating dense interconnect pathways between adjacent dies. This architecture offers many of the performance advantages associated with 2.5D integration while maintaining greater flexibility and cost efficiency. EMIB has already been deployed in high-performance computing, AI accelerators, FPGAs, and data center products where bandwidth and power efficiency are paramount.
As the number of chiplets within a package increases, design complexity grows exponentially. Engineers must manage signal integrity, power delivery, thermal performance, mechanical stress, and manufacturing variability across multiple dies and package layers. Traditional package design methodologies are often insufficient for these highly integrated systems, creating the need for a comprehensive co-design approach that spans silicon, package, and system domains.
Synopsys addresses these challenges through a suite of advanced packaging tools that support Intel’s EMIB design ecosystem. By enabling concurrent chip-package co-design, designers can optimize performance earlier in the development cycle and identify potential issues before costly physical implementation stages. This integrated methodology helps reduce design iterations while improving overall product quality.
One key area of focus is signal integrity analysis. EMIB-based designs support extremely high-speed interfaces that require accurate modeling of interconnect behavior across dies and package structures. Synopsys simulation and analysis tools provide detailed visibility into channel performance, enabling engineers to validate electrical characteristics and ensure reliable communication between chiplets.
Power integrity is equally important in advanced heterogeneous systems. High-performance AI and compute workloads place increasing demands on power delivery networks. Synopsys tools help designers analyze voltage drop, current density, and transient behavior across the package and silicon domains, allowing optimization of power distribution before fabrication.
Thermal analysis represents another critical component of the EMIB design methodology. Multiple high-power chiplets operating within a single package can create localized hotspots that affect performance and reliability. Integrated thermal modeling capabilities allow engineering teams to evaluate heat dissipation strategies and make informed architectural decisions during the design process.
Verification and design signoff have also become more complex in multi-die architectures. Designers must validate connectivity, physical implementation, and manufacturing readiness across numerous interfaces and package structures. Synopsys provides automated verification capabilities that help ensure design correctness while supporting the stringent requirements of advanced packaging technologies such as EMIB.
Beyond individual tools, the Intel-Synopsys collaboration highlights the importance of ecosystem readiness in the chiplet era. Successful heterogeneous integration requires interoperability between design environments, IP providers, foundries, OSATs, and packaging technologies. By aligning methodologies and workflows, Intel and Synopsys are helping establish industry best practices that enable broader adoption of advanced packaging solutions.
Looking ahead, EMIB is expected to play an increasingly important role in AI, high-performance computing, networking, and data center applications. As transistor scaling becomes more challenging and system-level integration gains importance, advanced packaging technologies will continue to drive semiconductor innovation. Through close collaboration with partners such as Synopsys, Intel is expanding the design methodology foundation needed to support the next generation of chiplet-based systems.
Bottom line: The combination of Intel’s EMIB technology and Synopsys’ advanced EDA capabilities demonstrates how packaging innovation and design automation must evolve together. By providing comprehensive analysis, verification, and co-design methodologies, the two companies are enabling engineers to confidently develop increasingly complex heterogeneous systems that deliver higher performance, greater efficiency, and faster time-to-market.
TSMC, the world’s largest contract semiconductor manufacturer, is significantly expanding its deployment of NVIDIA artificial intelligence and accelerated computing technologies throughout its chip design and manufacturing operations. The initiative represents one of the most comprehensive applications of AI within advanced semiconductor fabrication, spanning lithography, process simulation, defect inspection, production scheduling, and factory optimization. The collaboration underscores how AI is becoming a critical enabler of next-generation semiconductor manufacturing as process technologies advance toward the angstrom era.
Modern semiconductor manufacturing has become extraordinarily complex, with advanced nodes requiring billions of transistors, hundreds of process steps, and nanometer-level precision. Traditional CPU-based computing environments often struggle to handle the computational demands associated with process development, computational lithography, and factory optimization. To address these challenges, TSMC is leveraging NVIDIA CUDA-X libraries, GPU-accelerated computing platforms, and AI models to accelerate critical workloads across the semiconductor production lifecycle.
One of the most significant areas of deployment is computational lithography. TSMC is utilizing NVIDIA cuLitho technology to accelerate the simulation and optimization processes required for advanced chip patterning. Computational lithography plays a vital role in translating circuit designs into physical patterns that can be printed onto silicon wafers. According to NVIDIA, TSMC has achieved improvements ranging from 20% to 50% in cycle time and cost effectiveness when using GPU-accelerated lithography workflows compared with conventional CPU-based approaches. These gains are particularly important as the industry moves toward increasingly sophisticated process technologies that require extensive optical proximity correction and mask optimization.
Beyond lithography, TSMC is applying AI and accelerated computing to transistor and process simulation. Semiconductor process development requires detailed modeling of materials, device structures, and manufacturing interactions. NVIDIA’s cuEST library enables significantly faster electronic structure and chemistry simulations, reportedly accelerating semiconductor material design calculations by as much as 50 times. Faster simulations allow engineers to evaluate more design alternatives, optimize materials, and reduce development cycles for future process nodes.
Factory operations are another major focus area. TSMC is deploying NVIDIA H200 GPU infrastructure and CUDA-based scheduling technologies to optimize production workflows and improve fab utilization. Semiconductor fabs generate enormous volumes of operational data, including equipment status, wafer movement, process parameters, and yield metrics. AI-powered scheduling and optimization systems can analyze these data streams in real time to improve throughput, reduce bottlenecks, and enhance overall manufacturing efficiency.
Quality control is also benefiting from AI integration. TSMC is using NVIDIA Metropolis and the NVIDIA TAO Toolkit to develop advanced vision AI systems for automated defect inspection. These systems are designed to detect nanometer-scale defects on wafers and photomasks with greater accuracy while reducing the need for repeated data labeling and model retraining. Automated inspection is increasingly important as feature sizes shrink and defect detection becomes more difficult using traditional methods. Improved defect identification directly contributes to higher yields and reduced manufacturing costs.
Another strategic initiative involves the development of digital twins for semiconductor manufacturing. TSMC and NVIDIA are collaborating on FabTwin, a virtual factory environment built using NVIDIA Omniverse technology. Digital twins enable engineers to simulate fab layouts, equipment configurations, material flows, and operational scenarios before implementing changes in physical production environments. Such capabilities help reduce deployment risks, improve resource planning, and accelerate process optimization across large-scale manufacturing facilities.
The expanded partnership reflects a broader industry shift toward AI-driven manufacturing. As advanced semiconductor nodes become more difficult and expensive to develop, AI is emerging as a critical tool for improving yield, reducing energy consumption, accelerating design cycles, and increasing fab productivity. NVIDIA CEO Jensen Huang stated that TSMC is bringing AI and accelerated computing directly into the fabrication environment to address some of the industry’s most complex design and manufacturing challenges. The result is a highly intelligent manufacturing ecosystem capable of supporting the next generation of AI processors, high-performance computing devices, and advanced semiconductor technologies.
Bottom line: TSMC’s adoption of NVIDIA AI technologies represents a significant milestone in the evolution toward autonomous, data-driven chip manufacturing. As AI workloads continue to grow globally, the integration of AI into semiconductor production itself may become a defining competitive advantage for leading foundries in the years ahead.
The semiconductor industry is generating more engineering data than ever before.
This article follows the previously published GFL and TCG foundation pieces. GFL introduced the lifecycle-governance problem. TCG clarified why observable or interoperable data is not automatically trustworthy convergence evidence. CEMH now defines the maturity path by which information becomes eligible for authority.
Advanced design and realization flows now produce massive volumes of simulation results, telemetry streams, firmware traces, validation outputs, DFT evidence, manufacturing data, qualification results, and field observations. Interoperability improvements have made it easier for this data to move across tools, domains, teams, and organizations.
But a critical distinction is becoming increasingly important:
Data movement does not create decision authority.
A signal may be observable. A file may be interoperable. A telemetry stream may be accessible. A simulation result may be available to downstream tools. Yet none of this guarantees that the information is trustworthy enough to influence convergence governance, closure decisions, runtime intervention, or Fleet Learning.
This is why SEGA-AI™ requires a Convergence Evidence Maturity Hierarchy, or CEMH.
The hierarchy defines how information matures from raw observation into convergence-authoritative evidence capable of supporting governed system decisions.
The canonical sequence is:
Raw Data → Interoperable Data → Normalized Evidence → Admissible Evidence → Convergence-Authoritative Evidence
The purpose of this hierarchy is not theoretical classification alone. It provides the implementation basis for SEGA-AI™ evidence handling. Without defined maturity levels, tools may collect data, platforms may exchange data, and AI systems may analyze data, but the governance system still cannot determine whether that information is eligible to close a gate, reopen a decision, trigger intervention, or refine future lifecycle assumptions.
Figure 1 illustrates the Convergence Evidence Maturity Hierarchy as a progression from raw data toward evidence with increasing rigor, trust, and decision authority.
This sequence may appear simple, but it addresses one of the most important challenges in advanced heterogeneous systems: determining when information becomes authoritative enough to govern convergence.
The purpose of CEMH is not simply to organize data. Its purpose is to define the path by which information becomes eligible for authority. In SEGA-AI™, convergence-authoritative evidence is the maturity state at which information can support bounded gate closure, runtime intervention, Fleet Learning refinement, or lifecycle governance without breaking causality, synchronization, or realization-state validity.
Why Raw Data Is Not Enough
Raw data is the starting point.
It may include sensor outputs, telemetry streams, simulation logs, manufacturing measurements, validation results, firmware traces, workload behavior, thermal readings, voltage behavior, SI/PI observations, EM indicators, or field-return signals.
Raw data is valuable because it provides observability.
But observability alone is not governance.
Raw data may be incomplete, stale, desynchronized, incorrectly contextualized, weakly correlated, or disconnected from the relevant physical state.
A telemetry stream may show a thermal event without preserving the workload condition that produced it. A firmware trace may record an intervention without preserving the package, board, voltage, or thermal state in which the intervention occurred. A field observation may reflect a real failure pattern but lack enough causal context to refine future closure assumptions.
Raw data tells us that something was observed.
It does not automatically tell us whether that observation can govern a decision.
Raw data observes. It does not govern.
Level 1: Raw Data
The first maturity level is raw data.
This includes:
telemetry
logs
sensor outputs
tool outputs
simulation results
lab measurements
manufacturing records
validation outputs
field observations
At this level, the system has visibility but not authority.
Raw data may identify that something occurred, but it does not necessarily explain why it occurred, whether it is synchronized to the correct state, whether it represents the current realization configuration, or whether it is valid enough to influence a convergence decision.
Raw data is therefore necessary but insufficient.
It is the beginning of the evidence path, not the endpoint.
Level 2: Interoperable Data
The second maturity level is interoperable data.
Interoperable data can move across tools, databases, workflows, teams, or organizational boundaries. It may follow a standard format, connect to downstream environments, or be accessible through shared infrastructure.
Interoperability is essential because modern semiconductor systems require coordination across silicon, package, interposer, PCB, PDN, thermal, mechanical, firmware, validation, manufacturing, and runtime domains.
However, interoperability solves transport.
It does not solve authority.
A piece of data can be interoperable while still being misleading for convergence decisions. It may preserve syntax but lose context. It may move correctly while carrying stale assumptions. It may be readable by another tool while lacking boundary-condition consistency, correlation status, timestamp validity, or realization-state alignment.
This is the core limitation of interoperability:
Interoperability makes data movable. It does not make evidence authoritative.
This distinction is central to advanced semiconductor governance. As systems become more heterogeneous and lifecycle-dependent, the industry cannot assume that connected data is qualified data.
Data can move perfectly and still fail as convergence evidence.
Level 3: Normalized Evidence
The third maturity level is normalized evidence.
To become useful for governed convergence, data must gain context. Normalized evidence preserves not only the result itself, but the conditions required to interpret it.
This may include:
source domain
model version
geometry revision
timestamp
boundary conditions
temperature assumptions
reference-plane definitions
model fidelity
confidence level
correlation status
package or board configuration
workload state
relationship to other evidence
This stage is essential because advanced heterogeneous systems do not fail only because data is unavailable. They often fail because different domains interpret data through different assumptions.
A package model may use one thermal boundary condition. A PCB PDN model may use a different return-path assumption. An EM calculation may depend on a temperature map that no longer matches the current thermal solution. A firmware trace may correspond to an operating state that does not match the validation scenario being reviewed.
Normalized evidence creates a shared decision context.
It allows domain outputs to be compared, correlated, and evaluated as part of a larger convergence structure.
But normalized evidence is still not enough.
It must become admissible.
Level 4: Admissible Evidence
The fourth maturity level is admissible evidence.
Admissible evidence is evidence that satisfies bounded governance criteria before it participates in a closure decision, runtime intervention, or lifecycle refinement process.
Admissibility may require:
provenance continuity
synchronization integrity
realization-state validity
model fidelity
causal relevance
boundary-condition completeness
confidence qualification
timestamp freshness
chain-of-custody preservation
correlation maturity
This is where Trusted Convergence Governance becomes important.
Operational evidence, telemetry, firmware traces, DFT infrastructure, qualification outputs, and Fleet Learning inputs should not be trusted simply because they are observable or interoperable. They must pass through admissibility governance before they influence convergence decisions.
This protects the system from a dangerous condition:
operationally connected but convergence-non-authoritative data.
A system may continue exchanging data while losing the trust continuity required for deterministic convergence. Telemetry may remain active while becoming desynchronized. Firmware traces may exist while losing causal context. Field data may show a pattern while lacking realization-state validity. Fleet Learning may identify a statistical correlation while the underlying evidence is not physically admissible.
Admissible evidence is therefore the threshold where information becomes qualified to participate in governance.
It is not yet the final destination.
But it has crossed the boundary from visibility into governed participation.
Level 5: Convergence-Authoritative Evidence
The fifth maturity level is convergence-authoritative evidence.
This is evidence strong enough to influence governed closure, bounded intervention, Fleet Learning, lifecycle refinement, or future realization assumptions.
This does not mean the evidence is perfect.
It means the evidence has preserved enough trust, context, causality, synchronization, fidelity, and admissibility to support bounded decision authority.
Examples may include:
a thermal model correlated to measured package behavior and synchronized with the current geometry revision
an EM margin calculation using the correct temperature state and current-density distribution
a PDN analysis aligned with package and board return-path assumptions
a telemetry stream with provenance, timestamp validity, and realization-state consistency
field evidence that has passed correlation checks and can refine future package constraints
Fleet Learning outputs that recommend threshold adjustment without independently closing gates
This is the point at which evidence may influence governance decisions.
The distinction is critical:
Observable data can inform.
Admissible evidence can participate.
Convergence-authoritative evidence can govern.
Why This Matters for Fleet Learning
Fleet Learning makes the hierarchy even more important.
Within SEGA-AI™, Fleet Learning is not generic analytics. It is a governed realization-feedback mechanism through which operational evidence can refine convergence assumptions, admissibility boundaries, firmware policies, package constraints, validation priorities, and future closure criteria.
That creates a recursive governance problem.
If Fleet Learning refines future convergence decisions, then the evidence feeding Fleet Learning must itself be governed. Otherwise, future closure criteria may be refined using non-admissible or causally incomplete evidence.
This is the question Trusted Convergence Governance raises:
Who validates the evidence that validates the system?
CEMH answers by requiring operational information to mature through visible stages before it can influence governance.
Raw data is not enough.
Interoperability is not enough.
Normalization is not enough.
Admissibility is the gate.
Convergence authority is the outcome.
Fleet Learning should therefore not learn equally from all available data. It should refine future convergence assumptions only from evidence that has matured sufficiently for bounded decision use.
Relationship to GFL and TCG
CEMH also clarifies the relationship between three SEGA-AI™ concepts: Governance for Lifecycle, Trusted Convergence Governance, and the Convergence Evidence Maturity Hierarchy.
GFL asks whether the realized system can remain converged throughout operational life.
TCG asks whether the evidence entering governance is trustworthy enough to influence convergence decisions.
CEMH defines the maturity level that evidence must reach before it can carry decision authority.
These are separate but connected concepts.
GFL defines the lifecycle governance problem.
TCG defines the trust gate.
CEMH defines the evidence maturity path.
Together, they prevent a common failure mode in advanced heterogeneous systems: assuming that visibility, interoperability, or analytics automatically creates convergence authority.
It does not.
Evidence must mature before it can govern.
From Evidence Maturity to Implementation
The Convergence Evidence Maturity Hierarchy is not only a conceptual classification model. It also provides the implementation logic for how SEGA-AI™ handles evidence across tools, domains, gates, and lifecycle states.
At the architecture-theory level, SEGA-AI™ defines why evidence must become authoritative before it can govern system realization. This includes admissibility, causality continuity, synchronization, realization-state validity, bounded convergence, and decision authority.
At the implementation-specification level, those principles must become executable. This includes evidence schemas, admissibility checks, timestamp and synchronization rules, causal dependency maps, gate states, validation criteria, runtime policies, audit artifacts, and closure/reopen logic.
In simple terms:
D2 defines the authority model.
D3 verifies and executes the authority model.
This distinction is important because convergence-authoritative evidence is not created by one tool, one database, or one AI model. It emerges only when the architecture defines what authority means and the implementation layer proves that the evidence satisfies that authority model.
Without the architecture layer, evidence lacks governance meaning.
Without the implementation layer, evidence lacks operational proof.
Together, they allow SEGA-AI™ to distinguish between information that is merely visible and evidence that is mature enough to govern system convergence.
Relationship to Governed Convergence
Governed convergence depends on CEMH because deterministic closure requires more than domain completion.
It requires evidence that is admissible, causally consistent, synchronized, and authority-bearing.
A local SI result may pass. A PI model may pass. A thermal solution may pass. An EM calculation may pass. But unless those results mature into convergence-authoritative evidence within a shared decision context, the system may still remain globally inconsistent.
This is why the hierarchy is not only a data pipeline.
It is a governance pipeline.
It transforms fragmented observations into bounded decision authority.
Together, they allow SEGA-AI™ to distinguish between information that is merely visible and evidence that is strong enough to govern system convergence.
A Practical Example
Consider a high-current advanced package where a thermal sensor reports repeated local hotspot behavior during field operation.
At the raw-data stage, the system has a temperature observation.
At the interoperable-data stage, that observation can move into a diagnostic environment or fleet database.
At the normalized-evidence stage, the observation is associated with workload state, package lot, board revision, firmware version, sensor location, timestamp, operating voltage, and thermal boundary conditions.
At the admissible-evidence stage, the system validates provenance, synchronization, realization-state relevance, sensor confidence, and causal relationship to package behavior.
At the convergence-authoritative stage, the evidence may influence future package constraints, firmware policy refinement, thermal-interface validation criteria, or Fleet Learning recommendations.
The same temperature reading therefore changes meaning as it matures.
It begins as a signal.
It becomes data.
It becomes evidence.
It becomes admissible.
Only then can it become convergence-authoritative.
Why This Matters for AI, Chiplets, HBM, and Advanced Packaging
In AI and HPC systems, evidence crosses many boundaries.
It moves from die to package, package to board, board to rack, simulation to silicon, lab to field, firmware to workload, and telemetry to Fleet Learning.
Advanced packaging increases the importance of this evidence path because the system is no longer governed by one isolated domain. Chiplets, HBM, interposers, substrates, power delivery, thermal spreading, mechanical stress, firmware behavior, and workload dynamics interact across the realization environment.
A result that appears valid inside one domain may become misleading when used outside its original context.
A thermal map may not match the electrical state. A PDN result may not reflect the current package deformation condition. A firmware trace may not preserve the physical state that caused it. A field pattern may be statistically visible but physically incomplete.
CEMH gives the organization a way to ask:
What maturity level has this evidence reached?
Without that question, organizations risk treating all visible data as equally useful.
That creates convergence risk.
Conclusion
The semiconductor industry has made major progress in interoperability, observability, simulation, and data infrastructure.
These advances remain necessary.
But they do not automatically create trustworthy convergence decisions.
As heterogeneous systems become more physically coupled, operationally adaptive, and lifecycle-dependent, the industry must distinguish between data that is available and evidence that is authoritative.
The Convergence Evidence Maturity Hierarchy provides that distinction.
It defines the path from raw data to convergence-authoritative evidence and clarifies why each stage matters.
Without this hierarchy, systems risk making closure, intervention, or learning decisions from information that is visible but not admissible, interoperable but not synchronized, correlated but not causal, or useful but not authoritative.
The future of advanced packaging and heterogeneous integration may depend not only on collecting more data, but on governing the maturity of evidence itself.
The critical question is no longer only what the system observed.
The deeper question is whether that evidence has matured enough to become convergence-authoritative.
Raw data observes.
Interoperable data moves.
Normalized evidence contextualizes.
Admissible evidence qualifies.
Convergence-authoritative evidence governs.
This evidence-maturity model also prepares the ground for the next SEGA-AI™ layer: Fleet Learning as a governed convergence system. Fleet Learning should not learn equally from all available data. It should refine future convergence assumptions only from evidence that has matured sufficiently to become admissible or convergence-authoritative.
Fleet Learning may recommend refinement, but bounded gate authority must approve lifecycle decisions.
IPLM is not always prominent, nevertheless it is a very necessary aspect of semiconductor (and systems) design. Modern designs build on a wide range of IPs and subsystems, each evolving through multiple variants and versions, each with different PPA characteristics and recommended use-cases, many from different suppliers and/or in different states of readiness, or possibly no longer supported. Then there are license agreements and export restrictions. Managing this complexity is not a task that can be left to a spreadsheet. IP catalog management demands high levels of automation all the way from product design to in-field support and ultimately through to decommissioning.
The essentials of IPLM
It is very rare that a full system design starts from scratch. Most designs build on significant legacy system and subsystem data, refining and evolving to meet new and more challenging objectives. Inevitably IPs used in those legacy systems may been upgraded. Should you continue to use an old version or switch to a newer version? You may not have a choice if the old version has been deprecated. Or maybe you need the newer version of performance characteristics, but the older version is proven in silicon where the newer version may not yet have that advantage.
In bringing legacy subsystems together you may find they use different versions of the same IP, for whatever reason. In a combined system to be fabricated in one process that conflict must be resolved to one selection. Your decision of course on how you want to resolve such a conflict, but first you need to know where the conflicts are.
There is a different spin on this issue in chiplet-based systems. Each chiplet provider will drive manufacturing according to their IP choices which need not affect manufacturing choices for other chiplet makers. Here IPLM must recognize that conflicts between chiplets, unlike conflicts with a chiplet, need not be limiting.
Traceability is an important consideration throughout a design lifecycle for multiple reasons. Problems detected in other designs can be flagged to other design teams or to customers, with proposed workaround. Some standards such as ISO 26262 require detailed traceability. License agreements demand that usage be tracked. Further, export restrictions can be quite dynamic these days. You can’t recall product already in the field, but you need to know what might require a redesign, to become compliant with a changed restriction.
AI and IPLM
As a favorite topic of mine naturally I am interested in how IPLM integrates with AI, especially in agentic flows. I recently listed to a Perforce webinar, on enhancements to their product touching on some of the topics above and particularly on their directions in AI. These include an MCP interface to the underlying Perforce technology, which I imagine should enable direct connection to agentic flows. They also mention a RAG server to help IPLM novices learn how to use the system, for example how to set access controls. The intention is to expose this capability through a chat interface. I am told that planned release for these capabilities is June 2026.
Interesting stuff. Managing IP usage across an incredibly complex matrix of characteristics and restriction has become very challenging task. Adding agentic methods into the mix will further simplify understanding, search and management in SoC and multi-chiplet designs. Again you can access the webinar HERE.
The strategic cooperation between Semidynamics and SiPearl to develop a European sovereign rack-scale AI compute platform is important for reasons that extend far beyond technology. It represents a major step toward Europe gaining greater control over its artificial intelligence infrastructure, reducing dependence on foreign technology providers, and building a competitive position in the rapidly expanding global AI economy.
Today, the AI infrastructure market is dominated by companies based primarily in the United States and increasingly China. Most advanced AI compute systems rely on processors, accelerators, software ecosystems, and cloud infrastructure controlled by non-European companies. This creates strategic vulnerabilities for Europe in areas such as economic competitiveness, national security, supply chain resilience, and digital sovereignty. The Semidynamics-SiPearl collaboration directly addresses these concerns by helping establish a homegrown European AI compute ecosystem.
One of the most significant aspects of this partnership is the concept of “EU-sovereign” AI infrastructure. Sovereignty in computing means that Europe can design, develop, deploy, and operate critical AI systems using technology largely controlled within its own political and regulatory framework. This matters because AI is increasingly becoming foundational infrastructure, similar to energy grids or telecommunications networks. Nations and regions that do not control their AI infrastructure risk losing influence over economic development, industrial innovation, data governance, and security standards.
The partnership also comes at a critical time when demand for AI compute power is exploding. Training and deploying large AI models require enormous amounts of processing capability, memory bandwidth, and energy-efficient architectures. Rack-scale AI systems — where compute, networking, and memory are tightly integrated at the data center rack level — are emerging as the next frontier in high-performance AI infrastructure. By collaborating on this technology now, Semidynamics and SiPearl are positioning Europe to participate competitively in the future of hyperscale AI computing rather than remaining dependent on imported platforms.
Technologically, the cooperation combines complementary strengths. SiPearl has been developing high-performance European processors designed specifically for exascale supercomputing and AI workloads. Semidynamics contributes advanced semiconductor IP and architecture innovation, particularly in areas involving high-performance RISC-V processor technologies. Together, they can create specialized AI compute platforms optimized for European requirements, including performance efficiency, open architectures, and interoperability.
The use of RISC-V technology is especially meaningful. RISC-V is an open instruction set architecture that allows companies and governments to develop processors without relying on proprietary licensing models from dominant foreign suppliers. This reduces technological dependency and provides greater customization flexibility. For Europe, supporting RISC-V-based AI infrastructure aligns with broader goals of technological independence and open innovation.
Another important dimension is economic competitiveness. AI is expected to become one of the defining economic drivers of the next several decades, influencing industries ranging from automotive and healthcare to aerospace, manufacturing, and finance. If Europe lacks indigenous AI compute infrastructure, European companies may face higher costs, reduced access to advanced systems, and strategic disadvantages compared to competitors in the U.S. and Asia. Building sovereign AI platforms helps retain high-value semiconductor expertise, research capability, and manufacturing opportunities within Europe.
The collaboration also strengthens Europe’s semiconductor ecosystem at a time when governments worldwide are investing heavily in chip independence. The United States has launched the CHIPS Act, while China has aggressively pursued semiconductor self-sufficiency. Europe’s own semiconductor ambitions require not only fabrication capacity but also strong processor design companies, IP providers, software ecosystems, and AI infrastructure players. The Semidynamics-SiPearl partnership demonstrates that Europe is developing a more integrated semiconductor strategy rather than focusing solely on manufacturing.
Security and data governance are additional factors driving the importance of this initiative. AI systems increasingly process sensitive government, industrial, healthcare, and defense-related data. European policymakers have become increasingly concerned about relying entirely on foreign-owned infrastructure for mission-critical workloads. A sovereign AI compute platform offers more control over hardware security, data residency, compliance, and operational transparency.
The timing is also significant because Europe has been criticized for lagging behind in AI commercialization despite strong academic research capabilities. Partnerships like this show a shift toward industrial-scale execution. Rather than simply funding research projects, Europe is now supporting infrastructure capable of enabling large-scale AI deployment across commercial and public sectors.
Finally, the cooperation symbolizes Europe’s ambition to shape the future of AI according to its own values and priorities. Europe has emphasized ethical AI, privacy protections, sustainability, and regulatory accountability. To enforce and operationalize those principles effectively, Europe needs its own compute infrastructure foundation. Without sovereign platforms, regulatory influence alone may not translate into practical technological leadership.
Bottom line: The Semidynamics and SiPearl partnership is important because it represents far more than a technical collaboration. It is part of a broader strategic movement toward European AI independence, semiconductor competitiveness, digital sovereignty, and long-term economic resilience in the age of artificial intelligence.
Accurate, complete, and consistent technical documentation is a critical element of success for any embedded system design project. This includes IP, SoCs, and the associated hardware and software infrastructure. When documentation contains errors, the consequences go beyond engineering inefficiency. Errors that drive the development, testing and use model of the system can manifest as late-stage bugs that are costly and time-consuming to fix. Or worse, issues arise after the system is in production. Beyond the cost of repair, problems like this can damage customer confidence and weaken a company’s brand.
The process to address this important problem has typically involved a lot of manual work by design team members that should really be focusing on design and not documentation. llmda.ai solves this latent flaw in system design with a new approach. One that employs AI and agentic technology to flatten the problem with minimal human overhead. The company recently issued an informative white paper on the approach. Learn how llmda uses agentic AI to generate hardware docs & keep them consistent. A link to this white paper is coming. Let’s first examine some of what it covers.
The Problem
Developing accurate technical documentation can become a major time and resource drain that diverts engineering effort, slows execution, and directly impacts time-to-market. Some of the drivers of this situation include:
Time constraints: Documentation often competes with other high-priority engineering tasks and is typically due alongside major project milestones and deliverables.
High-cost resource drain: Creating accurate documentation requires significant time from the most critical and expensive project resources—design engineers, architects, and domain experts.
Distributed collaboration: Documentation is frequently a multi-stakeholder effort, and geographically dispersed teams make coordination, review cycles, and alignment difficult.
Content duplication: Many documents share the same foundational technical content, yet teams repeatedly rewrite and reformat similar material across specifications, manuals, and guides.
Product configuration complexity: Modern products often ship in multiple variants, requiring documentation to be tailored, maintained, and validated across numerous configurations.
The Solution – llmda Spectra™
llmda Spectra is a product that addresses these documentation challenges head-on. It leverages advanced LLM technology to intelligently extract, synthesize, and structure content from internal engineering artifacts, transforming fragmented technical information into clear, accurate, and production-ready documentation.
The white paper will help you understand how this is achieved. Some of the topics covered include:
Intelligent information extraction
Contextual technical understanding
Automated structuring and formatting
User-friendly guided workflows
How the platform is collaboration-ready
How section-by-section build and lock is achieved
How transparent sources and traceability are delivered
The impact of human-in-the-loop GenAI
How hardware description language awareness is achieved
How IP-XACT and metadata extraction is achieved
The impact of automated block diagram generation
The documentation quality key performance indicators (KPIs) that llmda Spectra tracks are also discussed. You will learn how these KPIs transform documentation from an “afterthought deliverable” into an engineered output that can be tracked, improved, and validated over time.
To whet your appetite, here is a summary of some of the KPIs llmda Spectra tracks and the results achieved.
Case Studies
The white paper also presents the details of two case studies that illustrate how llmda Spectra delivers measurable outcomes by accelerating documentation cycles, improving quality, and reducing engineering burden.
The first case study examines the details associated with high-volume IP user guide generation. It shows how a semiconductor design team delivered IP user guides for 20 new IP blocks in under one month, despite having limited access to dedicated technical writing resources.
The second case study examines the details of rapid application note updates for new silicon revisions. This one shows how an application engineering team at a major semiconductor company quickly updated application notes to reflect new silicon features and design changes, without rewriting the documents from scratch.
In each case study, details of the business challenge, how llmda Spectra was applied, and the outcome and impact achieved are presented.
To Learn More
Poor quality documentation can have a dramatic negative impact on any embedded system design project. llmda.ai has a solution to this problem that substantially reduces the effort required to achieve the best outcome.
You can get your copy of this important new white paper here. And that’s how llmda uses agentic AI to generate hardware docs & keep them consistent.
