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Podcast EP352: The Path to High Impact Parallel AI Agents with ChipAgents CEO and Founder William Wang

Podcast EP352: The Path to High Impact Parallel AI Agents with ChipAgents CEO and Founder William Wang
by Daniel Nenni on 06-26-2026 at 10:00 am

Daniel is joined by William Wang the CEO and Founder of ChipAgents.ai, the category-leading agentic AI platform for advancing agent-based AI approaches for semiconductor workflows. He is also the Mellichamp Endowed Chair Professor of AI and Designs at UC Santa Barbara, and a global leader in fundamental AI research. He founded the UCSB Center for Responsible Machine Learning, the Mind and Machine Intelligence Initiative, and the UCSB NLP Group. His honors include the IEEE SPS Pierre-Simon Laplace Award, NSF CAREER Award, BCS Karen Sparck Jones Award, DARPA Young Faculty Award, and IEEE AI’s 10 to Watch.

In this highly informative discussion, William describes his early work on AI models with Dan. Over two decades, William began to see the impact agentic AI could have on production chip design. One shortcoming he saw was the relatively long time it took for university research to make an impact versus what could be done in private industry. Another shortcoming was the way AI was being added to existing design flows, as an additional technology that yielded relatively low impact.

These observations led William to form ChipAgents, a company that takes a fresh view of AI in chip design by creating a new and unique end-to-end approach to AI automation enabled by a new platform. The technology has broad applicability, and William describes how ChipAgents technology is starting with verification, the most time-consuming part of the design process. He describes what has been developed and its impact across all forms of verification, including formal methods. In the formal area, William describes how a one- to two-week process can be achieved in one hour with ChipAgents.

Book a Demo

ChipAgents is a Platinum Sponsor at DAC this year, and William describes the many demos and presentations that will take place at the conference. This includes a joint presentation with ADI that describes how to scale AI agent deployment. There are presentations with large companies as well.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

June 26, 2026June 25, 2026

Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?

Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?
by Daniel Nenni on 06-26-2026 at 6:00 am
Categories: Foundries, Intel Foundry

Intel’s 18A process technology has become one of the most scrutinized semiconductor manufacturing nodes in the industry. It represents Intel’s introduction of two major innovations: RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery (BSPD). These technologies are intended to improve transistor performance, power efficiency, and overall chip density while helping Intel regain process leadership. However, Intel’s roadmap does not stop with 18A. The company has introduced Intel 18A-P, an enhanced version of the 18A platform that offers significant improvements in performance, power, thermal behavior, and design flexibility.

At first glance, Intel 18A-P may appear to be simply a minor revision of Intel 18A. In reality, it is a strategically important process enhancement that allows Intel and its foundry customers to achieve better product performance without waiting for the next major node, Intel 14A. Similar to how TSMC has developed optimized versions of its process technologies such as N5P and N3P, Intel 18AP extracts additional value from the 18A technology platform while maintaining compatibility with existing designs.

Both Intel 18A and Intel 18A-P utilize RibbonFET transistors and PowerVia backside power delivery. RibbonFET replaces the traditional FinFET structure with stacked nanosheets that provide improved electrostatic control of the transistor channel. PowerVia moves power routing to the backside of the wafer, reducing congestion on signal routing layers and improving overall performance. These innovations are foundational technologies shared by both nodes.

The primary difference is that Intel 18A-P incorporates several optimizations that improve power, performance, and thermal characteristics. Intel has disclosed that 18A-P can provide approximately 9% higher performance at the same power level or about 18% lower power consumption at the same performance level compared with standard 18A. These are substantial improvements, particularly in markets where energy efficiency and performance per watt are critical.

Intel 18A-P also introduces additional transistor options, including enhanced RibbonFET variants sometimes referred to as “Power Boost” devices. These allow designers to optimize different sections of a chip for maximum speed, lower leakage, or improved efficiency. The process also includes interconnect enhancements that reduce resistance, helping signals travel more efficiently through the chip.

Another significant improvement is thermal performance. Intel has indicated that 18A-P reduces thermal resistance by approximately 20% to 40% compared with 18A. Better thermal behavior means heat can be removed more effectively from the silicon, allowing chips to sustain higher performance levels without exceeding thermal limits. This is especially important for artificial intelligence accelerators, high-performance computing devices, and next-generation server processors.

From a design perspective, one of the most attractive aspects of 18AP is its compatibility with 18A. Customers that begin development on 18A can migrate to 18A-P with relatively limited redesign effort. This reduces risk while providing access to improved power and performance characteristics. For foundry customers, this compatibility can significantly shorten development cycles and lower engineering costs.

Why does this matter? The semiconductor industry is increasingly driven by performance-per-watt requirements rather than raw transistor scaling alone. Data centers, AI systems, and advanced computing platforms demand greater efficiency because power consumption and cooling costs are becoming major constraints. A process technology that delivers nearly double-digit performance gains and significant power reductions can directly affect product competitiveness and profitability.

For Intel Foundry, 18A-P is also strategically important because it demonstrates that Intel can offer customers not only breakthrough technologies but also a mature roadmap of optimized derivatives. The availability of 18A-P provides customers with confidence that their investments in 18A-based designs can continue to deliver improved results over time.

Bottom line: Intel 18A introduced the revolutionary technologies of RibbonFET and PowerVia, while Intel 18A-P refines and enhances those innovations. The result is higher performance, better energy efficiency, improved thermal behavior, and greater design flexibility. For both Intel and its foundry customers, 18A-P represents an important bridge between the initial 18A generation and future nodes such as Intel 14A, making it one of the most significant process enhancements in Intel’s recent manufacturing road map.

See More About Intel Process Innovation

Also Read:

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes

Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026

Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools

June 25, 2026June 25, 2026

WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA Workloads

In this webinar, Google Cloud and NetApp explore how semiconductor companies can address the growing infrastructure demands of modern Electronic Design Automation (EDA) workflows. As process technologies continue to advance and chip designs become increasingly complex, engineering teams require scalable, high-performance infrastructure capable of supporting massive datasets, large compute clusters, and demanding storage requirements. Google Cloud NetApp Volumes is presented as a key technology that helps organizations modernize EDA environments while improving performance, scalability, and operational efficiency.

REGISTER HERE

The webinar highlights the unique characteristics of EDA workloads and why they place extraordinary demands on storage systems. Front-end design and verification processes generate millions of small files and metadata operations that require low-latency access and high IOPS performance. Back-end design, physical verification, and signoff workloads create large sequential data streams that demand substantial throughput and parallel access capabilities. In addition, production testing and silicon validation workflows generate significant volumes of simulation outputs, test vectors, and manufacturing data that must be stored, managed, and analyzed efficiently.

A major theme of the discussion is the scale of modern semiconductor development. Today’s projects can generate hundreds of terabytes of data and involve deeply nested directory structures containing millions or even billions of files. Engineering teams are often distributed across multiple geographic locations and require secure, high-performance access to shared design libraries, intellectual property (IP), and verification results. The presenters emphasize that storage bottlenecks can directly impact engineering productivity, delay project milestones, and extend time-to-market.

The webinar also examines how Google Cloud has developed a comprehensive ecosystem for semiconductor design. This ecosystem includes high-performance compute instances, GPU accelerators, workload scheduling technologies, and cloud-native management tools designed to support EDA, HPC, and AI-driven workflows. However, the presenters stress that compute resources alone are not enough. To fully realize the benefits of cloud-based EDA, organizations need storage infrastructure capable of delivering consistent performance at scale.

Another important discussion point is cloud elasticity. Semiconductor workloads often experience significant fluctuations in resource demand, particularly during verification cycles, tape-out preparation, and signoff activities. Google Cloud enables organizations to scale compute resources on demand, while NetApp Volumes allows storage capacity and performance to scale alongside those workloads. This flexibility helps organizations avoid the costs associated with overprovisioning traditional on-premises infrastructure.

The webinar concludes by emphasizing that storage performance and scalability have become critical factors in semiconductor innovation. By combining Google Cloud’s scalable infrastructure with NetApp’s enterprise storage technology, organizations can improve resource utilization, accelerate design cycles, support hybrid cloud strategies, and enable the next generation of EDA workloads. As semiconductor complexity continues to increase, solutions such as Google Cloud NetApp Volumes are positioned as an important foundation for future design environments.

REGISTER HERE

SPEAKERS:

Oliver Krause – Principal Product Manager

Oliver Krause is a product manager at NetApp for Google Cloud NetApp Volumes. He has over 25 years experience working with large and small companies to architect the right solution for their data storage needs.

Raja Sandireddy, Product Manager, Google Cloud Raja

Sandireddy is a seasoned Product Leader with over 20 years of experience spanning product management, marketing, and software engineering. Currently a Product Manager at Google Cloud, driving Cloud Storage innovations for Google Cloud NetApp Volumes, with prior ownership of Cloud Compute solutions.

Also Read:

Panel Discission: Beyond Moore’s Law and the Future of Semiconductor Manufacturing

WEBINAR: Beyond Moore’s Law and The Future of Semiconductor Manufacturing Intelligence

GTC 2026: Agentic AI for Semiconductor Design and Manufacturing

June 25, 2026June 25, 2026

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late
by Mike Gianfagna on 06-25-2026 at 10:00 am
Categories: AI, EDA, Events, llmda.ai

Embedded systems programs often fail because critical engineering documentation drifts out of alignment over time and distance. This results in a team that is correctly following the wrong instructions. All forms of engineering documentation suffer from this problem, and it really is the silent killer of many programs.

llmda.ai recently presented a webinar on this topic. If you missed it, the good news is that a reply link is now available. I’ll get to that in a moment. I did attend the webinar, and I want to offer some eye-witness comments about its content. The material is on point, compelling and very useful. It will show you how to free yourself from inconsistent engineering documentation before it’s too late

What You Will Learn

Some of the opening comments will get your attention:

Engineering documentation requires complete grounding in authoritative engineering artifacts such as specifications, requirements, RTL, and test plans. These items serve as a reliable system of record and source of truth.
In this webinar, we will explore why engineering documentation is fundamentally different from marketing or general content creation.
The scale and complexity of engineering data presents unique challenges, with technical reference manuals often exceeding thousands of pages, creating significant constraints for conventional LLM-based approaches.
Finally, we will demonstrate llmda Spectra, a purpose-built platform for producing engineering-grade documentation, and address common questions about the use of AI for documentation.

The webinar then explores the problem of fragmentation across the silicon lifecycle.

Here, critical information is distributed across architecture specs, RTL, verification environments, and software interfaces. Manual synchronization fails to scale with design complexity.

This phenomenon, often referred to as design drift, creates a growing disconnect between specification, implementation, verification, and documentation. As changes accumulate across teams and tools, engineers must spend significant time manually reviewing and reconciling vast amounts of data to determine which artifacts accurately reflect the current state of the design.

Maintaining a single source of truth becomes increasingly difficult in a dynamic development environment where requirements, designs, and implementations are constantly evolving. The result is higher engineering costs, longer development cycles, increased compliance risk, and documentation that often lags the actual product.

Next, how AI can help is discussed.

Here, AI should do more than generate content—it should actively maintain consistency as information moves through the design lifecycle. As engineering data is transformed across architecture, RTL, verification, software, and implementation teams, AI should continuously reconcile changes, synchronize artifacts, and prevent design drift.

But what kind of AI is useful here? Many organizations are mandating AI adoption with popular and powerful generic LLMs. But generic LLMs are architected for conversational intelligence and broad knowledge synthesis—not repeatable, auditable, engineering output. This is the hidden flaw of this approach. The webinar digs into this topic to explain what’s really needed.

Anthropic’s popular ecosystem is used as an example of what generic LLMs can and cannot do. A comparison is made between this approach and the platform llmda.ai can deliver.

First, a general-purpose LLM such as Claude is used as the core intelligence layer of the system. While these models provide strong language understanding and content generation capabilities, they are inherently probabilistic in nature. As a result, achieving reliable and repeatable engineering-grade outputs requires significant additional engineering effort. Organizations must build surrounding infrastructure such as documentation pipelines, source grounding mechanisms, approval workflows, routing logic, and multi-layered human review processes to enforce consistency and correctness. In practice, much of the complexity shifts from documentation creation to system integration and validation.

An alternate approach is to use a purpose-built system designed specifically for engineering documentation. It is explained that llmda Spectra™ has been developed over two years with a focus on solving the core challenges of engineering-grade documentation generation. Rather than treating documentation as an isolated output, Spectra is designed to ingest, connect, and continuously synchronize across all relevant engineering artifacts. This enables the system to maintain consistency, traceability, and alignment across evolving specifications, designs, and verification data.

A live demonstration of llmda Spectra is then provided. This lets you see the product in action so you can begin to understand its impact on documentation accuracy and overall system design quality and predictability.

The webinar concludes with a spirited Q&A session that covers many important topics. Some examples include:

How broad are the documentation generation capabilities of llmda Spectra?
Several questions about using a tool like Claude and what the impact of changing to llmda Spectra will be.
Concerns about documentation accuracy and hallucinations are also addressed.

To Learn More

This webinar treats a critical item for system design success, how to ensure you are building the right system from the start. If complex system design is part of your world, this webinar is a must-see event. You can access the webinar replay here. This will show you how to free yourself from inconsistent engineering documentation before it’s too late

Also Read:

How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler

WEBINAR: Engineering Documentation is a Critical Source of Truth – Do You Know if it’s Accurate?

Podcast EP349: llmda.a’s Unique AI Fabric for Embedded Systems Development with Nagesh Gupta

June 25, 2026June 25, 2026

COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era

COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore “EDA+IP” Synergy for the AI Era
by Daniel Nenni on 06-25-2026 at 6:00 am
Categories: AI, Andes Technology, Prototyping, RISC-V, S2C EDA

COMPUTEX 2026 officially concluded under the theme “AI Together,” bringing the global semiconductor and computing ecosystem together to showcase the latest advances in artificial intelligence, HPC, and intelligent systems. While AI accelerators and advanced computing platforms dominated the exhibition floor, one collaboration stood out for addressing a critical challenge facing the industry: how to efficiently design and verify increasingly complex AI chips.

S2C, the world’s largest company focused exclusively on prototyping verification solutions, joined forces with Andes Technology, a leading provider of RISC-V processor IP, to demonstrate how deep integration between EDA platforms and processor IP can accelerate AI innovation. The companies delivered a joint technical presentation and hosted a live demonstration of the Andes AX66 Edge AI platform running on S2C’s flagship Prodigy S8-100 prototyping system.

Solving AI Complexity Through Collaboration

The rapid growth of AI and HPC workloads has dramatically increased SoC complexity. Modern designs routinely incorporate multi-core processor clusters, specialized AI accelerators, and custom instruction extensions. At the same time, chip sizes are approaching hundreds of billions of gates, creating significant challenges for traditional verification and prototyping methodologies.

To address these challenges, S2C and Andes have strengthened their long-term partnership by combining advanced RISC-V processor technology with state-of-the-art FPGA-based prototyping solutions. The goal is to enable engineers to evaluate architectures, validate software, and identify hardware issues much earlier in the design cycle.

At COMPUTEX, the companies showcased this approach through both technical presentations and a real-time AI inference demonstration.

The demonstration featured Andes’ AX66 processor IP, compliant with the latest RVA23 RISC-V standard, implemented on S2C’s Prodigy S8-100 platform. Together, the technologies created a highly integrated hardware emulation environment capable of supporting advanced software workloads.

Running on a Linux KVM virtualization platform, the system launched two virtual machines, each executing a Large Language Model (LLM) based on the Llama2 architecture. The live demo highlighted TinyStories, a lightweight language model containing approximately 42 million parameters. Although modest in size compared to today’s frontier AI models, TinyStories demonstrated how RISC-V processors can efficiently support edge AI applications where power consumption, cost, and deployment flexibility are critical considerations.

The Power of Advanced Prototyping

At the heart of the demonstration was S2C’s latest-generation Prodigy S8-100 prototyping system, powered by the AMD Versal™ Premium VP1902 adaptive SoC. The platform provides approximately 100 million ASIC-gate equivalent capacity per FPGA, making it well suited for validating large-scale multi-core and AI-intensive designs.

As semiconductor designs continue to grow in complexity, single-FPGA solutions often struggle to provide sufficient capacity. S2C addresses this challenge through advanced multi-FPGA prototyping technology and a comprehensive hardware-software co-design environment.

The company’s ecosystem includes tools such as Player Pro, which simplify compilation, design partitioning, and multi-FPGA debugging. These capabilities enable engineering teams to perform deep hardware verification while simultaneously validating operating systems, drivers, middleware, and AI software stacks. By allowing hardware and software development to proceed in parallel, companies can significantly reduce development risk and accelerate time-to-market.

Building a Complete RISC-V Ecosystem

“The explosion of AI, autonomous driving, and HPC applications is pushing chip complexity to unprecedented levels,” said Ying, Vice President of S2C. “When designs reach hundreds of billions of gates, no single company can innovate alone. Customers need complete solutions that help them evaluate architectures, adopt new technologies, and accelerate product development.”

According to Ying, S2C is focused on lowering the barriers to innovation by building an open ecosystem that integrates processor IP, architecture evaluation, software development, and application validation early in the design process.

That strategy is reflected in S2C’s three core strengths: more than two decades of prototyping expertise, close collaboration with leading ecosystem partners such as Andes Technology, and a global support infrastructure that provides localized technical assistance worldwide.

Bottom line: From high-performance multi-core validation to edge AI inference, the S2C-Andes collaboration demonstrates how tightly integrated EDA and IP solutions can help drive the next wave of RISC-V innovation. More importantly, it illustrates a complete methodology centered on ecosystem collaboration, workflow optimization, and early verification—one that can guide advanced AI and RISC-V designs from concept to mass production faster and more efficiently than ever before.

Contact S2C

Also Read:

Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox

Accelerating Advanced FPGA-Based SoC Prototyping With S2C

June 24, 2026June 25, 2026

The Wedding of the Year: Why AI Infrastructure Financing Is Becoming a Semiconductor Story

The Wedding of the Year: Why AI Infrastructure Financing Is Becoming a Semiconductor Story
by Jonah McLeod on 06-24-2026 at 2:00 pm
Categories: AI

Every family has that one wedding where, halfway through the toasts, someone leans over and whispers “wait, who’s paying for all this?” This is that wedding. OpenAI and Broadcom are the happy couple. Apollo Global Management walked the bride down the aisle. Nvidia may have just stood up to offer a toast, a very expensive one, for a second ceremony happening simultaneously in Ohio.

The metaphor is useful for exactly one reason: it captures the strangeness of what is actually happening. Semiconductor companies are no longer just designing chips and collecting purchase orders. They are underwriting deployment. They are co-signing leases. They are guaranteeing that AI infrastructure gets built whether or not the tenant can ultimately pay for it. That is the new story.

What follows sets aside the wedding and focuses on what this financing structure means for the semiconductor industry: which companies are exposed, what volumes are implied, and what the downstream effects look like for foundries, packaging, and memory.

Section 1: What Broadcom Actually Filed

Start with what is in the public record. Broadcom’s Form 10-Q for the fiscal quarter ended May 3, 2026, filed June 9, 2026, discloses in Note 11 (Subsequent Events) that on June 8 an investor partner agreed to purchase AI racks built around Broadcom’s custom chips, with related lease agreements covering compute access. Broadcom guaranteed those lease obligations for up to $29 billion, escalating as racks deploy and decreasing as payments are made.

Item 5 of that same filing identifies the investor partner as Apollo Global Management, which manages approximately $700 billion in assets. Apollo bought the racks. Apollo holds the lease. Broadcom is acting as guarantor to Apollo in the event OpenAI defaults.

The structure is straightforward: OpenAI gets compute access without deploying capital upfront; Apollo gets a yield-bearing infrastructure asset backstopped by Broadcom’s balance sheet; and Broadcom gets a committed customer for its custom AI silicon at a scale that justifies the design services investment. The $29 billion is a contingent liability, real exposure, in its SEC filing.

One additional reported element: according to an internal OpenAI memo cited in trade press, Broadcom originally conditioned the first phase of the chip program on Microsoft agreeing to purchase roughly 40 percent of the packaged silicon, installed in Microsoft’s data centers with compute rented back to OpenAI. OpenAI’s own head of compute reportedly called that arrangement financially unattractive and likely unworkable. Whether Apollo’s entry as investor partner resolved the Microsoft condition is not in any filing. The Microsoft piece remains unconfirmed.

Section 2: Why This Is Unusual

For most of the history of the semiconductor industry, the commercial relationship between chip vendors and customers was relatively clean: a customer needed silicon, a vendor designed and manufactured it, a purchase order changed hands. The vendor’s balance sheet exposure ended when the wafers shipped. Infrastructure financing was the hyperscaler’s problem.

What Broadcom has done here is different. By guaranteeing $29 billion in lease obligations, Broadcom has subordinated its balance sheet to OpenAI’s ability to generate revenue from the compute it is leasing. Broadcom is no longer just supplying the silicon inside the rack; it is now the guarantor for whether the rack gets paid for at all. That may prove to be the most important structural change in the AI hardware industry in this cycle. Semiconductor vendors are no longer merely suppliers. They are becoming financial participants in deployment.

Gil Luria, an analyst at D.A. Davidson, framed the underlying tension plainly in comments to the Financial Times: OpenAI is in no position to make commitments of this magnitude on its own. The company generates approximately $12 billion in annual revenue against projected cumulative cash burn of $115 billion through 2029. OpenAI has signed approximately $1 trillion in infrastructure agreements with Nvidia, Broadcom, AMD, Oracle, and CoreWeave. The math only works if the silicon vendors and alternative asset managers are willing to carry the financing until AI inference revenue scales. That is what Apollo and Broadcom have agreed to do.

This is not how chip companies have historically operated. It may be how they operate going forward.

Section 3: Why Nvidia May Follow; With Important Caveats

Media reporting indicates that Nvidia is in discussions to act as financial guarantor for OpenAI’s lease obligations on a proposed 10-gigawatt AI campus in Ohio; the former Portsmouth uranium enrichment plant in Pike County. If confirmed, Nvidia’s guarantee would cover both the lease obligations and the energy financing for a facility powered by approximately 9.2 gigawatts of planned natural gas generation from SB Energy.

As of this writing, there is no Nvidia 8-K or 10-Q disclosing this commitment. The Ohio information rests entirely on trade press sourcing. Readers should weight it accordingly and wait for a filing before treating it as confirmed.

Nvidia’s financial ability to make such a commitment is not in question. In fiscal Q1 2026, Nvidia generated $81.6 billion in revenue at 75 percent gross margins. Operating cash flow for the quarter exceeded $50 billion. The board approved an additional $80 billion share repurchase authorization on top of $38.5 billion already remaining. A guarantee that catalyzes $500 billion in AI infrastructure buildout; infrastructure that will be filled with Nvidia GPUs; is less a financial risk than a demand-creation mechanism funded by excess cash. The guarantee is the cost of making sure the order gets placed.

To provide a glimpse of the financial landscape, Nvidia’s January 2026 10-Q disclosed that its prior $100 billion commitment to OpenAI carried no assurance of completion. By March, the CEO confirmed the figure had contracted to $30 billion in compute. The Ohio number, reported at $500 billion; should be read in that context. Filings tend to be more conservative than announcements.

Section 4: The Semiconductor Implications

This is what SemiWiki readers actually need to think through. The financial engineering is interesting, but the chip and systems consequences are the story.

Silicon volume implied by $29 billion

The Broadcom guarantee is tied to AI rack procurement. Depending on rack configuration and accelerator density, the guarantee could correspond to thousands of AI racks. Broadcom’s custom AI ASIC, designed in close collaboration with OpenAI’s silicon team, is the primary compute element in those racks. That is meaningful volume for a custom ASIC program that was, until recently, operating below the visibility threshold of most industry analysts.

Does Broadcom become a hyperscaler-scale AI silicon supplier?

Broadcom has historically served hyperscalers with networking ASICs (Tomahawk, Trident series) and custom compute under its Custom Silicon Group. This program represents a qualitative step: Broadcom is now co-designing the primary training and inference compute element, not just the switching fabric. The margin profile of those two businesses is different, and CFO Kirsten Spears addressed it directly on the Q2 call. Guiding consolidated gross margin from approximately 78% in Q2 down to 74% in Q3, she told analysts the decline “does not represent a structural change in semiconductor margin” — it reflects product mix, as lower-margin custom AI accelerators scale faster than the higher-margin communications chip franchise. If the OpenAI program ramps toward the $29 billion guarantee ceiling, that mix shift accelerates.

Custom AI silicon programs require years of engineering investment and billions of dollars of manufacturing capacity commitments before a single rack ships. By helping ensure that deployment actually occurs, Broadcom is protecting not only future chip revenue but also the utilization of the design, packaging, and manufacturing ecosystem built around the program. The guarantee is, in part, a mechanism for making certain that the investment already made in getting to production does not go unrecouped.

Custom silicon versus Nvidia GPU dependence

OpenAI’s dual-path strategy: Broadcom custom ASIC for the longer term, Nvidia GPUs for the Ohio facility in the nearer term reflects the standard hyperscaler logic: own your own silicon roadmap while maintaining merchant silicon optionality. Google, Amazon, and Microsoft have all pursued variants of this. The difference is execution timeline. OpenAI’s custom chip program slipped from a Q2 to a Q3 2026 target. That slip is why Nvidia’s Ohio path, if it materializes, comes online first and generates inference revenue that partially carries the custom silicon program through to completion.

TSMC capacity and packaging implications

Both paths have to go through TSMC. Broadcom’s custom AI ASIC is almost certainly on a leading-edge node; N3 or N2; given the compute density requirements. Nvidia’s Blackwell and next-generation GPU architectures are similarly TSMC N3/N2. A $500 billion Ohio campus filled with Nvidia GPUs implies sustained TSMC CoWoS (Chip-on-Wafer-on-Substrate) demand for the advanced packaging that connects GPU dies to HBM stacks. TSMC has been capacity-constrained on CoWoS for multiple consecutive quarters; OpenAI’s buildout, if it proceeds at reported scale, compounds that constraint further.

HBM demand

High-bandwidth memory is the other constrained variable. Each Nvidia Blackwell GPU ships with HBM3e; each custom AI ASIC of this class requires comparable memory bandwidth. At the rack volumes implied by either guarantee; Broadcom’s $29 billion confirmed, Nvidia’s Ohio reported; the HBM demand increment is meaningful for SK Hynix and Micron, both of which are already operating near HBM capacity limits. OpenAI’s buildout is not the only driver, but it is an incremental one that HBM supply chain planners will need to account for as they set capacity investment priorities through 2027 and 2028.

What this means for AI factory economics

The broader pattern is worth noting. Broadcom’s guarantee and Nvidia’s reported guarantee represent a model where semiconductor vendors effectively become the balance sheet behind AI infrastructure deployment; not by building data centers, but by underwriting the financing structures that allow hyperscalers and AI labs to deploy at a scale their own revenue cannot currently support. If this model spreads, the semiconductor industry’s financial exposure to AI adoption curves becomes structurally deeper than it has ever been. The upside is that chip companies now have a direct financial interest in accelerating deployment. The risk is that balance sheet exposure to a single tenant’s revenue performance is a different kind of risk than the cyclical demand risk chip companies have historically managed.

The Reality of the Toast

Two of the most important hardware companies in the world have independently concluded that the safest way to support OpenAI’s buildout isn’t to hand over cash; it is to co-sign something and hope. Broadcom’s commitment is documented in an SEC filing. Nvidia’s reported commitment awaits similar disclosure.

The semiconductor industry has spent fifty years in the business of designing chips and collecting purchase orders. It is now also, apparently, in the business of underwriting AI infrastructure. The center of gravity has shifted; from silicon design to financial engineering; and the implications for TSMC capacity, HBM supply chains, packaging constraints, and custom silicon economics are only beginning to be visible in the filings.

Watch the next Nvidia 10-Q. That filing will either confirm a new model for how semiconductor vendors participate in AI deployment — or reveal that the reported commitment was never what it appeared to be.

Also Read:

Broadcom Told the Truth. The Market Hasn’t Heard the Rest of It Yet.

From the Selfie to Samantha: The Next Trillion-Dollar Behavior

Is Intel About to Take Flight?

June 24, 2026June 25, 2026

The Modulator Is Not the Product: Why AI Photonics Needs an Electro-Optical Realization Corridor

The Modulator Is Not the Product: Why AI Photonics Needs an Electro-Optical Realization Corridor
by Moh Kolb on 06-24-2026 at 10:00 am
Categories: Photonics

Co-packaged optics, silicon photonics, optical I/O, and photonic engines are becoming central topics in the future of AI infrastructure.

The common story is simple:

Copper is reaching limits.
Light can move data farther and more efficiently.
Therefore, AI systems will move from electrical interconnects toward optical interconnects.

That story is directionally correct, but incomplete.

The real product challenge is not only the photonic device. It is not only the modulator, the photodiode, the laser, the waveguide, or the optical engine. Those are critical components, but they are not the full system.

For AI infrastructure, the product is the full electro-optical realization path.

That path includes:

electrical launch → ASIC / SoC interface → EIC → PIC → modulator / photodiode / optical engine → coupling → fiber array attach → package substrate → TIM → underfill → adhesive system → heat spreading → thermal stability → mechanical alignment → signal and power integrity → wafer-level test → package-level test → module test → yield → reliability → lifecycle evidence

This is why I believe we need a stronger way to describe the problem.

I call this the Electro-Optical Realization Corridor, or EORC.

An EORC is the complete realization path where electrical, optical, thermal, mechanical, material, manufacturing, test, yield, reliability, and lifecycle constraints must converge before optical interconnect becomes trusted at system scale.

Inside this corridor, an Electro-Optical Realization Block, or EORB, is the local multi-material integration zone where the electrical interface, photonic engine, coupling structure, fiber attach, substrate, TIM, underfill, adhesive system, package environment, thermal behavior, mechanical alignment, and test access come together.

The distinction matters.

A photonic device can work.
A modulator can demonstrate strong bandwidth.
A photodiode can show excellent sensitivity.
A laser can meet target performance.
A coupling structure can show low insertion loss.
An optical engine can pass a controlled lab demonstration.

But AI infrastructure does not buy isolated device success.

AI infrastructure needs manufacturable, testable, package-integrated, thermally stable, yield-capable, serviceable, and reliable electro-optical systems.

That is a different problem.

Silicon Photonics Is Becoming a Materials-Integrated Realization Stack

There is another reason the device-only view is incomplete.

A silicon photonics product is not only a PIC, an EIC, a waveguide, a modulator, or a fiber interface. It is a materials-integrated realization stack.

The realized optical engine depends on many physical contributors:

TIM,
heat spreading,
underfill,
build-up film,
glass core or substrate platform,
UV adhesives,
fiber array attach,
coupling structures,
waveguides,
reflectors,
meta-lens elements,
package assembly,
test access,
and module-level reliability.

Each material and interface changes the final behavior of the system.

A UV adhesive is not only an assembly material. It can affect optical alignment, coupling stability, thermal drift, aging behavior, and field reliability.

An underfill is not only mechanical support. It can influence stress transfer, warpage, interface reliability, and optical alignment.

A TIM is not only a thermal material. It can change temperature gradients, wavelength stability, mechanical stress, and long-term optical performance.

A build-up substrate or glass core is not only a platform. It becomes part of the electrical, mechanical, thermal, and optical realization path.

This means silicon photonics is not only moving from copper to light. It is moving from device performance to multi-material realization.

That shift is important for AI infrastructure.

As optical engines move closer to ASICs, accelerators, switches, and package substrates, the number of coupled interfaces increases. The product must close across materials, structure, process, assembly, thermal behavior, test coverage, yield learning, and reliability evidence.

This is why the EORB should be understood as more than a photonic engine.

The optical engine is not only a photonic device. It is a multi-material electro-optical realization block.

The broader EORC then connects that local block to wafer processing, package assembly, module integration, system operation, lifecycle reliability, and future product learning.

In this view, materials are not secondary details.

They are evidence-bearing elements of the corridor.

CPO Is Not Optics Alone

Co-packaged optics is often described as moving optics closer to the switch ASIC, accelerator, or compute fabric.

That is true, but it hides the deeper integration challenge.

When optics move closer to compute, the optical problem becomes a package problem. The package problem becomes a material-interface problem. The material-interface problem becomes a thermal problem. The thermal problem becomes a reliability problem. The reliability problem becomes a lifecycle evidence problem.

This is the important shift.

CPO is not optics alone.

CPO is packaging realization.

The optical path has to survive real package conditions. The electrical launch must remain clean. The substrate must support escape and routing. The fiber attach must remain stable. The adhesive system must preserve alignment. The thermal environment must not destroy optical alignment, coupling behavior, or wavelength stability. The test strategy must support manufacturing confidence. The reliability data must support product guarantees.

In other words:

Light may solve distance, but realization determines scale.

The Device Is Not the Corridor

A single photonic component can be impressive and still fail to become a scalable AI infrastructure product.

Why?

Because the final system depends on cross-domain closure.

The device does not exist alone. It exists inside a stack of constraints:

electrical signaling,
package routing,
substrate loss,
return path behavior,
thermal gradients,
mechanical stress,
material aging,
adhesive stability,
fiber alignment,
connector reliability,
manufacturing variation,
test access,
calibration burden,
yield learning,
and field degradation.

Each domain can consume margin from another domain.

A thermal drift can become an optical penalty.
A package stress condition can become a coupling penalty.
A routing decision can become a signal-integrity penalty.
An adhesive shift can become an alignment penalty.
A fiber attach variation can become a yield penalty.
A test gap can become a reliability escape.
A material interface can become a lifecycle risk.

This is why electro-optical integration must be treated as a corridor, not as a collection of components.

The corridor is where margins interact.

Materials Are Part of the Evidence

In traditional semiconductor discussions, supply-chain analysis often emphasizes equipment.

That remains important.

But advanced packaging, silicon photonics, hybrid bonding, CoWoS-class integration, HBM integration, and optical engines are making materials central to realization.

Materials are no longer passive inputs.

They shape the final system.

They affect thermal gradients, stress fields, warpage, coupling stability, adhesion, optical loss, electrical performance, moisture sensitivity, aging behavior, rework limits, assembly yield, and long-term reliability.

This creates a new kind of realization evidence.

A material choice must be evaluated not only by its datasheet property, but by how it behaves inside the integrated electro-optical system.

For example:

A TIM must be evaluated through the thermal path, not only thermal conductivity.
An underfill must be evaluated through stress transfer and alignment impact, not only mechanical support.
A UV adhesive must be evaluated through coupling stability and aging behavior, not only bonding strength.
A substrate must be evaluated through electrical, mechanical, thermal, and optical integration, not only routing capability.
A fiber attach process must be evaluated through alignment, assembly tolerance, yield, and lifecycle stability.

This is why material behavior must become part of the electro-optical evidence chain.

In an EORC, materials are not background details.

They are part of the trusted realization record.

From Optical Performance to Realization Evidence

The next challenge for silicon photonics is not only improving optical performance.

It is generating evidence that the full electro-optical path is ready for product use.

That evidence must answer questions such as:

Can the electrical launch remain stable across operating conditions?

Can the optical engine maintain performance under thermal variation?

Can coupling remain stable through assembly and lifecycle stress?

Can the adhesive system preserve alignment over time?

Can the TIM and thermal path preserve optical stability?

Can underfill, substrate, and package stress remain compatible with optical performance?

Can wafer-level, package-level, or module-level test detect the right failure modes?

Can yield loss be traced to specific design, material, package, process, coupling, or assembly contributors?

Can field telemetry improve future product learning?

Can reliability claims be supported by measured evidence, not only model assumptions?

This is where the industry needs to move from device metrics to realization metrics.

Optical device performance is necessary, but not sufficient.

The larger question is:

Can the complete electro-optical corridor generate decision-ready evidence?

Evidence Must Mature Before Authority

In advanced AI systems, data is everywhere.

Simulation data.
Optical test data.
Thermal data.
Material characterization data.
Manufacturing data.
Reliability data.
Field telemetry.
Dashboard outputs.

But data is not automatically evidence.

A simulation result is not validated evidence.
Validated evidence is not causal explanation.
Causal explanation is not decision authority.

For an electro-optical system to be trusted, evidence must mature.

It must have measured correlation.
It must carry uncertainty.
It must preserve boundary conditions.
It must maintain traceability.
It must connect observed behavior to design, material, package, process, test, and assembly contributors.
It must support bounded engineering decisions.

This is where EORC connects naturally to a Scalable Trusted Realization Layer, or STRL.

An STRL treats advanced semiconductor systems as governed realization systems. The goal is not simply to collect more data. The goal is to determine when evidence is mature enough, traceable enough, and causally meaningful enough to support trusted engineering action.

For electro-optical systems, this matters because the failure modes are not isolated.

An optical penalty may have an electrical cause.
A thermal shift may have a packaging cause.
A coupling issue may have an adhesive or alignment cause.
A reliability issue may have a material or assembly cause.
A yield loss may have a coupling, test, substrate, or process contributor.
A field degradation pattern may reflect a hidden interaction between material aging, thermal cycling, mechanical stress, and optical alignment.

Without a trusted realization structure, these interactions can remain hidden until late in the product cycle.

The Electro-Optical Realization Corridor

The Electro-Optical Realization Corridor gives us a clearer way to frame the AI photonics challenge.

It says the product is not simply:

a laser,
a modulator,
a photodiode,
a waveguide,
a fiber interface,
or an optical engine.

The product is the realized corridor:

electrical launch,
photonic conversion,
multi-material package integration,
substrate interaction,
thermal stability,
mechanical alignment,
coupling stability,
testability,
yield control,
reliability evidence,
and lifecycle learning.

This framing is important because the AI infrastructure market will not scale on laboratory performance alone.

It will scale when optical interconnect becomes manufacturable, reliable, testable, serviceable, and trusted in real systems.

That is the shift from photonic device innovation to electro-optical realization.

Why This Matters for AI Infrastructure

AI scaling is often described through compute, memory, bandwidth, and power.

But the deeper challenge is bounded coexistence.

Compute, memory, optics, power delivery, thermal management, packaging, materials, firmware, and reliability do not naturally scale together. Each domain has its own physics, timing, limits, and failure modes.

The next generation of AI systems will require operational coherence across these domains.

That means the optical system cannot be optimized in isolation. It must coexist with the electrical system, the package, the substrate, the thermal path, the adhesive system, the material stack, the power corridor, the manufacturing flow, the test strategy, and the field reliability model.

This is why EORC is not only a photonics concept.

It is a system realization concept.

It connects photonics to packaging.
It connects packaging to materials.
It connects materials to thermal behavior.
It connects thermal behavior to alignment.
It connects alignment to coupling.
It connects coupling to test.
It connects test to yield.
It connects yield to reliability.
It connects reliability to lifecycle evidence.
It connects lifecycle evidence to future design decisions.

Conclusion

Silicon photonics and co-packaged optics are becoming essential to AI infrastructure, but the industry should be careful not to reduce the challenge to a simple copper-versus-light story.

The real question is not only whether light can move data.

The real question is whether the electro-optical path can be realized, manufactured, tested, trusted, and governed at scale.

The modulator is not the product.

The optical engine is not only a photonic device.

The manufacturable electro-optical corridor is the product.

That is why I believe the next phase of AI photonics should be framed not only around devices, engines, or modules, but around the Electro-Optical Realization Corridor.

Final question:

Are we still evaluating photonics as a device technology, or are we ready to evaluate it as a full electro-optical realization system?

Also Read:

CEO Interview with Vivek Raghunathan of Xscape Photonics

Synopsys and TSMC Deepen AI Design Alliance: What It Means

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June 24, 2026June 23, 2026

All-Embracing Multiphysics Analysis for Chiplet-Based Systems

All-Embracing Multiphysics Analysis for Chiplet-Based Systems
by Bernard Murphy on 06-24-2026 at 6:00 am
Categories: 3D IC, 5G, AI, Chiplet, EDA, Synopsys

What systems can accomplish by combining semiconductors, AI, and software seems at times boundless. Chiplet-based semiconductors deliver this promise, allowing a myriad of complex digital, memory, analog and photonic functions to be condensed into a single semiconductor package for higher performance, lower power consumption and lower total system cost. Yet we still demand that these systems be reliable, despite challenging physical constraints inevitable in these highly compressed form factors. To meet this need, multiphysics analysis, joint analysis of electrical, thermal, EM, mechanical and power and signal integrity is an essential component of system design. Individual analyses have been important for many years in single-die designs, progressing more recently to coupled evaluations; now chiplet-based systems have amplified the importance of full multiphysics signoff.

The big multi-die consumers

It wasn’t long ago that multi-die designs seemed exotic. Now they have become ubiquitous, perhaps not in low-end consumer electronics but certainly in many leading systems applications. Datacenters are a primary example. An AI system will combine CPUs, GPUs and a high-bandwidth memory (HBM) stack in a single package. GPUs alone are famous power hogs and memory access in such systems is equally demanding. Thermal load generated by this power draw can throttle performance and trigger mechanical failures, die warpage leading to delamination, broken contacts and more. Other concerns are electromigration (causing aging through wear and failure in connections) and power integrity risks resulting in intermittent functional failures.

Electric vehicles (EVs) introduce similar challenges in a very different context. Power switching devices operate at high voltages and high frequencies, with junction temperatures approaching 200^oC creating similar thermal challenges. This operation also introduces significant parasitic oscillations and electromagnetic interference which can negatively impact reliability in both drivetrain and body/cabin electronics.

More generally in automotive, multiphysics analyses are essential around electronics throughout the car, compelled by safety requirements. Electronic systems in the drivetrain (EV, hybrid or ICE), body and cabin are held to very high safety standards, in a very hostile environment – high temperatures, vibrations and humidity – requiring even tighter control over physical factors. Modern automotive electronics is required to meet safety standards over 15–20 year lifetimes, significantly longer than expectations for consumer electronics.

The wireless infrastructure (cell-towers) supporting phone calls and all the other clever things we can do over cellular must stretch to 15–20 year lifetimes to justify high capital and maintenance costs. These systems share a mix of challenges with the above examples. Thermal degradation is a big concern, not only thanks to the multiple power amplifiers at radio heads but also in increasingly complex MIMO beam management and added AI functionality. Electromagnetic interference in an obvious concern given the nature of an application simultaneously handling many wireless channels.

Huge industries, driving economic growth worldwide, depend on high-performance, reliability and safety in multi-die systems which can only be assured through robust and efficient multiphysics analysis.

Multiphysics analysis is non-negotiable

Methods to analyze each of these factors standalone are well known: thermal analysis starting from localized heat mapping within a semiconductor together with classical heat diffusion modeling and finite-element methods for cooling (radiative, forced air, liquid); Mechanical behaviors such as warping under heating; Electromagnetic analysis (Maxwell) modeling wave behaviors from sources in complex environments; Signal integrity, power integrity and aging.

But modeling standalone is no longer enough. Thermal profiles are not uniform spatially or in time and affect mechanical, aging and other factors. Electromagnetic interference affects signal integrity and power integrity. Use-cases affect all these factors. The only way to accurately model behavior to ensure device reliability in the intended implementation and across a wide range of use-cases is through full multiphysics analysis, concurrent with design.

Following the acquisition of Ansys, Synopsys has released its first Multiphysics Fusion solutions for chiplets and for Multi-Die Designs. For example, the 3DIC Compiler platform incorporates RedHawk-SC for dynamic power integrity analysis, RedHawk-SC Electrothermal for dynamic thermal analysis, and HFSS-IC for high-frequency electromagnetic simulation, within a unified environment. This integration enables concurrent EMIR, thermal, signal integrity, and electromechanical stress signoff. The full range necessary to ensure reliability in multi-die designs required to deliver long lifetimes.

The benefits aren’t just about guard-banding correct operation over the lifetime of devices. Synopsys’ press release announcing these solutions is supported by quotes from MediaTek, NVIDIA and Samsung indicating up to 3X faster IR-drop-aware STA signoff, while accelerating multiphysics design closure by 10X within individual die and across multi-die designs. Similar improvements apply for analog and photonics components in multi-die systems.

Looks like exactly what we expected from a Synopsys/Ansys merger, advancing systems performance and reliability to the demands of leading-edge multi-die designs. You can read the release HERE, an eBook on the Multiphysics Fusion for Multi-Die Designs HERE and an eBook on optimizing analog design with multiphysics HERE.

Also Read:

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June 23, 2026June 22, 2026

Semidynamics Brings Its Full Inference Stack to ISC HPC 2026 — And Why It Matters

Semidynamics Brings Its Full Inference Stack to ISC HPC 2026 — And Why It Matters
by Daniel Nenni on 06-23-2026 at 2:00 pm
Categories: IP, Semidynamics

AI inference is quickly becoming the real battleground for next-generation computing. Training still gets the headlines, but inference is where AI becomes a business, a service, and an infrastructure problem. Every chatbot response, agentic workflow, code assistant, scientific model, and enterprise copilot depends on the ability to run large models efficiently, repeatedly, and at scale. That is why Semidynamics’ appearance at ISC High Performance 2026 this week in Hamburg matters.

Semidynamics is bringing a full silicon-to-rack inference stack to the show, positioning itself not merely as a RISC-V IP supplier, but as a systems-level AI infrastructure company. The message is direct: inference performance is no longer defined by peak TOPS alone. It is defined by how much of that compute can actually be used once memory, data movement, latency, model size, and rack-level integration are taken into account.

That distinction is important. Modern AI workloads are increasingly memory-bound. Large language models require massive movement of weights, activations, and KV-cache data. As context windows expand and agentic AI systems maintain longer-running sessions, the memory footprint grows dramatically. A chip can advertise impressive arithmetic throughput, but if the memory subsystem cannot keep the execution units fed, much of that performance remains theoretical. Semidynamics is trying to attack the problem at the architectural level.

The company’s approach starts with RISC-V, but it does not stop at the CPU. Semidynamics has built an “all-in-one” architecture that integrates scalar, vector, and tensor processing more tightly than traditional accelerator approaches. Instead of treating matrix acceleration as a bolt-on block connected through layers of software and data orchestration, Semidynamics is emphasizing programmability, memory efficiency, and tighter coupling across the compute pipeline. Its Gazzillion Misses technology is intended to hide memory latency and keep compute resources active, while its vector and tensor capabilities target the mixed workload profile of real AI inference.

The ISC HPC 2026 story is also about ambition. Semidynamics is talking about 3nm silicon, boards, and liquid-cooled OCP-compliant racks. That is a major shift in posture. The company is not simply selling a core or a block of IP into someone else’s system. It is presenting a full-stack platform aimed at data center inference, from the processor architecture through system packaging and deployment.

Why does this matter? First, AI infrastructure buyers are under pressure to reduce total cost of ownership. Inference is a high-volume workload, and small improvements in utilization, memory efficiency, and power consumption can translate into large economic differences at fleet scale. A memory-centric architecture that improves usable compute could be more valuable than one that simply wins a peak benchmark.

Second, the market needs credible alternatives. The AI hardware ecosystem has been dominated by a small number of large incumbents, and supply, cost, sovereignty, and specialization concerns are pushing customers to look at new architectures. A European RISC-V company showing a complete inference stack at a major HPC event is strategically significant, especially as Europe debates how to participate more directly in the AI compute race.

Third, inference workloads are changing fast. Agentic AI is not just a sequence of isolated prompts. It involves planning, tool use, memory, retrieval, multi-step reasoning, and long-lived sessions. That shifts the bottleneck from raw matrix math toward memory capacity, bandwidth, latency, software flexibility, and system-level orchestration. Semidynamics’ thesis is that the winning architecture for this era will be the one that keeps data close, keeps compute busy, and scales from silicon to rack without excessive overhead.

Bottom line: The company still has to prove itself in silicon, software maturity, ecosystem adoption, and customer deployments. But the direction is notable. At ISC HPC 2026, Semidynamics is making a bigger claim than “RISC-V can do AI.” It is arguing that the next phase of AI inference will be won by architectures designed around memory realities from the start.

That is exactly the conversation HPC needs to have.

Also Read:

Why Europe Needs Its Own AI Supercomputing Platform

Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips

Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems

June 23, 2026June 22, 2026

Chips&Media Signs Next-Gen ‘AV2’ Video IP Licensing Deal with North American Big Tech, Strengthening Global Standards Leadership

Chips&Media Signs Next-Gen ‘AV2’ Video IP Licensing Deal with North American Big Tech, Strengthening Global Standards Leadership
by Daniel Nenni on 06-23-2026 at 10:00 am
Categories: Chips&Media, IP

Chips&Media, a leading provider of video intellectual property (IP) solutions, has announced a strategic licensing agreement with a major North American technology company for its next-generation AV2 video codec IP. The agreement marks a significant milestone for the company as demand accelerates for advanced video processing technologies capable of supporting ultra-high-resolution streaming, artificial intelligence (AI)-enhanced media applications, cloud gaming, and next-generation content delivery platforms.

The AV2 codec, widely regarded as the successor to AV1, is being developed to address the rapidly growing bandwidth and efficiency requirements of modern video ecosystems. As video traffic continues to account for the majority of global internet data consumption, semiconductor companies and system developers are seeking more efficient compression technologies that can deliver higher quality video at lower bitrates while reducing power consumption and infrastructure costs.

Under the new agreement, Chips&Media will provide its AV2 hardware encoder and decoder IP cores for integration into custom system-on-chip (SoC) platforms targeting data centers, AI infrastructure, edge computing systems, and consumer devices. The licensing deal reflects growing industry confidence in Chips&Media’s ability to deliver standards-compliant video processing solutions with optimized silicon area, low power consumption, and high-performance throughput.

The AV2 architecture introduces significant improvements over previous codec generations. Early industry projections suggest compression efficiency gains of 30% to 50% compared to AV1, enabling content providers to reduce storage and transmission requirements while maintaining equivalent visual quality. Such improvements are increasingly important as 8K video, immersive media, virtual reality (VR), augmented reality (AR), and AI-generated content place unprecedented demands on network and compute resources.

Chips&Media’s implementation leverages a highly configurable hardware architecture that supports scalable video coding, advanced motion compensation techniques, adaptive transform processing, and AI-assisted encoding optimizations. The company’s design methodology allows customers to tailor codec configurations based on application-specific requirements, balancing performance, silicon area, memory bandwidth, and energy efficiency.

The licensing agreement also highlights the growing importance of dedicated video acceleration hardware in AI-centric computing environments. Large-scale AI models increasingly process multimodal data streams combining video, audio, and text. Efficient video compression and decompression have therefore become critical components of AI training pipelines, inference workloads, and real-time content analysis systems. Hardware-based AV2 acceleration can significantly reduce CPU and GPU utilization, improving overall system efficiency while lowering operational costs.

Industry analysts view the agreement as further validation of Chips&Media’s long-standing position within the global video IP market. The company has established a strong reputation for delivering production-proven codec solutions supporting standards including H.264/AVC, H.265/HEVC, VP9, AV1, and VVC. Its technology has been integrated into a broad range of semiconductor platforms used in smartphones, smart TVs, automotive systems, surveillance equipment, and cloud infrastructure.

The North American customer, while not publicly identified, is expected to deploy the AV2 IP across multiple product categories. Such deployments could accelerate ecosystem readiness as industry stakeholders begin evaluating AV2 adoption strategies. Early hardware support is often a key factor in driving codec standardization and commercial deployment, particularly in markets where performance and power efficiency are critical competitive differentiators.

Beyond the immediate business impact, the agreement reinforces Chips&Media’s role in shaping the future of video compression standards. Participation in emerging codec ecosystems enables the company to contribute technical expertise while ensuring that its IP portfolio remains aligned with evolving market requirements. As video applications continue expanding across AI, automotive, industrial, consumer, and cloud markets, advanced codec technologies will play a central role in enabling scalable and efficient digital media delivery.

Bottom line: With this latest licensing win, Chips&Media strengthens its global footprint and demonstrates its ability to secure design engagements with leading technology innovators. The agreement underscores the increasing strategic value of video IP as semiconductor companies prepare for the next generation of media processing workloads and standards-based video infrastructure.

Also Read:

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