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Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines

Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines
by Daniel Nenni on 07-13-2026 at 8:00 am

Daniel is joined by Wally Rhines, CEO of Silvaco to discuss the Electronic Design Market Data report that was just released. Wally is the industry coordinator for the EDA data collection program called EDMD. SEMI and the Electronic System Design Alliance collect data from almost all of the electronic design automation companies in the world and compile it by product category and region of the world where the sales occurred. It’s the most reliable data for the EDA industry and provides insight into which design tools and IP are in highest demand around the world.

Wally explains that Q1 2026 was another very good quarter for EDA at 12.7% growth compared to last year. Total revenue was $5.7B. That equates to an annual run rate for the industry of $22.8B. The last four-quarter moving average is 10.3% growth, reflecting the continuing demand for EDA software and IP to fuel the large number of chip and system designs in progress. In this in-depth and informative discussion, Dan explores more details of the report with Wally.

Growth rates across IP and segments of the design flow are discussed, along with details across the regions of the world. Some observations reveal potential industry shifts worth considering. If you want a comprehensive overview of the direction the industry is taking, this discussion will help. Dan and Wally also touch on the upcoming DAC Chips to Systems Conference with discussions about various must-see events.

News Release

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Enabling AI to Understand Complex Runtime Behavior for Accurate, Automated Root Cause Analysis — DAC 2026

Enabling AI to Understand Complex Runtime Behavior for Accurate, Automated Root Cause Analysis — DAC 2026
by Daniel Nenni on 07-13-2026 at 6:00 am

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Undo gives AI coding agents the runtime context they need to solve hard problems in complex software and system verification workflows Undo’s technology records complete program execution, allowing engineers and AI coding agents to understand exactly what happened during execution rather than inferring behavior from source code, logs, or waveforms alone.

Leading semiconductor companies use Undo to accelerate debug across C/C++, SystemC models, and software components used throughout modern silicon development.

Target applications
  • System-level verification (C++/SystemC)
  • Virtual platforms and fast functional models
  • High-Level Synthesis (HLS)
  • Complex EDA applications

Challenges being addressed

Semiconductors

System verification
  • Long regression debug cycles. Failing regressions often require engineers to spend hours or days reproducing failures and tracing through complex software and hardware interactions before they can identify the root cause.
  • Root cause analysis across complex verification environments. As designs grow in complexity, failures can originate anywhere in the verification stack, including the testbench, SystemC models, virtual platforms, firmware, RTL, or the interaction between them – making diagnosis increasingly difficult.
System design architects
  • Limited confidence in architectural exploration. System architects depend on simulation models to evaluate architectural trade-offs before silicon. Functional issues in those models often limit workload coverage, reducing confidence that enough meaningful use cases have been exercised before key design decisions are locked in.
AI-assisted workflows
  • Scaling engineering expertise with AI. Generic LLMs (and even models fine-tuned on proprietary engineering data) cannot capture the deep, experience-based knowledge verification engineers apply when diagnosing failures on real silicon. Runtime context from the live design is far more valuable than only static training data or generic LLM intelligence. Undo provides that runtime context – and you can’t get that data any other way.
  • AI lacks visibility into C/C++ execution. RTL verification benefits from waveforms that capture signal activity over time, providing both engineers and AI with a complete picture of execution. In C/C++ and SystemC, there is no equivalent representation of runtime behavior. Without that runtime evidence, AI agents are forced to infer what happened from source code and logs alone, reducing the accuracy of root cause analysis.
EDA / Computational Software

EDA R&D teams

  • Debugging extremely complex C++ codebases. EDA tools tend to be large and complex codebases that have evolved over decades and therefore are especially difficult to understand.
  • Debugging non-deterministic and hard-to-reproduce failures. Many EDA tools are multi-threaded and process huge customer designers. Incorrect results are incredibly difficult to reproduce and R&D engineers can spend significant time trying to recreate the customer’s environment.
  • Resolving customer escalations. With critical customer designs being blocked, R&D teams often need to rapidly determine whether the issue is a tool defect, a model issue, or customer input. But rigorous IP protection protocols and constrained access to the failing environment make diagnosing issues extremely difficult and time-consuming.

EDA AE teams

  • Reproducing and investigating complex customer issues. When customers encounter crashes, incorrect simulation results, or unexpected behavior on large proprietary designs, the race is on to try to investigate and reduce escalations to R&D.
  • Limited visibility into customer environments. Customers often cannot share their entire design due to IP restrictions. So AEs often have to diagnose problems from incomplete logs, waveforms, stack traces and screenshots.

Target audience

  • System verification teams who need to reduce debug time across their silicon verification workflows.
  • System design architects who need to increase use case coverage and ensure a higher quality design.
  • Engineering leaders driving AI adoption across semiconductor engineering teams and/or responsible for system verification productivity
  • EDA R&D teams working complex EDA applications
  • EDA application engineers responsible for debugging complex EDA software on-site at customers
Booth information

Come meet us on booth # 858 at DAC! Our Solution Architects will be there to demo the tech live, so you can see how it works.

Schedule a DAC Demo

Other DAC engagements:
  • Attend our poster session on “Agentic Time-Travel Debugging for HLS Code”
  • Participate in our raffle to win a free Undo license and a coveted Lego set

Curious about how verification teams at AMD and system design architects at NVIDIA are using Undo’s technology? Get in touch directly with Chirag Goyal (Chair of the System & Software Deployment track at DAC) for an on-site meeting.

Also Read:

Revolutionizing Hardware Design Debugging with Time Travel Technology

Taming Concurrency: A New Era of Debugging Multithreaded Code

Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law


AI Driven Semiconductor Systems

AI Driven Semiconductor Systems
by Daniel Nenni on 07-12-2026 at 8:00 pm

AI Driven Semiconductor Systems NetApp

AI-driven semiconductor systems are the next major transformation in chip design and manufacturing. The central idea is that semiconductor workflows are becoming too complex, too data-intensive, and too time-sensitive to be managed only through traditional human-driven engineering processes. Modern chips now involve billions or even trillions of transistors, advanced packaging, chiplets, 3D integration, heterogeneous architectures, and nanometer-scale manufacturing tolerances. Inside the uploaded IEEE-CASS webinar, Janhavi Giris presentation explains that semiconductors are the “invisible backbone” of major computing eras, from microprocessors to mobile, cloud, and now AI factories .

Technically, semiconductor design is a multi-stage optimization problem. A chip begins with architectural definition and front-end design, where engineers write RTL, simulate behavior, and verify functional correctness. It then moves into physical design, where logic is transformed into manufacturable geometry through floorplanning, placement, routing, clock-tree synthesis, and timing closure. Finally, signoff validates power integrity, timing, design-rule compliance, layout-versus-schematic correctness, reliability, and manufacturability before tapeout. This is not a simple linear pipeline. It is an iterative loop involving massive compute, millions of files, repeated verification, and constant tradeoffs among power, performance, and area.

AI matters because this design space is exploding. Advanced-node chips have too many possible design configurations for manual exploration. AI and machine learning can help search through enormous parameter spaces, recommend floorplans, optimize placement and routing, identify timing violations, triage verification failures, and reduce debug cycles. In electronic design automation, AI can function first as a copilot, then as an agent, and eventually as part of autonomous EDA workflows. Instead of merely assisting engineers, future AI systems may orchestrate entire design flows, launch simulations, compare results, identify root causes, and suggest corrective actions.

Manufacturing is equally complex. A semiconductor fab contains thousands of process steps across many expensive tools, sensors, metrology systems, recipe controls, manufacturing execution systems, and test environments. The deck notes that a typical fab may include around 1,200 multimillion-dollar tools and that wafer processing can span thousands of steps over hundreds of machines. This creates enormous data fragmentation across equipment, process, inspection, metrology, test, and engineering-log systems. AI cannot deliver reliable automation unless that data is unified, standardized, governed, and available in real time.

This is why data architecture becomes the foundation of intelligence. AI-driven semiconductor systems require unified data access, standardized metadata, compute-data locality, and strong governance. Data must move from being a passive archive to an active participant in decision-making. In design, this means connecting RTL, verification logs, synthesis results, physical-design artifacts, timing reports, and signoff data. In manufacturing, it means linking equipment telemetry, sensor data, wafer histories, defect maps, metrology results, test outcomes, and maintenance records. Without this continuity, AI models see only fragments of the system and cannot make trustworthy decisions.

The most important manufacturing applications include advanced process control, predictive maintenance, virtual metrology, dynamic scheduling, yield optimization, root-cause analysis, and back-end process improvement. For example, predictive maintenance can reduce downtime by identifying tool drift before failure. Virtual metrology can estimate wafer quality without measuring every wafer physically, improving throughput. Yield analytics can correlate defects with process conditions across many tools and steps, helping fabs find hidden causes of failures faster.

Why does this matter? First, AI chips are now strategic infrastructure. The AI economy depends not only on models but also on the ability to design, manufacture, package, and scale advanced silicon. Second, time-to-market is critical. Tapeout delays can cause lost market windows and major revenue loss. Third, manufacturing efficiency affects cost, supply-chain resilience, and sustainability. Fabs consume enormous capital, energy, and water, so better optimization has economic and environmental value. Finally, national competitiveness increasingly depends on semiconductor capability.

Bottom line: AI-driven semiconductor systems matter because they connect three critical needs: faster chip innovation, more autonomous manufacturing, and smarter use of massive industrial data. The future semiconductor leader will not simply be the company with the best chip design; it will be the company that can combine AI, data infrastructure, secure hybrid computing, and autonomous workflows across the entire silicon lifecycle.

Also Read:

Panel Discission: Beyond Moore’s Law and the Future of Semiconductor Manufacturing

GTC 2026: Agentic AI for Semiconductor Design and Manufacturing

Agentic EDA Panel Review Suggests Promise and Near-Term Guidance


CEO Interview with Dr. Albert Liu of Kneron

CEO Interview with Dr. Albert Liu of Kneron
by Daniel Nenni on 07-12-2026 at 6:00 pm

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Dr. Albert Liu is the Founder and CEO of Kneron, a full-stack edge AI company pioneering next-generation Neural Processing Unit (NPU) architectures and localized AI infrastructure.

Widely recognized as a pioneer in NPU architecture, Dr. Liu has spent decades advancing AI hardware, semiconductor systems, and computer vision technologies through leadership roles at Qualcomm, Samsung Electronics R&D Center, MStar, and Wireless Information. He is the holder of multiple foundational patents in AI and semiconductor design and has contributed technologies that have scaled across billions of devices worldwide.

Dr. Liu holds more than 30 international patents, has published over 70 technical papers, and received the prestigious IEEE Darlington Award for his work in reconfigurable AI accelerator architectures. He earned his PhD in Electrical Engineering from UCLA and is the author of “Artificial Intelligence Hardware Design: Challenges and Solutions.”

Today, Dr. Liu is recognized as a leading voice in edge AI and inference infrastructure as the industry shifts from centralized cloud AI toward distributed real-world intelligence.

Tell us about your company?

Founded in 2015, Kneron is an early pioneer of Neural Processing Unit (NPU) architecture and full-stack edge AI computing, built on the belief that inference would become the next foundational layer of AI infrastructure.

As the industry shifts from cloud-centric training toward large-scale real-world AI deployment, Kneron develops scalable edge AI infrastructure designed to enable AI to operate efficiently, privately, and in real time directly where data is generated.

Kneron’s technology is purpose-built for sustained AI inference workloads across enterprise systems, AI PCs, automotive platforms, smart devices, and future intelligent infrastructure where power efficiency, low latency, privacy, and deployment scalability are increasingly critical.

What problems are you solving?

The AI industry is entering a major deployment bottleneck.

Training models is no longer the primary challenge. Enterprises now face the far more difficult task of deploying AI at scale in a way that is energy efficient, secure, cost-effective, and practical to operate.

As AI adoption accelerates, organizations are increasingly concerned about power consumption, cooling requirements, latency, privacy, data sovereignty, and rising infrastructure costs.

Kneron addresses these challenges through localized inference infrastructure designed to run AI directly where data is generated. Our platform enables enterprises to process AI workloads on-device or on-premise with lower latency, stronger data control, and significantly improved deployment efficiency.

We believe the future of AI will extend far beyond hyperscale data centers into factories, hospitals, vehicles, enterprise campuses, and intelligent edge systems worldwide.

What application areas are your strongest?

Kneron’s architecture is strongest in environments where AI must operate continuously, in real time, and close to where data is generated.

Our core strengths are in enterprise edge AI infrastructure, intelligent security systems, automotive AI, and next-generation AI PCs — markets where power efficiency, low latency, privacy, and reliable localized inference are critical.

As enterprises move beyond AI experimentation into large-scale deployment, we believe these real-world inference environments will become one of the most important growth areas in the industry.

What keeps your customers up at night?

The biggest concern we hear today is scalability.

Enterprises are realizing that deploying AI at scale is far more difficult than simply accessing large models. Customers are increasingly concerned about rising inference costs, power and cooling demands, data privacy, infrastructure dependency, and long-term sustainability.

There is also growing recognition that not every AI workload belongs in the cloud. Many organizations want AI systems that can operate locally, securely, and reliably in real-world environments.

This is where edge AI becomes strategically important.

What does the competitive landscape look like and how do you differentiate?

The competitive landscape is evolving rapidly because the industry is shifting from a training-centric AI era toward an inference-centric AI era.

Many companies can build accelerators. Far fewer companies have spent nearly a decade building infrastructure specifically optimized for real-world inference deployment.

Kneron differentiates itself in several key ways:

Inference-First Architecture
Our technology was designed specifically for inference efficiency from the beginning, not adapted later from training-centric architectures.

Full-Stack Ownership
We control the stack across silicon, operating systems, runtimes, orchestration layers, and deployable infrastructure systems. That vertical integration allows us to optimize performance, efficiency, deployment flexibility, and long-term scalability.

Energy Efficiency
Inference happens continuously. Efficiency becomes critical at scale. Our architecture is designed for significantly lower power and cooling requirements compared to traditional AI infrastructure approaches.

Localized & Sovereign AI
We enable enterprises to run AI where their data lives. This is becoming increasingly important for privacy-sensitive industries and sovereign AI initiatives worldwide.

Real-World Deployability
The future AI market will not be won solely by benchmark performance. It will be won by who can deploy AI sustainably, economically, and reliably across real operating environments.

That is the market Kneron is focused on leading.

What new features/technology are you working on?

Kneron is focused on advancing scalable localized AI infrastructure for the next generation of enterprise and consumer AI deployment.

Areas of active development include:

  • Advanced edge AI servers and rack-scale inference systems
  • Agentic AI infrastructure for localized enterprise deployment
  • AI PC companion technologies
  • Real-time multimodal AI systems
  • Distributed inference orchestration
  • Energy-efficient large language model deployment
  • Secure on-device AI systems
  • Next-generation reconfigurable NPU architectures

We are also continuing to expand our software ecosystem to make enterprise AI deployment significantly easier across edge and hybrid environments.

A major focus for us is enabling organizations to deploy powerful AI systems without requiring hyperscale cloud dependency.

How do customers normally engage with your company?

Some organizations begin with a specific edge AI challenge such as privacy-sensitive inference, real-time AI processing, or infrastructure efficiency optimization. Others engage with us while building larger AI transformation roadmaps and looking for alternatives to purely cloud-dependent architectures.

Engagements often start through:

  • Enterprise infrastructure evaluations
  • Proof-of-concept deployments
  • Joint development partnerships
  • OEM and system integration relationships
  • AI PC and intelligent device collaborations
  • Automotive and industrial platform development
  • Channel and ecosystem partnerships

Kneron positions itself as a company helping define what the next generation of AI infrastructure looks like in the real world.

Contact Kneron

Also Read:

Executive Interview with Chris Morrison, VP Product Marketing at Agile Analog

CEO Interview with Brice Cruchon, CEO of Dracula Technologies

Executive Interview with Genta Taniguchi of Kyocera


Executive Interview with Ebrahim Hussain and Aaditya Subediand of Architect Labs

Executive Interview with Ebrahim Hussain and Aaditya Subediand of Architect Labs
by Daniel Nenni on 07-12-2026 at 4:00 pm

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Ebrahim Hussain is Co-Founder of Architect Labs, where he is building AI-powered systems to accelerate semiconductor design and engineering. He brings deep expertise in AI and hardware development, with a focus on transforming how advanced chips are designed and brought to market.

Aaditya (Aadi) Subedi is Co-Founder of Architect Labs, where he is helping develop AI-native tools that streamline chip design and verification. His work centers on applying cutting-edge AI technologies to modernize semiconductor development and accelerate innovation across the compute stack.

Tell us about your company?

Architect Labs is building an AI system that designs and verifies custom chips end-to-end. Our mission is to make world-class silicon design accessible to any organization with a demanding workload, not just the handful of companies that can afford to build large in-house semiconductor teams. We believe the future of computing will be defined by custom hardware, and we’re building the infrastructure to dramatically accelerate how that hardware gets created.

What problems are you solving?

Today, designing a chip is one of the most difficult and resource-intensive engineering efforts in technology. It can take years, cost hundreds of millions of dollars, and requires highly specialized expertise that is increasingly scarce. At the same time, AI, robotics, defense, cloud infrastructure, and other industries are demanding more specialized hardware than ever before.

We’re solving the mismatch between the growing need for custom silicon and the industry’s limited ability to produce it. Our AI system is designed to automate and accelerate major parts of the chip design and verification process, enabling organizations to move from workload requirements to production-ready silicon much faster than traditional approaches allow.

What application areas are your strongest?

We’re focused on workloads where hardware has become a strategic bottleneck. That includes AI training and inference infrastructure, data center systems, networking, robotics, autonomous systems, edge computing, and other compute-intensive applications where performance, efficiency, and cost matter at scale.

More broadly, we’re interested in any domain where custom silicon can unlock meaningful advantages over general-purpose hardware.

What keeps your customers up at night?

Our customers are under pressure to deliver more compute, better performance, lower power consumption, and improved economics—all while operating within increasingly constrained hardware environments.

Many organizations recognize that custom silicon could provide a competitive advantage, but they’re concerned about the risks: lengthy development cycles, enormous upfront investment, talent shortages, and the possibility of spending years on a design that ultimately doesn’t meet expectations. They want a path to custom hardware without having to become semiconductor companies themselves.

What does the competitive landscape look like and how do you differentiate?

There are a number of companies applying AI to portions of the semiconductor workflow, whether that’s verification, EDA tooling, or specific design tasks. Our view is that the opportunity requires a much more comprehensive approach.

We’re building an end-to-end AI system for chip design and verification rather than point solutions that optimize individual steps. Our team combines deep expertise in both frontier AI research and production silicon development, which allows us to rethink the design process from first principles. Ultimately, we want to make custom silicon accessible through a much simpler interface: organizations define the workload they care about, and our system helps generate the hardware optimized for it.

What new features/technology are you working on?

Our current focus is advancing the capabilities of our AI system across the chip development lifecycle, including architecture exploration, design generation, verification, and optimization.

Longer term, we see a future where hardware and software are co-designed together. We’re investing in technologies that connect silicon design with compilers, runtimes, systems software, and eventually AI models themselves, enabling tighter optimization across the entire computing stack.

How do customers normally engage with your company?

Today, we work closely with a select group of partners that have their own chip programs, or are exploring custom solutions that off-the-shelf hardware cannot solve. For companies, with an existing chip program, we co-design silicon alongside them to dramatically accelerate their chip development timelines. For companies exploring custom silicon, the engagements typically begin by understanding the workload, performance requirements, and deployment constraints, then collaborating to evaluate how purpose-built silicon could improve outcomes.

Over time, our goal is to make custom silicon significantly more accessible, allowing many more organizations to leverage specialized hardware without needing a chip design team. This will allow companies to co-evolve their models, and software together with the underlying hardware, accelerating the industry’s path to superintelligence.

Also Read:

CEO Interview with Mark Ren of Agentrys

Executive Interview with Chris Morrison, VP Product Marketing at Agile Analog

CEO Interview with Brice Cruchon, CEO of Dracula Technologies


Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena
by Daniel Nenni on 07-10-2026 at 2:00 pm

Daniel is joined by Sagar Saxena, Senior Product Engineer at Siemens EDA specializing in computational lithography, optical proximity correction (OPC), and advanced patterning solutions for leading-edge semiconductor manufacturing. Sagar has led the development and deployment of advanced OPC technologies, including curvilinear OPC methodologies, computational lithography workflows, and next-generation mask synthesis solutions. His work has contributed to high-volume manufacturing enablement at advanced nodes for some of the world’s most advanced semiconductor processes.

Dan explores the changing world of mask fabrication with Sagar in this informative discussion. Sagar describes the changes underway to move from orthogonal (Manhattan-style) mask layout to a curvilinear format. Sagar explains that curvilinear shapes are more compatible with current high-density manufacturing, but these types of geometries introduce substantial challenges for geometry processing and OPC. These challenges include run time, data size and overall complexity.

Sagar describes a unique approach that Siemens EDA has implemented to address these challenges, opening the way to better yield and performance. He describes the approach, along with descriptions of actual customer usage.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview with Mark Ren of Agentrys

CEO Interview with Mark Ren of Agentrys
by Daniel Nenni on 07-10-2026 at 10:00 am

Mark Ren Agentrys AI

Mark Ren has 26 years of EDA and AI R&D experience spanning IBM Research and NVIDIA Research, driving design automation innovations that power modern chip design. He received the IBM Corporate Award for contributions to the design closure for high-performance microprocessors. At NVIDIA, he helped establish the company as a world leader in AI for chip design and GPU-accelerated EDA. Mark has spearheaded the modern GPU-accelerated EDA movement, driving adoption of deep-learning frameworks to unlock performance and scalability for EDA workloads. He also led the first industrial LLM-for-chip-design effort, ChipNeMo.

His work spans design automation across digital, analog, and PCB, and has been recognized with two DAC Best Paper Awards and 10+ Best Paper Awards /nominations across major EDA conferences. Mark has delivered keynotes for Cadence, Synopsys, TSMC, Intel, and Silicon Labs. He has taught AI-for-chip-design tutorials at DAC and Hot Chips, served as Chair of the LLM Aided Design Conference and is on the steering/organizing committees for ICCAD and ISPD. He is an IEEE Fellow, and his work has been covered by publications such as WIRED, Fortune, and EE Times.

Tell us about your company

Agentrys is an applied research team building the future of chip design. We are pioneering Agentic Design Automation (ADA), a new paradigm for semiconductor engineering. Electronic Design Automation (EDA) has transformed the industry by automating engineering algorithms. Today, frontier AI can automate many engineering tasks by understanding specifications, generating RTL and scripts, creating assertions and testbenches, and assisting with debug.

We believe the next transformation is to automate and continuously improve the engineering workflows that determine product quality, engineering productivity, and time-to-market. This transformation will result in an agentic engineering workflow customized to each design team’s own engineering knowledge and design methodology. We call this Agentic Design Automation (ADA).

Our mission is to help every semiconductor company create its own continuously improving agentic engineering workforce. The Agentrys Studio delivers a platform that enables engineering organizations to build, deploy, evaluate, and continuously improve that workforce, running securely on the company’s existing EDA infrastructure and learning from its own engineering data.

Agentrys includes researchers and engineers from NVIDIA, Meta, AMD, Samsung, Google, Siemens, and other leading technology companies.

What problems are you solving?

Contemporary chip development depends on long-running, complex, repeatedly executed engineering workflows that demand significant manual effort and engineering judgment. Examples include verification closure, physical implementation, timing closure, analog layout optimization, design-space exploration, and signoff.

Even though EDA tools have automated many parts of these workflows, significant engineering effort is still required to achieve high-quality results. For example, debug dominates verification time, floor planning gates physical design, and layout remains difficult for analog circuits.

General AI and commercial agents will increasingly automate many engineering tasks by writing code, generating scripts, answering questions, analyzing logs, debugging, and more. However, solving these complex workflows at expert design quality is still out of reach.

Our goal is to help design teams automate these workflows and keep improving them, eventually surpassing expert-level design capability.

What application areas are your strongest?

Our platform is designed to span the semiconductor development lifecycle, but we are deliberately focused. Our strongest and most proven area today is functional verification — testbench stimulus generation, checker generation, and assertion creation.

On the verification tasks of NVIDIA’s public CVDP (Comprehensive Verilog Design Problems) benchmark, our system reaches roughly 95% on both checker generation and assertion generation, and 90% on testbench stimulus generation. These are measurable, published results on a benchmark our own team helped create.

Next, we are extending into physical implementation and optimization, where we are already in active customer engagements. Our roadmap covers RTL design, analog design, and system design.

Rather than shipping isolated point tools, we deliver Agentrys Studio, giving design teams one platform to build continuously improving capability across multiple engineering domains. This allows a team’s agents to become a compounding, crossflow asset rather than a collection of disconnected tools.

What keeps your customers up at night?

Every semiconductor company is wrestling with the same questions. How do we use AI to improve engineering productivity — safely, and inside our existing flows? How do we protect proprietary engineering knowledge when our designs are our most valuable asset? How do we deploy AI inside secure, often air-gapped, enterprise environments?

And the deepest question: if every competitor adopts similar frontier AI, where does lasting advantage come from? If AI is just another productivity tool everyone buys off the shelf, it raises the floor for the whole industry but gives no one an edge.

Our answer is that the advantage must come from something a team owns — its methodology and its data. So, the agents should be yours. They should learn from your designs, run behind your firewall, and get better with every project. That is the difference between renting capability everyone else can rent and building an asset that compounds for you alone.

What does the competitive landscape look like and how do you differentiate?

The industry is moving rapidly. Frontier-model providers, commercial AI agents, EDA vendors, and startups are all bringing AI into semiconductor engineering. We see that as validation that AI will become a standard component of chip design.

Major EDA companies provide AI capabilities on top of the tools they sell. Some AI-for-chip-design startups focus on building foundation models for chip design. Others focus on domain-specific AI agents, and internal AI teams within design organizations are building their own agents with the help of coding agents such as Codex and Claude Code.

Our view is that the core problem to solve is how effectively an engineering organization builds, deploys, evaluates, and continuously improves the engineering workflows that define its products.

That philosophy drives several architectural decisions.

Agentic Design Automation Platform: We provide Agentrys Studio rather than a fixed collection of vendor-controlled agents. This platform combines frontier models with a self-evolving agent infrastructure, agent-native tools, and customizable AI models and domain knowledge to automate complex design workflows and learn from existing design data.

Customer Ownership: Customers build an agentic engineering workforce that evolves around their own workflows, methodology, engineering knowledge, and design data. We deploy inside the customer’s environment, either on-prem or in a private cloud. The RTL, netlists, PDKs, verification collateral, and engineering knowledge remain under the customer’s control.

Cross-vendor by design: Production engineering workflows span commercial EDA tools and agents from multiple vendors as well as internal tools and infrastructure. We orchestrate across that heterogeneous environment instead of assuming a single tool ecosystem.

What new features or technologies are you working on?

We are expanding Agentrys Studio along several dimensions: enterprise on-premise deployment, workflow orchestration for long-running engineering processes, grounded engineering evaluation, engineering knowledge management, and continuous optimization through our Self-Evolve framework. A major area of innovation is agent-native tooling.

Traditional EDA tools are designed for human engineers. They provide interfaces, controls, and feedback optimized for interactive engineering. AI agents require a different interaction model. These tools need machine-actionable APIs and engineering feedback that enable autonomous reasoning, rapid iteration, and continuous optimization.

Agent-native tooling complements commercial EDA by providing AI agents with the interfaces and feedback needed to solve long-running, complex engineering workflows more effectively. Rather than replacing existing EDA tools, it works alongside them to make AI-driven engineering more capable.

We are also advancing our Self-Evolve framework, which continuously evaluates engineering outcomes against grounded references and customer-defined acceptance criteria. Every workflow execution generates engineering observations that improve agents, workflows, engineering knowledge, and tooling over time.

Our long-term vision is to give every semiconductor company a continuously improving agentic engineering workforce that becomes more capable with every project, while preserving the security, methodologies, and engineering knowledge that make each organization unique.

How do customers normally engage with your company?

Engagements usually follow three steps — we call it Onboard, Evolve, Scale.

The process starts with a technical discussion of the customer’s workflows and AI strategy, where we identify one or two high-value workflows with measurable targets. We then onboard that real flow, integrating with the customer’s existing EDA tools, knowledge, and infrastructure, on-prem. We operate in the customer’s methodology rather than requiring them to re-implement it in ours.

From there, the agents evolve by adapting to how the team designs and become more correct on the team’s own designs with each run, measured against grounded references. As confidence grows, customers scale ADA across additional workflows and engineering teams.

That arc is also our business model. Onboard to land, evolve to earn trust, scale across the organization. Today we are engaged with customers across both front-end design and physical design, from tier-1 semiconductor companies to AI-silicon startups looking to scale small teams with agentic automation.

CONTACT AGENTRYS AI

Also Read:

Executive Interview with Chris Morrison, VP Product Marketing at Agile Analog

CEO Interview with Brice Cruchon, CEO of Dracula Technologies

Executive Interview with Genta Taniguchi of Kyocera


TSMC A16 Backside Power at VLSI 2026

TSMC A16 Backside Power at VLSI 2026
by Daniel Nenni on 07-10-2026 at 6:00 am

TSMC A16 Backside Power at VLSI 2026

TSMC’s A16 technology, presented as Paper T1.5 at the June 2026 IEEE/JSAP VLSI Symposium, marks the company’s first angstrom-class CMOS platform combining enhanced nanosheet gate-all-around transistors with backside power delivery. The key integration feature is Super Power Rail, or SPR, which TSMC describes as a backside direct-contact power delivery scheme targeted at AI and high-performance-computing designs with dense power grids and complex signal routing. Compared with N2P, the VLSI abstract reports 8–10% higher speed at the same power, or 15–20% lower power at the same speed, plus 8–10% chip-density gain, with mass production slated for Q4 2026.

The technical motivation is straightforward: at advanced nodes, frontside metal stacks are increasingly congested. Conventional power rails compete with signal interconnect for routing tracks, and resistive voltage loss, or IR drop, becomes harder to control as supply voltages fall and current density rises. By moving the primary power distribution network to the wafer backside, A16 separates power delivery from frontside signal routing. This releases frontside resources for timing-critical interconnect while creating a lower-resistance path for VDD/VSS delivery. TSMC’s public A16 page states that SPR improves logic density and performance by dedicating frontside routing to signals and significantly reducing IR drop.

A notable part of TSMC’s approach is the backside direct contact architecture. Rather than only placing large backside power metals underneath the device layer, SPR connects backside power more directly into the transistor source/drain region through backside vias and contacts. The VLSI technical tipsheet describes A16-SPR as using backside direct-contact power delivery, front/back-side metals, and 3D MIM capacitors, indicating that the power-delivery system is not merely a routing rearrangement but a full process-integration module.

This matters because backside power can create tradeoffs in cell height, device width, standard-cell architecture, and design-technology co-optimization. TSMC emphasizes that its backside contact scheme preserves N2P gate density and NanoFlex design flexibility, meaning designers can still tune cell layouts for performance, power, and area rather than being locked into a single restrictive cell template. The VLSI session abstract specifically says SPR preserves N2P gate density and NanoFlex DTCO benefits, which is important for real product implementation rather than only test-chip demonstration.

For AI and HPC chips, A16’s benefit is especially relevant. Large accelerators have massive simultaneous switching currents, long global routes, high SRAM/cache content, and strict timing closure requirements. Reducing IR drop improves effective transistor drive because less voltage is lost before reaching active devices. Freeing frontside routing also helps high-utilization logic blocks where congestion can otherwise force longer wires, more buffers, or larger cells. In practice, SPR should improve both electrical efficiency and physical-design closure, particularly for compute tiles, CPU cores, and accelerator fabrics.

Bottom line: A16 represents more than a node shrink. It is a structural change in how power and signals are partitioned across the chip stack. The result is a process positioned between classic two-dimensional scaling and future three-dimensional logic integration: nanosheet devices provide gate control, while backside power attacks interconnect and power-delivery bottlenecks. At VLSI 2026, TSMC’s message was that A16 is already qualified as a platform technology and moving toward production, making backside power delivery a near-term manufacturing feature rather than a distant research concept.

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by Daniel Nenni on 06-03-2026 at 10:00 am


Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm

2025 TSMC Revenue by Platform

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show the HPC platform officially dominating the market, accounting for 58% of total revenue. This macro shift is the primary engine fueling the Interface IP market, which reached a valuation of $2.438 billion in 2025 and is projected to grow at a robust 13.2% CAGR to $4.537 billion by 2030. This growth is anchored by high-speed serial protocols that have become the dominant choice for modern SoC design.

Wired Interface IP Revenues by Protocol, 2021-2030

This visual confirms that the market is no longer just expanding in volume; it is expanding in value as the cost of developing advanced IP skyrockets. For example, a 3nm PCIe 7 PHY solution now commands a license premium between $4.0M and $4.5M, a massive leap from the historical costs of legacy protocols.

The Evolving Vendor Hierarchy

While Synopsys remains the undisputed leader with a 57% market share, the 2025 data reveals interesting structural shifts. Despite its dominance in USB (75.4%), PCIe (63.1%), and MIPI (80.4%), Synopsys saw a marginal revenue drop in 2025 as leading-edge accelerator designs began prioritizing highly customized, bespoke interconnect solutions over standardized blocks to meet stringent AI bandwidth and power requirements.

Cadence has firmly established itself as the primary challenger, growing its market share to 17% with significant gains in the DDR and PCIe sectors. Meanwhile, specialized players like Credo and Rambus continue to carve out niches in high-speed SerDes and security IP, leveraging a “multi-pole” strategy to monetize through both licensing and hardware connectivity products.

The Qualcomm-Alphawave Disruption

Perhaps the most significant competitive event of the past year was the Qualcomm-Alphawave merger, completed in December 2025. This move transforms a high-growth IP challenger into a critical engine for Qualcomm’s broader data center and AI platform strategy. Early indicators from Qualcomm’s leadership suggest they will pursue a “dual-use” model, continuing to license Alphawave’s merchant IP to external customers while leveraging it internally for next-generation custom silicon.

Top 5 Interface IP Revenue, 2026-2030

This “Top 5” view highlights where the real revenue battleground lies: USB, PCIe, DDR, SerDes/D2D, and MIPI. Together, these five protocol families are forecasted to account for $4.356 billion in total value by 2030. Within this group, the Chip-to-Chip (D2D) segment is the fastest-growing outlier, boasting a 23.7% CAGR as chiplet partitioning becomes a first-order architectural decision for hyperscalers.

Strategic Intelligence for a New Era

In an environment defined by rapid protocol refreshes such as the transition from 400G to 1.6T Ethernet and the emergence of UCIe-standardized chiplets, relying on outdated market assumptions is a significant risk. Successful navigators of this $4 billion market require more than high-level trends; they need vendor rankings, license pricing guidance and many other important details that drive real-world procurement and design decisions.

The 18th edition of the “Interface IP Survey” provides the details. Authored by Dr. Eric Esteve, a world-renowned Design IP expert, and Kalar Rajendiran, a veteran semiconductor executive, this latest report synthesizes years of primary research and interviews with more than 45 major IP vendors and foundries.

To purchase, Contact Daniel Nenni: dnenni@semiwiki.com

For industry professionals aiming to secure first-pass success in the 2026–2030 era, the full Interface IP 2025 Survey and 2026-2030 Forecast is the definitive resource for competitive intelligence.

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SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise
by Daniel Nenni on 07-09-2026 at 10:00 am

EDA Industry Primer SemiAnalysis

Electronic Design Automation, or EDA, is the software infrastructure that transforms a hardware specification into a manufacturable integrated circuit. At advanced process nodes, the problem is no longer simply drawing transistors or connecting gates. A modern system-on-chip contains billions of standard cells, hundreds of clock and power domains, dense SRAM macros, high-speed interfaces, embedded analog blocks, and often chiplet or advanced-package integration. EDA tools manage this complexity by converting register-transfer level descriptions into optimized physical layouts while proving that the resulting design satisfies functional, electrical, timing, and manufacturing constraints.

The flow begins with RTL written in Verilog, SystemVerilog, or VHDL. Logic synthesis maps this RTL into a gate-level netlist using a process-specific standard-cell library. The synthesis engine must optimize Boolean logic under timing, area, power, and testability constraints while respecting library characterization across process, voltage, and temperature corners. For high-performance designs, synthesis is not a single pass. Engineers iterate constraints, clock definitions, hierarchy boundaries, retiming options, and physical-awareness settings to reduce critical-path delay before physical implementation.

Physical design then converts the netlist into layout. Floorplanning defines macro placement, power grids, clock topology, voltage islands, and routing resources. Placement engines position millions or billions of instances while minimizing wirelength, congestion, timing violations, and power density. Clock-tree synthesis inserts buffers and balances skew across clock domains. Routing tools assign interconnect across many metal layers while obeying spacing, width, via, electromigration, multi-patterning, and density rules. At leading-edge nodes, routing is constrained by thousands of design rules, and local layout decisions can affect yield, timing, IR drop, and signal integrity simultaneously.

Signoff analysis verifies that the physical implementation is electrically robust. Static timing analysis checks setup and hold closure across many PVT scenarios, extracted parasitics, clock uncertainties, and on-chip variation models. Parasitic extraction calculates resistance, capacitance, and coupling effects from the final routed layout. Power integrity tools evaluate dynamic and static IR drop, electromigration, and local current density. Signal-integrity analysis checks crosstalk-induced delay shifts and noise. These analyses are interdependent: fixing timing can worsen congestion, reducing IR drop can increase area, and changing routing can alter parasitics enough to reopen timing violations.

Functional verification is usually the largest engineering workload. Simulation runs directed and constrained-random tests against RTL and gate-level models. Formal verification proves equivalence between RTL and synthesized netlists, checks protocol properties, and validates unreachable-state assumptions. Coverage tools track exercised states, transitions, assertions, and functional scenarios. For large SoCs, hardware emulation maps the design onto specialized hardware so firmware, drivers, operating systems, and system workloads can run before silicon returns. This is essential for AI accelerators and datacenter processors, where full-stack validation requires interactions among compute arrays, memory controllers, interconnect fabrics, PCIe, CXL, HBM, security engines, and software runtime layers.

Physical verification is the final manufacturing gate. Design rule checking verifies compliance with foundry geometry constraints. Layout-versus-schematic comparison proves that the mask layout implements the intended circuit. Antenna checks, density checks, lithography-aware checks, and reliability checks reduce manufacturing and lifetime-failure risk. The final output is a GDSII or OASIS database delivered to the foundry for mask generation and wafer fabrication.

The engineering lock-in in EDA comes from flow dependency. Tool outputs are not isolated artifacts; each stage feeds constraints, models, reports, and databases into the next. A change in synthesis can alter placement. A placement change can affect routing. Routing changes modify parasitics. Parasitic changes can break timing, power integrity, or signal integrity. Because of this dependency graph, design teams build extensive internal scripts, regression systems, signoff checklists, and debug methodologies around specific toolchains.

Bottom line: The technical value of EDA is therefore not just automation. It is convergent optimization under extreme constraint density. The tools must search enormous design spaces while producing results that are functionally correct, timing-clean, power-compliant, manufacturable, and economically competitive. As process nodes shrink and systems move toward chiplets, advanced packaging, and AI-driven design-space exploration, EDA is becoming an integrated optimization platform spanning RTL, silicon, package, board, thermal, electromagnetic, and system-level verification.

Reference:

EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

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