SemiWiki – Page 2 – The Open Forum for Semiconductor Professionals

June 23, 2026June 22, 2026

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26
by Mike Gianfagna on 06-23-2026 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services

I recently covered what Samtec was doing at DesignCon 26. Samtec has a tendency to dominate any show it attends in multiple dimensions. The prior post focused on the company’s contributions to the technical agenda and the high-profile experts in attendance. While all that is interesting and valuable, attending a large show like DesignCon is also about seeing products in action on the show floor. Samtec was quite active in this area as well, and this post will explore some of that work. Let’s examine how Samtec blazes a trail to 224/448 Gbps at DesignCon 26.

Why 224/448 Data Rates are Important

224/448 Gbps data rates represent lane-rate inflection points. That is, they determine how much bandwidth a system can move per SerDes lane, optical wavelength, connector pin, package escape, cable, or backplane path. This is particularly important for the electrical/optical interconnect level in AI, switch, and multi-die systems. To dig just a bit deeper, here are some of the benefits of getting this technology right:

Enable 1.6T and 3.2T systems without exploding lane count. There are many standards at work that cover chip-to-module, chip-to-chip, die-to-die, and backplane/copper-reach use cases.
Reduce the number of lanes, traces, fibers, connectors, and retimers. Moving from 112G to 224G roughly doubles bandwidth per lane. That can mean fewer SerDes lanes for the same port bandwidth, or twice the port bandwidth with the same number of lanes.
Alleviate the I/O bottleneck in AI and HPC systems. AI training and inference clusters are increasingly limited by moving data between GPUs, memory, switches, NICs, and storage, not just by raw compute.
Reduce power per bit. It is well-known that interconnect power is a major system constraint.

Achieving these data rates is NOT easy as these rates push very close to the limits of the electrical channel. So, there are many choices to consider – copper, flyover cable, LPO, CPO, or optics. As lane rates rise, conventional PCB reach becomes harder and more power-hungry. These are significant areas of focus for Samtec, so what was shown at DesignCon has meaningful impact on future systems. Let’s look at what Samtec showed for 224/448 Gbps at DesignCon.

130 GHz Test Platform

Samtec showed two versions of its new Samtec BE130 Bulls Eye® test point system. The BE130 brings 130 GHz of coaxial test cable bandwidth for boards, packages, and substrates for emerging device characterization. This level of performance is critical to enable evaluation of new 224/448 systems. The test hardware is shown below.

130 GHz Test Platform

Applications for this hardware include characterization for emerging 400 G-class devices and substrate characterization that supports it, high-speed digital testing, AI/ML computing, wafer probing, phased-array antenna systems, and satellite communications, among others.

The Bulls Eye high-performance test assembly featured a high-density space-saving design that enables smaller evaluation boards and shorter trace lengths in test and measurement applications. All this helps to open a path to the advanced, high-speed channels that are so critical for future products.

224/448 Gbps Test Platforms with Keysight

This demo with Keysight illustrates the path to building more comprehensive systems. In this demo, it was shown how Keysight’s new 250 GHz Vector Network Analyzer (VNA) and the previously mentioned Samtec BE130 can be combined to push the limits of channel performance. Details about Keysight’s 250 GHz VNA can be found here.

Keysight explained how digital engineers performing signal integrity analysis want the best time domain resolution between adjacent impedance discontinuities. As designs move to higher frequencies (in the frequency domain), the Keysight VNA provides 150-micron resolution in the time domain. This is especially important when analyzing very small features, such as co-packaged optics, IC package characterization, or BGA packages.

The demo showed that Samtec’s BE130 and Keysight’s 250 GHz VNA were able to reach beyond 130 GHz. So, the combination of Keysight test and measurement capabilities with Samtec’s interconnect technology demonstrated a validated test platform for next-generation testing, especially at 448 Gbps over copper or optics. The demo hardware is shown below.

Keysight-Samtec demo hardware

A 448 Gbps Co-Packaged Copper Channel

For this live demo, Samtec developed a prototype cable system representing a chip-to-chip, intra-tray GPU-to-GPU interconnect running at 448 Gbps. A Keysight VNA (N5295AX03) measured the loss up to 125 GHz in the next-generation prototype Samtec Si-Fly® HD co-packaged copper system, or CPC. Information about the Keysight VNA can be found here.

As we follow the signal path for this demo, the 448 Gbps signal passes through a Samtec Nitrowave® LL130 premium RF metrology cable, to 1 mm compression-mount precision RF connectors, and into the PCB routing of 13 mm. It then routed through the Si-FLY HD 448 Gbps connector systems that are linked by 400 mm of Samtec EyeSpeed® Hyper Low Skew cables, and back to the VNA for analysis.

The photo of this unique demo is shown at the top of this post. The 400 mm EyeSpeed Hyper Low Skew cables are shown in blue on the left of the photo.

To Learn More

Samtec provided several live demonstrations at DesignCon 26 that brought 224/448 channel performance closer to reality. Seeing the goal posts move is one of the reasons we all attend trade shows, and Samtec did not disappoint.

You can learn more about the Samtec technologies mentioned here:

And you can always reach out to the Samtec RF Group here. And that’s how Samtec blazes a trail to 224/448 Gbps at DesignCon 26.

Also Read:

Samtec’s Strong Presence at embedded world 2026

Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026

2026 Outlook with Mathew Burns of Samtec

June 22, 2026June 22, 2026

Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs

Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs
by Boris Shteinberg on 06-22-2026 at 2:00 pm
Categories: Foundries
3 Comments

A deposition chamber drops out of production at 2 a.m. Forty minutes later it is back, the dashboard flips from red to green, and two people want opposite things. The operations-center operator has a step starving downstream and wants the tool dispatched now. The module’s shift group leader wants test wafers run and confirmed on target before a single product lot goes near it. Both are right. Someone has to choose in the next few minutes, on partial data, with a clock running.

That small standoff is the real work of high-volume manufacturing, and it repeats across a fab every shift. It turns on a distinction the dashboard hides. Available is the door being open. In control is whether it is safe to walk through: whether you can trust the tool to do to the next thousand wafers what it did to the last, stable and predictable, within a risk you have actually accepted rather than merely hoped for. A green board is a hypothesis, not a guarantee.

Every fab runs on two clocks. One counts output now: availability, utilization, throughput, the commit for the shift. It is carried by ROC operators, shift supervisors, shift managers, and the manufacturing engineers keeping product moving. The other counts consequences later: process stability, equipment health, quality. That clock belongs to the module and process engineering teams, the shift group leaders, the engineering group leaders, who know that a tool released too soon, or a PM deferred to make a number, can send a quiet excursion downstream, one you do not catch until two hundred wafers have already passed through it.

Neither clock is wrong. That is the point. The tension is not dysfunction; it is the system working as designed. Output and control are meant to compete, because a fab that served only one of them would quickly fail at the other.

It helps to be precise about what the green light actually claims. SEMI E10 gives the industry a shared vocabulary for equipment states: productive, standby, engineering, scheduled and unscheduled downtime, non-scheduled time, and from those states the metrics every fab lives by: availability, utilization, mean time between failures, mean time to repair. The vocabulary is exact, and that exactness is what exposes the gap. A tool counted as available may be genuinely productive or merely idle in standby. A tool pushed toward higher utilization buys throughput today at the cost of cycle time and flexibility tomorrow, because a line run too close to saturation amplifies its own variability. The states tell you what a tool is doing and how often it does it. They do not tell you whether to trust it with your next lot right now, and they do not tell you whether the number you are optimizing is the one that matters tonight.

That is why the same standoff takes so many shapes. A PM comes due, and taking the tool down costs output today while deferring it risks a bigger failure tomorrow. A chamber runs at the edge of spec under a green light, and the supervisor who owns tonight’s number is not the engineer who will own the excursion. A tool comes back at partial capability, and someone has to decide whether half a tool now beats a whole tool in three hours. None of these has a clean answer in a procedure. Each is a bet placed with incomplete information, and the standard that names the states cannot place the bet for you.

That call lives in people: the engineer who knows this chamber’s tells, the operator who has seen this signature before, the group leader who decides which risk the shift will carry. It is built from pattern memory and hard-won feel as much as from data, and much of it is invisible. No one is credited for the excursion they prevented or the downtime they avoided by holding a tool one hour longer. The save never shows up on the wall of screens, which means the people best at this are often the hardest to see, and the easiest to lose when they leave.

This is also the part that does not automate away. We can predict tool health, optimize dispatch, and model utilization better every year, and we should; the floor needs every bit of that signal. But software can recommend; it cannot own the consequence. The decision still belongs to people, and it is rarely one person’s to make alone: the operator, the supervisor, the group leader, and the engineer each hold a piece of the picture, and a good call is usually the one they reach together. So the real edge is not a sharper metric or a smarter system. It is people who can weigh availability, quality, equipment health, and risk in a single judgment, made in cooperation rather than in defense of their own number. Output and control were never meant to be enemies; they are two halves of the same call. The fabs that win the next decade will be the ones whose people can hold that balance.

Boris Shteinberg has spent over a decade in high-volume semiconductor manufacturing, across equipment integration, floor operations, and real-time production decisions.

Also Read:

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes

Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026

The Memory Sector Is Becoming One of the Main Beneficiaries of the AI Boom

June 22, 2026June 22, 2026

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk
by Daniel Nenni on 06-22-2026 at 10:00 am
Categories: Aion Silicon, IP, RISC-V, Semiconductor Services

Architecting Smarter SoCs with RISC-V: From Requirements to Silicon Success

As semiconductor complexity accelerates across AI, automotive, and edge computing markets, SoC architecture has become a critical determinant of commercial success. Modern silicon programs must simultaneously achieve aggressive performance-per-watt targets, support evolving workloads, and maintain manageable development risk. The emergence of RISC-V as an open and extensible instruction set architecture (ISA) is reshaping how design teams approach these challenges.

Traditional SoC development often treated architecture as an early planning stage before RTL implementation. Today, that approach is no longer sufficient. Advanced process nodes dramatically increase tape-out costs, making architectural mistakes extraordinarily expensive. According to Aion Silicon’s recent white paper on RISC-V system design, even a prototype tape-out on advanced nodes can approach the cost of full production masks, meaning a single re-spin may result in multi-million-dollar losses and missed market windows.

Effective SoC architecture begins with rigorous requirement analysis. Teams must define measurable KPIs covering throughput, latency, power consumption, safety compliance, software ecosystem compatibility, and interface bandwidths before selecting compute resources. These constraints directly influence architectural feasibility and downstream verification complexity.

Modern heterogeneous SoCs increasingly combine multiple compute engines optimized for different workloads. Scalar CPUs continue to provide operating system control and sequential execution, while DSPs handle low-latency streaming workloads such as radar and sensor fusion. Vector processors accelerate SIMD operations common in image processing and AI inference, and GPUs provide massively parallel throughput for machine learning and graphics applications.

The challenge is not simply integrating these compute engines, but balancing them efficiently within a scalable architecture framework. Aion Silicon describes a layered architecture model consisting of compute subsystems, fabric and chassis infrastructure, custom accelerators, and dedicated safety/security subsystems. This modular approach allows engineering teams to optimize performance without unnecessarily increasing verification complexity or power consumption.

Memory architecture and interconnect design have become equally important. AI and edge inference workloads are increasingly constrained by memory bandwidth and data movement efficiency rather than raw compute capability. Cache hierarchy sizing, arbitration policies, and on-chip memory allocation significantly influence achievable throughput and energy efficiency. Small architectural decisions in these areas often create large downstream consequences in thermal performance and silicon area utilization.

To reduce risk, advanced SoC programs now rely heavily on cycle-accurate modeling prior to RTL development. SystemC-based architectural simulation enables engineers to evaluate realistic workload traffic, identify contention bottlenecks, and validate performance assumptions while changes remain inexpensive. This modeling phase transforms architecture from a theoretical exercise into a measurable engineering discipline.

For AI workloads, the modeling process becomes even more critical. Neural network execution generates highly dynamic memory traffic patterns that are difficult to predict using spreadsheets or static analysis alone. Aion Silicon’s methodology models full DNN graphs directly in SystemC, generating traffic profiles, node reordering recommendations, and fusion analysis before implementation begins. This enables architects to quantify the impact of design changes on KPIs such as latency, throughput, and power efficiency before committing to RTL.

RISC-V introduces additional opportunities and challenges within this environment. Its open ISA allows designers to create application-specific extensions tailored to unique workloads. Properly implemented, custom instructions can significantly improve workload efficiency while reducing power and silicon area. However, uncontrolled customization can also increase software complexity, verification overhead, and ecosystem fragmentation.

Disciplined customization is therefore essential. Successful RISC-V programs align processor extensions with clearly defined workload requirements and validate them through simulation and modeling early in the architecture phase. Even relatively modest changes, such as selecting 32-bit floating-point precision instead of 64-bit implementations, can deliver substantial reductions in area and energy consumption when analyzed systematically.

Collaboration across the semiconductor ecosystem has also become increasingly important. Successful SoC programs depend not only on architecture quality, but also on alignment between IP vendors, EDA providers, foundries, software toolchains, and verification teams. Early engagement with processor IP suppliers and modeling partners helps reduce integration delays and prevents late-stage schedule disruptions.

DOWNLOAD WHITEPAPER HERE

Bottom line: The transition toward heterogeneous compute and customizable architectures is transforming SoC development into a highly data-driven discipline. Architecture is no longer simply a specification document; it is an iterative optimization process grounded in workload analysis, simulation, and ecosystem coordination. Organizations that model early, validate continuously, and customize with purpose will be best positioned to achieve right-first-silicon success in increasingly competitive semiconductor markets.

Also Read:

RISC-V: From Niche Architecture to Strategic Foundation

NoC Matters: Designing the Backbone of Next-Gen AI SoCs

The 10 Practical Steps to Model and Design a Complex SoC: Insights from Aion Silicon

June 22, 2026June 22, 2026

AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoption

AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoption
by raghu shankar on 06-22-2026 at 6:00 am
Categories: 3D IC, Chiplet, EDA

2026 Jun AI Native Virtual Chiplet ecosystem Shift Left Shift Up Shift Out

Systems-in-package (SIPs) with 2.5D and 3D heterogenous integration, consisting of multiple dies and chiplets deliver 10x more functionality than traditional monolithic chips. This capability enables innovative solutions for diverse needs in scientific computing, automotive, edge computing, and aerospace/defense.

Chiplets deliver modular building blocks with smaller dies at higher yields thereby lowering costs. It also enables higher reusability across product lines and across generations. This approach has been adopted by established vendors, on proven legacy designs, in well-understood markets, and in closed eco-systems of few vendors. Beyond that, dies and chiplets can be available from wide range of organizations and generations. Many technologies and standards are in place to speed interoperability and adoption in multi-vendor eco-systems.

Despite the advantages of SIPs and chiplets, broad adoption across a wider range of market opportunities with lower volumes and at lower budgets remains a major challenge. There is a bottleneck right up-front during planning and design phase to identify promising ventures.

First, the market need must be clearly defined, including the value proposition, solution adoption potential, price sensitivity, and demand profile.
Second, each vendor across the supply chain must be confident that their investment will be profitable at level of manageable risk. Further each vendor wants to expand their pool of options to maximize their investments across multiple products, multiple buyers, and multiple generations.

Systematically evaluating the best combinations of design options on both technical merits and business case perspectives from a large pool of IP options improves profitability and spreads risk.

This is a 3-part problem to solve:

Articulate value proposition to adopters on how the new solution is far superior to the prior ones factoring in the migration effort and risk.
Estimate demand, i.e., market size, that is sizeable for supply side investments.
Each vendor on the supply side needs to prove its profitability and prioritize with other competing investments.

The above needs to be solved in a low-risk, low cost, and low-friction manner for any one market opportunity. The evaluation methodology and its outcomes need to be generally agreed upon by the diverse stakeholders including potential adopters. Further this evaluation needs to be scaled to 1000’s of opportunities from which a handful will make the cut for further investigation and investment. To solve this front-end bottleneck, we need to reduce friction and lower barriers for multi-organization explorations.

This requires a shift-left: Shift multi-vendor evaluations as early as possible to the front-end of the design cycle. This is the planning phase, design space exploration, architecture design and power-performance, area and cost (PPAC) estimation phase for further investments.

This requires a shift-up: Scope it down to architecture layer for faster interoperability testing. Abstract up the architecture implications of the lower three layers (physical, adapter/link, and protocol). Starting at the architectural layer (pre-RTL) speeds up evaluations. It allows exploring many configurations that can be synthesized (via HLS) for PPAC estimates. Simulation, emulation, and prototyping may be used for higher confidence estimates.

This requires a shift-out: Break out of industry silos, expand the pool of buyers and sellers, expand the pool of IP for explorations. Maximize finding (or co-developing) the best fit in terms of PPAC for the solution.

Lastly, today a lot of time is spent on repetitive and mundane activities of searching for vendors, IP, specs, tools alignment, benchmarks and test selection, PPA compatibility, etc. before the first interoperability evaluations can be started.

As an industry we need to define a robust, AI native multi-vendor virtual chiplet eco-system for planning and prototyping phases. With security, governance, and safeguards in place, this virtual eco-system will include specs, proven behavioral models, curated stimuli, reference designs, interop verification methodologies, and interoperability results.

AI Native: Many aspects of AI available today and in the future must be applied extensively to exponentially increase early-stage explorations while reducing mundane and repetitive activities. AI native includes semantic and keyword search of specs, rank ordering and scoring top matches, highlighting gaps, code generation, connections to EDA tools, test benches, and benchmarks.

Incorporate best practices including encrypted models, containerized models, fast models, fixed virtual platforms, cloud, IP libraries, local and remote verification IP, STCO, and scenario-based modeling.

Humans will set the objectives and level of interop validation required with AI automating the process flows for the design space explorations via simulations, emulation, and prototyping.

Leaders shaping the vision

The industry needs to deliver on the advances of system in packages, heterogenous integration to solve many high impact needs in scientific computing, automotive, defense and more. They can be better addressed through multi-vendor, heterogenous solutions, mixing new IP and existing designs, lower power, cost, and maximizing memory utilization (valuable commodity now).

The leaders in the industry need to start the dialog today to shape this vision, call out the challenges, and overcome hurdles for this multi-year journey.

Open chiplet economy (OCE) under Open Compute Project (OCP) is a vendor-neutral body encouraging participation from commercial, research labs, and academia who benefit from this initiative. OCP/OCE amplifies this effort through summits, newsletters, webinars, and more to build more visibility for this vision.

More on how to shape the vision, visit https://www.opencompute.org/community/open-chiplet-economy/open-framework-for-chiplet-eco-system-virtual-prototyping

By Raghu Shankar | LinkedIn, June 2026

Also Read:

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox, Daniel Nenni, Editor SemiWiki, May 2026

Synopsys and Samsung Foundry Extend AI-Driven Design Collaboration for Advanced 2nm and Multi-Die Systems

Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools

June 21, 2026June 22, 2026

CEO Interview with Mark Goranson of EMASS

CEO Interview with Mark Goranson of EMASS
by Daniel Nenni on 06-21-2026 at 4:00 pm
Categories: CEO Interviews

Mark Goranson is the Chief Executive Officer EMASS, a wholly owned subsidiary of Nanoveu, for which they serve as the semiconductor technology division. With more than 45 years in the global semiconductor industry, he has held senior leadership roles at companies including Intel, Freescale Semiconductor, and ON Semiconductor. He specialises in wafer fabrication, assembly, testing, and large-scale manufacturing and is responsible for driving EMASS’s commercialisation of ultra-low-power edge-AI system-on-chip solutions. He joined following EMASS’s acquisition by Nanoveu, where his expertise in scaling and strategic alliances is helping accelerate time-to-market for the company’s next-generation SoC offerings.

Tell us about your company?

EMASS is building the next generation of ultra-low-power Edge AI semiconductors. Our mission is to enable intelligent devices to continuously sense, understand, and respond to their environments without relying on the cloud and without sacrificing battery life. Through our ECS-DoT platform, we bring real-time AI directly onto wearables, drones, industrial systems, smart infrastructure, and other battery-powered devices. We believe the future of AI is not only in data centers—it is at the edge, where decisions need to be made instantly, privately, and efficiently. This shift toward always-on intelligence is driving the next wave of innovation, and EMASS is focused on enabling that transition.

What problems are you solving?

Battery-powered edge devices must continuously input sensor data and respond in real time within extremely limited power budgets. Many conventional edge processors process most if not all inputs, whether meaningful or not. They also rely on duty-cycled operation, external memory, or cloud connectivity to handle AI workloads, which can increase latency, consume more power, create security and privacy concerns, and reduce battery life.

EMASS developed ECS-DoT to enable always-on, real-time AI inference directly on-device while maintaining ultra-low power consumption and low latency. Its event-driven system-on-chip architecture keeps devices in an ultra-low-power state until meaningful sensor activity is detected, reducing unnecessary computation and energy use. By processing AI models and sensor data entirely on-chip, ECS-DoT removes the need for continuous cloud-based inference or frequent external memory access. This enables reliable, real-time decision-making for applications like voice detection, motion sensing, condition monitoring, and autonomous response, while extending battery life and reducing system complexity.

What application areas are your strongest?

EMASS’s ECS-DoT delivers the greatest value in battery-powered systems requiring continuous sensing and real-time intelligence within strict energy constraints. In wearables like smart glasses, hearables, and fitness trackers, ECS-DoT enables ultra-low-power, always-on processing for private voice interfaces, gesture detection, and biometric monitoring. One use case uses bone-conduction sensing through an IMU to support keyword spotting without continuously active microphones, improving power efficiency and privacy. Battery-powered drones and robotics also benefit from real-time onboard AI inference within a sub-milliwatt power envelope. In validation trials, this ultra-efficient processing improved operational endurance, making the technology well suited for industrial inspection, agriculture, surveying, and public safety. In industrial IoT and smart infrastructure, ECS-DoT processes sensor data locally to detect anomalies, monitor equipment conditions, and support event-driven wireless communication. Transmitting only meaningful events reduces bandwidth requirements, extends battery life, and enables scalable monitoring of remote infrastructure.

What keeps your customers up at night?

Battery life. For someone building a medical wearable, battery life can be critical – that battery should last as long as possible before it has to be replaced. Or maybe you can design with a smaller, lighter, less obtrusive battery for the next generation of product and still get the same amount of battery life. For someone building autonomous or semi-autonomous systems, such as drones, battery life might be less an issue of replacing the battery and more about utilization rates – the less time a unit spends recharging is that much more time it’s being used for its purpose. And here’s a brand new consideration: until now, AI has been used in power-constrained devices to evaluate what the device’s sensors are detecting. We can make that more efficient, but with our system we’re also making it practical to use AI for the operation of the device itself. Using a drone as an example, you can use AI to significantly improve flight dynamics. What keeps everyone up at night? “How can I compete better?” We can help in more than one way.

What does the competitive landscape look like and how do you differentiate?

The edge AI market is crowded with solutions designed for smartphones, cameras, and devices with relatively large batteries and power budgets. Many processors can run AI, but very few can do so continuously within a sub-milliwatt power envelope.

EMASS was designed specifically for always-on intelligence. ECS-DoT combines event-driven sensing, integrated memory, dedicated AI acceleration, and ultra-low-power operation to deliver real-time inference while consuming a fraction of the energy required by conventional approaches. In many applications, this allows customers to deploy AI capabilities that would otherwise be impractical because of battery life, thermal constraints, size limitations, or privacy concerns.

Our focus is not simply making AI faster—it is making AI continuously available in devices where every milliwatt matters. That is a fundamentally different design objective than most competing solutions.

What new features/technology are you working on?

Three tracks. On silicon, we’re scaling power and performance on more advanced process nodes and extending the always-on architecture across richer multi-modal workloads — vision, audio, and motion together. On software, we’re putting real investment into the developer experience: an expanding model zoo of ready-to-deploy models, a toolkit and IDE that shorten the path from a customer’s data to a model running on the chip, and broader framework support so teams can bring their own models easily. Third, we’re deepening partnerships across sensor makers, distributors, and toolchain partners, so ECS-DoT drops cleanly into real designs. The common thread is making always-on edge AI not just possible, but genuinely easy to adopt.

How do customers normally engage with your company?

Almost always through an evaluation first. We get a developer kit into the customer’s hands so they can run ECS-DoT in their own environment, benchmark the power against their target, and start integrating with our SDK. From there, the serious opportunities move into a design-in phase — a proof-of-concept or reference design built around their use case, then integration, design review, and commercial terms. We support that with reference designs across our core verticals and with field engineers plus a global network of distributors and reps. We also work shoulder-to-shoulder with sensor partners and device makers during integration. My goal is that the chip shows up as part of a working system — not a part the customer has to go figure out on their own.

Also Read:

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Q&A Interview with Mo Steinman, Lightelligence’s Senior Vice President and General Manager, U.S.

June 21, 2026June 22, 2026

CEO Interview with James Regan of Oriole

CEO Interview with James Regan of Oriole
by Daniel Nenni on 06-21-2026 at 2:00 pm
Categories: CEO Interviews
1 Comment

James Regan is a seasoned technology executive and physicist with over 30 years in optical communications. As Co-Founder and CEO of Oriole, he is pioneering the next radical breakthrough in advanced optical networking systems for AI. James has a proven track record of transforming university research into globally impactful companies. He is a frequent contributor to discussions on climate-conscious innovation, deep-tech commercialization, and the intersection of AI and photonics.

Tell us about your company.

We are building the next generation of data center networking, something fundamentally different from what’s come before. Oriole was founded out of University College London on the back of more than 20 years of research into optical networking, but what really defines us is the way we approached the problem.

Instead of starting with a piece of technology and looking for somewhere to apply it, we started with one of the biggest problems in the world right now – how do you scale AI? And we worked backwards from there.

That led us to a completely new kind of network: a pure photonic network that keeps data as light as it moves through the data center. It’s a full-stack system. We are not building a component; we are building the whole network. The goal is very simple: deliver dramatically higher performance, at dramatically lower power, so that AI can scale without hitting physical or economic limits.

What problems are you solving?

The core problem is that AI is running into the limits of existing infrastructure.

Today, if you want more performance, the industry response is essentially to just add more. More GPUs, more switches, more energy. But that only takes you so far. At some point, you run into very real constraints around power, cost, and complexity.

What’s happening is that the network is becoming the bottleneck. Electrical switching architectures simply can’t keep up with the scale and speed that modern AI demands.

That has very direct consequences, particularly for inference, which is where customers make money. As models scale, inference increasingly becomes latency-bound. The network sits on the critical path of how fast processors can work together, and if you introduce delay, you slow the whole system down.

The key point is this:
tokens per second, and tokens per second per user, are directly tied to revenue.

If your network is introducing latency, your GPUs are waiting. And when your GPUs are waiting, your throughput drops, immediately hitting your bottom line.

This isn’t just a technical problem; it’s an economic one.

What Oriole has done is reimagine the network from first principles and built a system where data moves as light, directly between processors, with extremely low and deterministic latency.

The result is that you can:

drive significantly higher tokens per second
deliver better tokens per second per user
and ultimately generate more value from the same compute infrastructure

In simple terms, we’re solving the problem of how to move massive amounts of data at very low, deterministic latency, without consuming unsustainable amounts of power. And how to build a network that can keep up with AI and actually unlock the performance of the compute you’ve already paid for.

What application areas are your strongest?

Our primary focus is large-scale AI infrastructure, both training and inference.

That’s where the problem is most acute, and where the benefits of what we’re doing are most significant. When you’re running large models, you’re constantly moving data between processors, and the efficiency of that communication directly impacts performance.

If you improve that network, you don’t just make things marginally better. You fundamentally change what’s possible. You can train larger models, run inference more efficiently, and ultimately deliver better outcomes per unit of compute.

Beyond hyperscale AI, we’re also seeing strong interest from enterprises and areas like financial services, where performance and latency really matter. But the common theme is always the same: environments where data movement is the limiting factor.

What keeps your customers up at night?

Two things, really: scale and efficiency.

On the one hand, everyone is trying to build bigger and more powerful AI systems, but there is a growing recognition that the current approach doesn’t scale indefinitely. At some point, you simply can’t keep adding more hardware and more power.

On the other hand, there’s a very real concern around the economics of AI. If the cost per token or per workload becomes too high, it limits what you can do.

Underpinning both of those is the network. If the network introduces latency, inefficiency, or overhead, it directly impacts performance and cost.

So, what keeps people up at night is:

Can we scale this?
Can we afford to scale this?
And will the infrastructure keep up with the ambition?

What does the competitive landscape look like and how do you differentiate?

There is a lot of activity in this space, but most of it is incremental. The industry is trying to evolve the current model. That means faster electrical switches, better optical links between those switches, or hybrid approaches that combine scale-up and scale-out networks. But those approaches still rely on the same underlying architecture, and that architecture has fundamental limits.

What Oriole has done is step outside that model entirely. We’ve built what we believe is the world’s first pure photonic AI network, where:

data stays as light end-to-end
every node connects directly to every other node
the network operates in a single-hop, fully connected, contention-free topology

There are no layers of switching, no queuing, no waiting.

The differentiation isn’t incremental. It’s architectural. Others are optimizing the existing system. We’re removing the constraints of that system entirely and building the system that comes after it.

What new features/technology are you working on?

At the core, we’ve built PRISM (Photonic Routing Infrastructure for Scalable Models), the first and that’s already up and running today and we are now taking it into real-world deployments and scaling it (as per our most recent announcement).

In March this year, we announced the next evolution of our platform, which we call PRISM Ultra, which takes the same fundamental concept – light in, light out – but pushes it closer to the processor and dramatically increases scale and performance.

This means:

direct processor connectivity
one-hop communication across very large systems
and extremely low, deterministic latency

At the same time, we’re continuing to innovate across the full stack, from software and control through to photonic hardware, because this only works if you solve the entire system end-to-end. What’s exciting is that once you introduce a fundamentally new technology like this, the pace of innovation accelerates very quickly.

How do customers normally engage with your company?

It typically starts with conversations. Because what we’re doing is quite different, people need to get their heads around it.

There’s often an initial reaction of excitement combined with scepticism, which is perfectly natural when you introduce something that challenges existing assumptions.

There are currently two engagement models, depending on the product and the customer.

For PRISM, it’s more of a transactional model, working with data centre builders, partners, and integrators to deploy systems.

For PRISM Ultra, it’s much more strategic and partnership-led, engaging directly with hyperscalers and leading-edge organisations who are building the next generation of AI infrastructure.

There’s a process of building confidence, what I’d describe as a “staircase”, where we go from demonstrating the technology to scaling it, and then to full production deployments.

Ultimately, because this is a full system solution, engagement is quite deep. We are not just dropping in a component; we’re working with customers on how to rethink their infrastructure for the next era of AI.

Also Read:

CEO Inte rview with Suresh Vasudevan of Clockwork.io

Q&A Interview with Mo Steinman, Lightelligence’s Senior Vice President and General Manager, U.S.

CEO Interview with Mike Horton CEO of HYFIX

Podcast EP351: A Detailed Overview of the Emerging Standards for 400G with Kent Lusted

Podcast EP351: A Detailed Overview of the Emerging Standards for 400G with Kent Lusted
by Daniel Nenni on 06-19-2026 at 10:00 am

Daniel is joined by Kent Lusted, a Distinguished Architect at Synopsys and an integral part of the company’s Ethernet IP design team. He has been an active contributor and member of the IEEE 802.3 Ethernet PHY standards development leadership team for more than 15 years. Prior to Synopsys, Kent worked at Intel for 30+ years, focused on designing Ethernet board products and performing Ethernet interop debug all over the world. Kent is currently the electrical track chair for the IEEE P802.3dj Task Force and Chair of the IEEE 802.3 400Gb signaling study group.

In this very informative discussion, Kent and Dan explore the emerging standards work that will enable 400G communications. Kent describes in detail the various stages that standards development go through to get from early specs and requirements to the robust details that facilitate successful production deployment. The 400G standards effort is in its very early stages. Kent explains that the prior 200G standards work is still not complete, so the 400G effort is indeed in its early stages.

That said, he points out that 400G speeds will be critical for the requirements of emerging scale-up and scale-out AI workloads. Kent describes the meaningful work design teams can engage in now to ensure a smoother path to implementation later. There is a lot of very useful information conveyed regarding how to build advanced systems, how to engage with and leverage standards efforts and how to use Synopsys’s substantial resources to move designs forward.

Synopsys Ethernet IP

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

June 19, 2026June 22, 2026

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes
by Daniel Nenni on 06-19-2026 at 6:00 am
Categories: Analytics, EDA, Foundries, Intel Foundry, PDF Solutions
1 Comment

One of the most difficult things to do in life is ask for help. This is inherently a big problem in the semiconductor industry dating back to the IDM days where silos of secrecy were established. As a result Intel has struggled with yield since the 14nm FinFET process nodes.

On the outside PDF Solutions is a publicly traded semiconductor analytics and manufacturing software company (NASDAQ: PDFS) headquartered in Santa Clara, California. The company helps chipmakers improve manufacturing yield, quality, reliability, and profitability by collecting and analyzing data from semiconductor fabrication, testing, assembly, and field operations.

On the inside PDF Solutions is the #1 yield expert working with the top semiconductor manufacturers in the world. 18 out of the top 20 semiconductor companies have worked with PDF. Founded in 1991 by John K. Kibarian and Kimon W. Michaels, the company was created to address semiconductor manufacturing yield and process-control challenges using data analytics, software, and engineering solutions.

In July of 2025, Intel and PDF Solutions announced a collaboration that redefines advanced semiconductor manufacturing. Lip-Bu Tan and John Kibarian shared a stage and clearly have an active executive-level business relationship through Intel Foundry and PDF Solutions. Given their long careers in the EDA and the semiconductor industry, they most certainly have known each other professionally for some time. From what I hear inside the ecosystem that relationship is quite close with both CEOs managing the projects directly.

Intel CEO Lip-Bu Tan has emphasized the importance of improving manufacturing execution and operational discipline as Intel works to strengthen its foundry business. Yield improvement sits at the center of that effort. While equipment suppliers, EDA vendors, and process technology teams all contribute to manufacturing success, data analytics providers such as PDF Solutions have become increasingly important partners in enabling advanced-node production.

Intel’s success with its 18A/P process technology has become one of the semiconductor industry’s most closely watched stories. After years of manufacturing challenges, Intel has made significant progress toward restoring confidence in its technology roadmap and foundry ambitions. A key element of that success is yield improvement, an area where Intel has increasingly collaborated with ecosystem partners such as PDF Solutions.

Yield learning has become exponentially more difficult at advanced process nodes. Technologies such as RibbonFET gate-all-around transistors and PowerVia backside power delivery, both introduced with Intel 18A, create new process integration challenges and dramatically increase the amount of manufacturing data generated throughout wafer fabrication. Traditional statistical process control methods are no longer sufficient to identify the subtle interactions that can impact yield at these levels of complexity.

This is where PDF Solutions plays a strategic role. The company has spent decades developing yield management, process control, and manufacturing analytics technologies used throughout the semiconductor industry. Its Exensio platform combines data from equipment, metrology, inspection, test, and design sources into a unified analytics environment capable of identifying yield limiters and accelerating root-cause analysis.

For Intel 18A-P, yield learning is particularly critical because the node serves multiple strategic objectives simultaneously. It is expected to support Intel’s own products while also serving as a cornerstone technology for Intel Foundry customers. Achieving competitive yields is essential not only for cost reduction but also for demonstrating foundry credibility. Customers evaluating Intel Foundry require confidence that manufacturing processes can deliver predictable performance, quality, and volume production.

PDF Solutions’ analytics capabilities help address this challenge by enabling faster identification of defect patterns, process excursions, and systematic yield loss mechanisms. Modern fabs generate enormous volumes of data from thousands of process steps, and extracting actionable insights requires sophisticated software infrastructure. By leveraging advanced analytics and AI-driven methodologies, Intel can potentially shorten learning cycles and accelerate yield ramp timelines.

Why this Matters

The collaboration becomes even more important when considering Intel’s roadmap beyond 18A-P. Intel 14A is expected to introduce additional technology innovations and greater process complexity. Every new node increases the number of variables that must be monitored and optimized. As transistor dimensions shrink and manufacturing tolerances tighten, small variations can have significant impacts on yield and performance.

For 14A, data-driven yield optimization will likely become a foundational requirement rather than a competitive advantage. The combination of advanced process technologies, heterogeneous integration, advanced packaging, and increasingly complex customer designs will require a comprehensive approach to manufacturing analytics. Companies that can transform vast amounts of production data into actionable insights will be better positioned to achieve rapid yield ramps and maintain profitability.

Bottom line: As Intel moves from 18A-P into the 14A era, the partnership with PDF Solutions reflects a broader industry trend: semiconductor leadership is no longer determined solely by transistor innovation. Success increasingly depends on the ability to collect, analyze, and act upon manufacturing data at unprecedented scale. In that environment, yield management platforms and AI-driven analytics are becoming as critical to competitive advantage as the process technologies themselves.

Also Read:

Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026

Re-Spins Get You Fired, Says Intel CEO Lip-Bu Tan

ASML High-NA EUV is Not Ready for High-Volume Production

June 18, 2026June 25, 2026

Webinar: Faster Design Spec to Implementation using IP-XACT

Webinar: Faster Design Spec to Implementation using IP-XACT
by Daniel Payne on 06-18-2026 at 10:00 am
Categories: Defacto Technologies, EDA, Events

As SoC design flows grow increasingly complex, IP-XACT has become a cornerstone standard throughout the entire development lifecycle: from architecture specification to design assembly and verification. Its growing adoption is reflected in the standard’s continuous evolution, from the 2009 release through 2014 and now to the 2022 revision, and whether driven by internal methodology choices or imposed by customers and providers, IP-XACT is now a reality.

See Replay Here

In practice, IP-XACT comes with significant challenges. First, the format is inherently complex: its XML-based structure is not human-readable, objects carry dense interdependencies, and different organizations often develop their own “flavors” of the standard, creating interoperability friction. Second, and more critically, IP-XACT cannot be treated in isolation, it must remain consistent with other design representations such as RTL, SDC, and register specifications, meaning any error or mismatch can silently propagate across the entire design flow. What design teams truly need is a platform that supports all major standard versions, abstracts away this complexity without sacrificing quality, enables smooth and productive IP-XACT manipulation (building, extracting, and editing), and above all guarantees consistency with RTL to ensure a reliable path to implementation.

Defacto Technologies has been offering an EDA tool called SoC Compiler to efficiently support an IP-XACT design flow for RTL design teams to make IP integration much easier. Their webinar on June 24^th covers a range of topics, like: Pitfalls of IP-XACT, an ideal IP-XACT platform, what SoC Compiler can do in your EDA tool flow.

With SoC Compiler your team members can design with either IP-XACT, RTL or both, while keeping the databases always synchronized, eliminating errors.

Webinar attendees will learn how they can check IP-XACT/RTL consistency, generate any missing views, package IPs, insert IPs, connect IPs, generate top-level views, report connectivity, extract and check system level memory map, and even generate documentation. SoC Compiler users can also use APIs to create, query or edit IP-XACT. Even advanced capabilities like TGI protocol are enabled.

There’s even support for the new Tight Generator Interface (TGI).

Last and not least, the Defacto’s AI Assistant is also presented as a way to help in a smooth tool adoption and also to reduce the IP-XACT required level of expertise.

Webinar Details

See Replay Here

When: June 24^th at 10AM – 11AM PDT

In this Webinar we will show how the Defacto’s SoC design solution fully supports IP-XACT design format. As a unique joint platform managing tightly both IP-XACT, RTL along with other design collaterals such as UPF and SDC, Defacto’s SoC Compiler takes SoC design integration and design packaging to the next level.

Who should attend the webinar
• Design teams who integrate internal and 3rd party IP cores
• RTL designers
• SoC design Architects
• Design Verification engineers

Speakers are Chouki Aktouf, CEO and CTO, and Olivier Florent, Technical Expert.

Related Blogs:

June 18, 2026June 18, 2026

Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late

Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
by Mike Gianfagna on 06-18-2026 at 8:00 am
Categories: AI, Caspia Technologies, Events, Security

I recently posted an overview of an upcoming webinar from Caspia Technologies. That post provides background on the excellent speakers who will present and an overview of the topics they will cover. I recently had the opportunity to attend a dry run of the entire event. The details presented are quite impactful, so I thought I’d provide an update.

Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. This upcoming webinar provides important information on how to build attack-resistant chips. Let’s examine how Caspia shows you how to fix security flaws before it’s too late.

REGISTER HERE

The Presentation

Beau Bakken begins the webinar with a presentation that covers many key topics. He provides an overview of the growing threat landscape. The statistics he shares may shock you. What you don’t know can hurt you. AI agents such as Claude Mythos are autonomously discovering and exploiting vulnerabilities at machine speed. Are you ready for these assaults?

Beau then explores what’s needed to build the required security verification and repair into your design flow. Expertise and scalability are key requirements here. He describes how Caspia’s static RTL checking tool, CODAx adds critical security checking and repair capabilities to any design flow. He shows how to expand your existing Lint processes to include extensive security checks with a tool that is built for non-security engineers. The figure below illustrates how CODAx fits into existing flows.

CODAx in the Design Flow

He then covers some of the very useful new features of the recent CODAx release. These include:

Asset Assist: that automatically identifies security-critical assets, eliminating manual security annotation for certain CODAx checks. This reduces reliance on security experts, enabling non-experts to run with minimal setup.

Report Assist: that summarizes complex violation reports, condensing detailed findings into clear, high-level insights. This facilitates prioritizing highest-risk issues by ranking violations based on impact and exploitability. The result is streamlined triage and remediation, providing a guided context to accelerate debugging and fixes.

The Demo

Dr. Zahin Ibnat then takes you through a comprehensive hands-on security analysis demo. The popular Caliptra open-source root-of-trust design is the primary focus here. She begins with a detailed overview of the design and how CODAx was applied to it. She describes the security issues that were found. A summary of these security issues is shown in the figure below.

Overview of Caliptra Issues Found

She then takes you through the details of how CODAx is applied to this design and how the various security risks are identified. The flow is quite easy to follow. The expertise that CODAx adds to all design flows is very clear. Any engineer can apply expert-level security analysis with this flow. There are many examples of how CODAx simplifies the process. The figure below shows an example of the impact that the new Asset Assist feature delivers.

Impact of Asset Assist

Zahin shows many more security analysis scenarios to identify and fix weaknesses. She concludes with a deep dive on four example violations. By the end of this webinar, you will start to feel like a security expert.

To Learn More

Thanks to sophisticated AI, a growing security threat is coming. This webinar will show you how to be ready for it. If you’re involved in complex chip design, this is a must-attend event. You can reserve your spot for this important webinar event here. And that’s how Caspia shows you how to fix security flaws before it’s too late.