SemiWiki – Page 2 – The Open Forum for Semiconductor Professionals

June 2, 2026June 1, 2026

TSMC Pioneers a New Era in AI-Powered Trade Secret Management, Achieving Intelligent Innovation

TSMC Pioneers a New Era in AI-Powered Trade Secret Management, Achieving Intelligent Innovation
by Daniel Nenni on 06-02-2026 at 6:00 am
Categories: AI, Foundries, TSMC

Launching a “Creativity Integration Partner Intelligent System” for Next-Level Efficiency

As semiconductor manufacturing becomes increasingly knowledge-intensive, protecting intellectual property and trade secrets has emerged as a strategic imperative. The world’s leading foundry, TSMC is advancing beyond conventional information security practices by integrating artificial intelligence into trade secret management. This transformation marks a significant milestone in the evolution of enterprise knowledge protection, enabling intelligent identification, classification, monitoring, and risk mitigation of critical proprietary information.

Trade secrets represent some of the most valuable assets within semiconductor organizations. Process technologies, design methodologies, equipment recipes, yield optimization techniques, materials research, and manufacturing know-how often provide competitive advantages worth billions of dollars. Traditional protection mechanisms, including access controls, document classification systems, and employee compliance programs, have become increasingly challenged by the sheer volume and complexity of digital information generated across advanced semiconductor operations.

TSMC’s AI-powered trade secret management framework addresses these challenges through the deployment of machine learning, natural language processing (NLP), and intelligent data analytics. Rather than relying solely on manual classification, AI systems continuously analyze documents, emails, technical reports, source code, process documentation, and collaborative communications to identify information that may constitute sensitive intellectual property.

A key component of this approach is semantic understanding. Modern large language models and domain-specific AI engines can recognize technical concepts, process parameters, device architectures, and manufacturing terminology associated with proprietary semiconductor technologies. This enables automated classification of sensitive content even when traditional keywords or predefined labels are absent. Such contextual awareness significantly improves the accuracy of trade secret identification while reducing administrative burden.

Another critical capability is intelligent risk detection. AI systems can monitor information flows across enterprise networks, cloud platforms, collaboration tools, and engineering databases to detect anomalous behavior. By establishing behavioral baselines, machine learning models can identify unusual access patterns, abnormal data transfers, excessive document downloads, or atypical collaboration activities that may indicate potential insider threats or unauthorized disclosure risks.

In advanced manufacturing environments, where thousands of engineers and researchers collaborate across multiple disciplines, real-time monitoring becomes essential. AI-driven analytics can evaluate risk scores dynamically, enabling security teams to prioritize investigations and respond proactively to emerging threats. This shift from reactive security management to predictive protection represents a fundamental advancement in enterprise risk management.

The integration of AI also enhances compliance and governance. Semiconductor companies operate within increasingly stringent regulatory environments that require comprehensive documentation of information security practices. AI-powered systems can automatically generate audit trails, maintain classification records, track data lineage, and provide evidence of policy enforcement. These capabilities improve transparency while supporting regulatory and legal requirements associated with trade secret protection.

From an operational perspective, intelligent trade secret management contributes to innovation acceleration. Engineers spend less time manually classifying documents and navigating security procedures, while organizations gain greater confidence in knowledge-sharing activities. AI enables a balance between collaboration and protection, ensuring that critical information remains secure without creating barriers to research and development productivity.

The emergence of generative AI introduces additional complexities and opportunities. As organizations increasingly deploy AI assistants and knowledge management platforms, protecting proprietary semiconductor data becomes even more important. TSMC’s approach demonstrates how AI can be leveraged not only as a productivity tool but also as a safeguard for intellectual capital. Advanced governance frameworks can ensure that sensitive information is appropriately managed within AI ecosystems while preventing inadvertent exposure through automated systems.

Looking ahead, AI-powered trade secret management is likely to become a standard capability across the semiconductor industry. As technology nodes advance toward increasingly sophisticated architectures and manufacturing processes, the value of proprietary knowledge will continue to grow. Organizations that successfully integrate AI into information protection strategies will be better positioned to safeguard innovation, maintain competitive differentiation, and support long-term technological leadership.

Bottom line: TSMC’s leadership in this area illustrates how artificial intelligence can transform cybersecurity and intellectual property management from administrative functions into strategic enablers of innovation. By combining advanced analytics, automation, and domain expertise, the company is establishing a new model for protecting the knowledge assets that drive the future of semiconductor technology.

Trade Secret Sustainable Intelligent Management Center

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TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling

June 1, 2026May 31, 2026

A Look at the High-Profile Speakers Presenting at #DAC2026

A Look at the High-Profile Speakers Presenting at #DAC2026
by Mike Gianfagna on 06-01-2026 at 10:00 am
Categories: 3D IC, AI, Chiplet, Events

Many of us think of DAC as an important trade show for the Semiconductors and EDA industries. That is certainly part of the history of DAC, but the event is also a highly prestigious technical conference dating back to 1964. In fact, the exhibits at DAC began 20 years after the conference started. That long history as a premier technical conference attracts some world-class speakers.

This year, there is a robust agenda of topics and presentations. Some of those details were covered in a recent post by Dan Nenni on SemiWiki. I’ll focus here on the high-level presenters that will be at the event. I’ll finish with details of how to register for DAC, including some background on how a unique, free access pass came to be. Let’s take a look at the high-profile speakers presenting at #DAC2026.

Keynotes

Keynotes typically define the major focus areas for an event.

John Martinis is a distinguished physicist and 2025 Nobel Laureate in Physics, renowned for his pioneering contributions to superconducting quantum computing. His research has been central to developing high-fidelity qubits and engineering the architectures needed for scalable quantum processors. He previously led Google’s quantum hardware team, where his group achieved the landmark 2019 quantum supremacy experiment — the first demonstration of a quantum computer outperforming the world’s most powerful classical supercomputer on a computational task. In 2022, he co-founded Qolab, where he now serves as CTO and continues to advance next-generation superconducting qubit technology and quantum system design.

Baaziz Achour serves as Executive Vice President and Chief Technology Officer of Qualcomm Technologies, Inc. In this role he is responsible for global research and development activities associated with all technologies in QCT, Qualcomm’s semiconductor business, as well as overseeing the execution of enterprise-wide technical and product roadmaps across all business areas. He holds master’s and doctorate degrees in Electrical Engineering from Tufts University and has 24 granted U.S. patents in communications.

Jan Rabaey is Professor Emeritus of the EECS Department at the University of California at Berkeley, after being the holder of the Donald O. Pederson Distinguished Professorship at the same institute for over 30 years. He is a founding director of the Berkeley Wireless Research Center (BWRC), the Berkeley Ubiquitous SwarmLab, and the SIA-DARPA GSRC Center. He served as the Electrical Engineering Division Chair at Berkeley twice. From 2019 until 2025, he also served as the CTO of the System-Technology Co-Optimization (STCO) Division of IMEC, Belgium. I have been involved in EDA for a very long time, and I can tell you that Professor Rabaey’s research has impacted my work over the years many times.

SKYTalks

These presentations feature insights from industry leaders on topics related to EDA and advancements in technology, particularly focusing on AI and semiconductor innovation.

Timothy Costa will kick things off on Sunday. He is the General Manager for Industrial and Computational Engineering at NVIDIA, where he spearheads the strategic development and implementation of solutions for these critical industries. He has played a key role in shaping NVIDIA’s scientific computing offerings and driving innovation in the Quantum Computing industry. He holds a Ph.D. in Mathematics, focusing on numerical methods for modeling fluids and semiconductors.

Lalitha Immaneni is Vice President of Semiconductor Research & Development in the Assembly Test Technology Development organization for Intel Corporation. She manages a world class and diverse team of packaging architects, designers, and specialized engineers in the Advanced Design & Customer Enabling group, spanning multiple geographies. She leads the back end technical interface to Intel’s foundry customers. She is a renowned mentor and coach to countless engineers within and outside Intel.

Huiming Bu is vice president of IBM Global Semiconductors R&D and Albany Operation. He has 20+ years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware. He is also responsible for the IBM Research Albany site and fab operations. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in the semiconductor area.

Artour Levin serves as Corporate Vice President of AI Silicon Engineering at Microsoft Corporation, where he leads the company’s in-house team focused on defining and building advanced silicon AI acceleration technologies — custom hardware designed to power next-generation artificial intelligence workloads. His background combines deep technical knowledge in semiconductor design, system-level architecture, and AI hardware acceleration.

TechTalks

TechTalks aim to provide insights and practical knowledge to attendees about current trends and technologies in the field.

Amit Gupta is Senior Vice President and General Manager of the Solido Custom IC and Central AI divisions at Siemens EDA. He leads the strategic growth and development of Solido’s AI-powered solutions for variation-aware custom IC design, simulation, library characterization, and IP validation, as well as the Fuse EDA AI system. I personally know Amit. He is very smart, articulate and entrepreneurial. He has a presentation style that delivers substantial, ground-breaking information in an approachable and easy-to-understand way.

Jeffrey Pan is the cofounder and CTO of Bronco AI. At age 15, he was the youngest-ever author at CVPR (the highest-impact ML conference). He then won the MIT-IBM Best Paper Award at KDD’s AdvML (Adversarial ML) Workshop, and his real-time edge model won First Place in an international competition focusing on efficient ML and hardware-software co-design. He was then a founding member of an AI research team that deployed generative AI models to hundreds of millions of monthly active users before co-founding Bronco to bring AI to semiconductors and other fundamental industries.

William Wang is the CEO and Founder of ChipAgents.ai, the category leading agentic AI platform for advancing agent-based AI approaches for semiconductor workflows. He is also the Mellichamp Endowed Chair Professor of AI and Designs at UC Santa Barbara, and a global leader in fundamental AI research. He founded the UCSB Center for Responsible Machine Learning, the Mind and Machine Intelligence Initiative, and the UCSB NLP Group. His honors include the IEEE SPS Pierre-Simon Laplace Award, NSF CAREER Award, BCS Karen Sparck Jones Award, DARPA Young Faculty Award, and IEEE AI’s 10 to Watch.

Analyst Reviews

Analyst reviews are a critical part of any industry conference. These presentations bring into focus all the information presented and aim to highlight the macro trends.

Jay Vleeschhouwer has over 40 years of research analyst experience in the technology sector, including software, computer hardware, and imaging technology; Jay was formerly a senior analyst at Merrill Lynch, Josephthal Lyon & Ross, Bear Stearns, and Cantor Fitzgerald. His work has been recognized on numerous occasions in the annual Institutional Investor and Greenwich Associates rankings of analysts.

Dylan Patel is the Founder, CEO, and Chief Analyst at SemiAnalysis – the preeminent authority on all things AI and semiconductors. Through Dylan’s unwavering commitment to excellence, he has built the firm from the ground up as the recognized authority on the semiconductor supply chain to the cloud ecosystem, machine learning models, and all things in between.

Going To DAC

DAC will be held July 26–29, 2026, at the Long Beach Convention Center in California. There are many reasons to attend the conference. The speakers highlighted in this post are just another aspect of why this show is so important.

You can register for the conference here. It’s important to note that the I Love DAC program provides free access to Keynotes, SKYTalks, TechTalks and Panels in the DAC Pavilion, and the Exhibitor Forum. You also have access to the Exhibit Hall and daily networking receptions.

Take note: I Love DAC passes are free until July 12, 2026. When I was at Atrenta back around 2010 I got a call from the marketing team at Denali. In those days, large exhibitors got a lot of free DAC passes to give to customers and prospects. The Denali folks proposed that we join forces and offer our combined free ticket inventory to folks who couldn’t afford to attend DAC. That was the birth of the I Love DAC program. It’s become quite popular over the years and is now administered directly by the conference organizers.

And that’s a look at the high-profile speakers presenting at #DAC2026.

Also Read:

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Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

June 1, 2026June 1, 2026

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P
by Daniel Nenni on 06-01-2026 at 6:00 am
Categories: IP, Mixel, Silvaco, TSMC

The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability of C-PHY/D-PHY combo IP implemented on the TSMC N2P process, enabling higher bandwidth, lower power, and improved area efficiency for next-generation applications.

MIPI interfaces have become the de facto standard for connecting cameras, displays, and sensors in mobile and embedded systems. While D-PHY has long dominated the ecosystem, the increasing data requirements of advanced image sensors and ultra-high-resolution displays are accelerating adoption of MIPI C-PHY. The latest combo PHY solutions provide support for both standards within a unified implementation, giving SoC developers maximum flexibility while reducing integration complexity.

The Mixel combo IP is the industry’s first to support MIPI D-PHY v3.6 with Embedded Clock Mode (ECM), marking an important milestone in MIPI interface evolution. ECM eliminates the dedicated clock lane traditionally required in D-PHY architectures by embedding clock information within the data stream itself. This innovation reduces pin count, simplifies routing, and improves channel efficiency while maintaining backward compatibility with existing MIPI ecosystems.

For advanced nodes such as TSMC N2P, these architectural improvements are particularly significant. The N2P process provides enhanced performance-per-watt characteristics compared to prior generations, making it well suited for power-sensitive applications that still require extremely high throughput. Combining N2P with a next-generation combo PHY allows designers to fully leverage the node’s capabilities while minimizing system-level overhead.

The integration of C-PHY and D-PHY functionality into a single IP block also enables seamless interoperability across multiple use cases. Camera subsystems, for example, may require D-PHY compatibility for legacy sensors while simultaneously supporting high-bandwidth C-PHY links for next-generation image processing pipelines. A combo implementation reduces die area compared to separate PHY solutions and simplifies validation across different product configurations.

MIPI C-PHY delivers substantially higher throughput efficiency than conventional D-PHY implementations by utilizing three-wire trios and embedded clocking techniques. This enables higher effective bandwidth without proportionally increasing pin count or operating frequency. As image sensor resolutions continue to scale beyond 100 megapixels and display refresh rates move toward 240Hz and beyond, these efficiency gains become increasingly valuable.

Meanwhile, D-PHY v3.6 introduces Embedded Clock Mode specifically to address scaling challenges associated with traditional source-synchronous clock architectures. By embedding the clock within the transmitted data stream, ECM reduces EMI concerns and improves signal integrity in dense package environments. This is especially beneficial in advanced packaging technologies such as chiplets and fan-out integration, where routing congestion and signal coupling are major design considerations.

The implementation of combo PHY IP on TSMC N2P also requires extensive analog and mixed-signal optimization. Advanced process nodes introduce new variability and tighter voltage margins, making robust PHY design more challenging. High-speed I/O circuits must maintain signal integrity across process, voltage, and temperature corners while meeting increasingly stringent power budgets.

To address these requirements, modern combo PHY architectures incorporate adaptive equalization, low-jitter PLLs, advanced calibration techniques, and sophisticated power management schemes. These features ensure reliable operation at multi-gigabit data rates while minimizing active and standby power consumption. For battery-powered devices, these optimizations directly translate into improved user experience and extended operating life.

Another important advantage of N2P-based PHY implementations is support for AI-enabled edge systems. Emerging applications such as autonomous robotics, intelligent surveillance, and spatial computing require massive sensor bandwidth combined with low latency and high energy efficiency. MIPI interfaces are increasingly central to these workloads because they provide standardized, scalable connectivity between sensors and compute engines.

Automotive applications are also driving demand for advanced PHY solutions. Next-generation vehicles integrate multiple high-resolution cameras, driver monitoring systems, and immersive displays, all of which require robust high-speed interfaces. Combo PHY implementations supporting both C-PHY and D-PHY enable automotive SoCs to accommodate a broad range of sensor and display configurations while maintaining compliance with evolving industry standards.

Bottom line: As semiconductor scaling continues, interface IP is becoming a critical differentiator for SoC platforms. The availability of C-PHY/D-PHY combo IP on TSMC N2P demonstrates how interface technologies are evolving alongside process innovation to meet escalating bandwidth and efficiency demands. With support for MIPI D-PHY v3.6 Embedded Clock Mode, Mixel’s implementation represents a significant advancement in next-generation connectivity infrastructure for mobile, automotive, AI, and consumer electronics applications.

Contact MIXEL

Also Read:

Mixel Company Update 2025

Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY

Mixel at the 2025 Design Automation Conference #62DAC

May 31, 2026May 29, 2026

John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager

John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio Manager
by Admin on 05-31-2026 at 4:00 pm
Categories: ESD Alliance, Events, Semiconductor Services

John Barr, Portfolio Manager of the top-ranked Needham Aggressive Growth Fund, has built a career with skills honed not just on Wall Street, but in the trenches of the early EDA industry.

Before becoming a respected sell-side analyst and later a buy-side portfolio manager, Barr spent 15 years in the EDA industry, working through marketing, sales and corporate development. It’s a foundation he credits for nearly everything that followed.

His entry into EDA was almost accidental. Fresh from Harvard Business School, Barr joined Communications Satellite Corporation’s corporate development group and worked on projects in various industries, including EDA. He then joined the new Comsat division, which had been launched just before Daisy Systems, Mentor Graphics and Valid Logic.

Comsat had acquired companies with the leading microwave, circuit and logic simulation products. What it lacked in ease of use and integration, it made up with powerful simulators. A few years later, the division was sold to GE Calma, which had the leading IC layout system, sending him through a labyrinth of corporate actions and long-ago EDA companies including HHB Systems, Cadnetix, Daisy, Racal-Redac and Interconnectix. It also meant moves from Washington, D.C. to Austin, to New Jersey, to Japan, and back to New Jersey

It sounds chaotic. Barr frames it differently. It gave him a unique understanding of technology and business.

“I learned so much,” he says without hesitation. “Founder vision is important, and engineer-led companies are good. Important customer backing goes a long way. Good things take time. Every quarter-end is a miracle. Third-party marketing deals are rarely a big deal. Layoffs are hard on an organization and its people. Mergers and acquisitions are really hard.”

He lived all of it. He was part of HHB’s IPO, which occurred just days before the Black Monday stock market crash of October 19, 1987. Within a few months, Cadnetix and HHB agreed to a friendly merger, which was designed to fend off a hostile takeover by Daisy — only to become the poison pill that left an over-leveraged Daisy heading toward collapse and Chapter 11. What followed was a friendly acquisition by U.K. firm Racal-Redac, and six years later, to a company breakup, layoffs, and the dispersal of assets: the front-end tools went to Viewlogic. The PCB CAD tools went to Zuken, which survives to this day. Barr was let go.

“All of that,” he reflects, “provides a complete history of everything you might want to go through if you want to be an investor.”

From Layoff to Needham

The layoff forced him to reconsider his path. He had always been interested in stocks and investing. He took six months and immersed himself in finding a Wall Street position. He wrote a report on the EDA industry and networked with analysts, investment bankers, traders and investors.

Alas, while he got close on a couple of positions, there were no job offers. He gave up on the idea and was fortunate to join a great, venture-backed EDA startup called Interconnectix, which had a very clever signal integrity-based PCB routing technology.

After a year, he learned that Needham & Company had an opening for a sell-side analyst. It turned out to be a natural fit. “A small firm like Needham was willing to take a chance,” he says. “They prided themselves on people with unconventional backgrounds — and I was it.”

Barr joined Needham’s sell-side in 1995. This timing put him at the center of one of the most extraordinary IPO windows in history. He was the analyst when Meta-Software, Analogy, OrCAD, and Summit Design went public.

In July 2001, he was recruited to Robertson Stephens, which he describes plainly as “the epicenter of the tech bubble.” In March of 2000, the tech market had started its crash, but there were a number of great, small, EDA companies poised to go public. Virage Logic and Synplicity went out in 2000 and were in the top 10 IPO performers of the year. 2001 was a terrible year for the markets and IPOs.

EDA companies defied the tide: four of the top ten performing IPOs of 2001 were EDA companies. Verisity was number one; Magma was second; NASSDA was fourth; and PDF Solutions was eighth. Simplex, he notes, had the best opening-day performance of 2001— up 77%.

What were the highlights? What was the greatest memory? “Taking those great EDA companies public in 2000 and 2001. Introducing them to small-cap institutional investors in the public markets — it really was something the whole EDA industry should be proud of. My greatest memory on the sell-side was helping those great companies and their leaders go public and be introduced to investors,” Barr says.

The Long View

Barr returned to Needham in 2009 and moved to the buy side, co-managing the firm’s mutual funds — a role he holds today. His EDA years give him an interpretive lens few investors possess: he’s seen these companies not just as ticker symbols, but from the inside.

It’s worth noting that of all the companies from the 2000 and 2001 vintages, PDF Solutions is the only one still publicly traded — and it remains in Barr’s current portfolio. Its CEO, co-founder and Director John Kibarian also serves as Co-Chair of the ESD Alliance’s Governing Council.

Now, as venture-backed agentic AI startups begin reshaping EDA, Barr watches with informed curiosity. Whether this moment echoes 2000–2001 remains to be seen. For those wanting early insight, the ESD Alliance’s Executive Outlook June 10 features a panel on “How Will Agentic AI Change Chip Design and Verification?”

Event Details:

Date: Wednesday, June 10
Location: Cadence Design Systems, 2655 Seely Avenue, San Jose, Calif.
Schedule: Networking, dinner and beverages at 5:30 p.m.; panel begins at 6:30 p.m.
Panelists: Three agentic AI entrepreneurs, plus EDA executives including Wally Rhines (longtime CEO of Mentor Graphics, now CEO of Silvaco)
Tickets: Registration is open and free for SEMI/ESDA members. SemiWiki readers should use the SEMIWIKI50 promo code for 50% off the non-member $40 per person rate.

Members of the EDA ecosystem, the semiconductor industry, startups and emerging companies are also invited to attend “Navigating Export Controls in EDA,” a free webinar Thursday, June 11, on why and how governments implement trade controls. Presented by members of SEMI’s Public Policy and Advocacy team and Cadence representatives The webinar is free to attend, but registration is required.

Julie Rogers
Executive Director
ESD Alliance, a SEMI Technology Community

Also Read:

SemiWiki Q&A with Julie Rogers, Executive Director, ESD Alliance

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Podcast EP333: A Look at the Broad, Worldwide Impact SEMI Has on the Semiconductor Industry with Ajit Manocha

May 31, 2026May 29, 2026

CEO Interview with Vivek Vishwakarma of ThirdAI Automation

CEO Interview with Vivek Vishwakarma of ThirdAI Automation
by Daniel Nenni on 05-31-2026 at 2:00 pm
Categories: CEO Interviews

Vivek Vishwakarma is an entrepreneur, investor, and technologist leading ThirdAI Automation, an industrial AI company that accelerates troubleshooting and reporting through automated root-cause analysis. A former technologist at Intel with 10+ patents and 300+ research citations, he speaks on the intersection of advanced manufacturing, data, and AI.

Tell us about your company.

ThirdAI Automation is an industrial AI company building Causal AI for the semiconductor equipment ecosystem. Co-founded by Vivek Vishwakarma (CEO) and Dr. Sainyam Galhotra (CTO and Cornell University faculty, with deep research credentials in causal inference), the company is backed by a $3M seed round led by Endiya Partners and Capria Ventures. We operate across dual headquarters in San Francisco and Bengaluru, with active pilots across leading semiconductor equipment vendors and select Fortune 500 manufacturers, spanning the U.S., Japan, Israel, and Taiwan. Our platform converts fragmented logs, sensor telemetry, and tribal engineering knowledge into automated root-cause intelligence, engineered to run on standard CPU infrastructure inside the air-gapped, on-premise environments where our customers’ tools operate.

What problems are you solving?

We solve the diagnostic-latency problem that sits between equipment vendors and their fab customers. When a CMP, lithography, etch, deposition, or packaging tool experiences a fault or process excursion at a customer site, the equipment vendor’s field-service and applications-engineering teams typically spend hours to days digging through logs, recipes, and historical incidents to isolate the root cause, while the customer’s tool sits down and wafers accumulate at risk. Our Causal AI agents automate this work, compressing diagnostic cycles that historically take 8 hours of expert time down to roughly 12 minutes, and surfacing not just what failed but why. The economic stake is substantial on both sides: tool vendors protect their uptime SLAs, lower field-service costs, and codify the tribal expertise of senior engineers; their fab customers avoid the millions in scrapped wafers a single calibration drift can cause at advanced nodes.

What application areas are you strongest in?

Our strongest position is across the semiconductor equipment vendor ecosystem, spanning Front-End-of-Line (FEOL), Back-End-of-Line (BEOL), and advanced packaging. We work with vendors of CMP, lithography, etch, deposition, metrology, inspection, bonding, and dicing tools, where unplanned downtime at a customer fab carries the highest cost. Our deployments are designed to plug into the vendor’s own service workflow, supporting field-service engineers, applications engineers, and process-development teams, and increasingly inside the equipment itself, so the diagnostic intelligence travels with the tool to the customer site.

What keeps your customers up at night?

Tool vendors today are squeezed on multiple fronts. Uptime SLAs at advanced nodes are tighter than ever, and a single delayed root cause can trigger penalty clauses or, worse, escalate into a customer relationship issue. Field-service costs keep climbing, sending senior engineers on-site to diagnose intermittent issues is expensive, slow, and increasingly hard to staff as veteran engineers retire and take decades of tribal knowledge with them. On top of that, fab customers won’t allow cloud connectivity into their environments, which rules out most modern AI options for vendors trying to scale diagnostics across their installed base. Our deployment model addresses all of this: faster RCA, codified institutional knowledge, and CPU-based on-premise inference that fits inside the most secured customer environments.

What does the competitive landscape look like, and how do you differentiate?

The market sits between two extremes: legacy SPC and FDC tools that detect anomalies but don’t explain them, and modern AI vendors (Augury, UptimeAI, Aitomatic, GaussLab/PDF Solutions, Ethon.ai, CausalLens) that require heavy GPU infrastructure and often cloud connectivity that tool vendors simply cannot deploy inside their customers’ fabs. We differentiate on three axes. First, causality: most AI tells you what happened, our platform tells you why, anchored in our CTO’s published research in causal inference, which is what closes the diagnostic loop rather than producing more alerts. Second, infrastructure fit: our engine runs on standard CPUs and is built to ship inside on-premise, air-gapped customer environments , exactly where our equipment-vendor customers need to land. Third, time-to-value: structured pilots typically deliver measurable RCA acceleration within 8 to 12 weeks of ingest.

What new features and technology are you working on?

We are extending our Automated Root Cause Analysis (ARCA) agents in three directions. First, multi-modal data ingestion, combining structured machine telemetry with unstructured sources like maintenance manuals, ECN notes, and engineer ticket logs. Second, closed-loop diagnostics, where the platform not only identifies the failure but also surfaces the precise maintenance or recipe-adjustment protocol from the tool’s documentation, turning every diagnostic event into an action. Third, we’re rolling out a dedicated MLOps platform that allows equipment vendors and their teams to manage their own models, including bring-your-own-model workflows, within the same lightweight inference layer, so vendors can extend the platform into their own intellectual property over time.

How do customers normally engage with your company?

Engagement typically begins with a structured pilot, 8 to 12 weeks, where we ingest historical log and telemetry data from a specific toolset and benchmark RCA performance against the customer’s existing process. Successful pilots transition into a multi-year platform license, deployed either inside the customer’s private cloud or fully on-premise within their service infrastructure. Pricing is tiered (Pilot, Professional, Enterprise) with hybrid subscription plus usage components. For equipment vendors who want the diagnostic intelligence to travel with their tools to end customers, we also offer a per-tool OEM licensing model, allowing vendors to embed the platform inside the equipment they deliver, while preserving customer data sovereignty and ThirdAI’s underlying platform IP.

Also Read:

CEO Interview with Vivek Raghunathan of Xscape Photonics

CEO Interview with Baratunde Cola of Carbice

CEO Interview with RP Singh of Seasia Infotech

Podcast EP348: How Lemurian Labs is Building the Foundation for AI’s Next Era with Jay Dawani

Podcast EP348: How Lemurian Labs is Building the Foundation for AI’s Next Era with Jay Dawani
by Daniel Nenni on 05-29-2026 at 10:00 am

Daniel is joined by Jay Dawani, co-founder and chief executive officer of Lemurian Labs, where he leads the company’s mission to reinvent AI infrastructure for greater efficiency, accessibility and performance. With a background spanning AI system architecture, hardware-software co-design and performance optimization, Dawani has built AI-powered systems for autonomous vehicles, spaceflight and large-scale model deployment. Before founding Lemurian Labs in 2022, he advised on NASA’s Mars Rover program at Geometric Energy, focusing on vision-based navigation and planetary mapping. A frequent speaker and commentator, Jay is passionate about shaping AI infrastructure to broaden access, accelerate innovation and unlock new frontiers in intelligent computing.

Dan explores Lemurian Labs’ unique perspectives and technologies with Jay, who describes Lemurian’s software stack that can run AI workloads on any hardware at any scale. Jay describes how Lemurian achieves this while matching or exceeding the performance of hand-tuned kernels. He discusses the differing requirements of edge vs. cloud applications and the fact that moving data is a very expensive part of the process that should be focused on.

In this far-reaching and very informative discussion, Jay describes why maximizing useful intelligence per joule is critical, and what fundamental changes Lemurian Labs brings to the development process to achieve this.

Contact Lemurian Labs

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

May 29, 2026May 31, 2026

Why Generic LLMs Fall Short for Critical Engineering Documentation

Why Generic LLMs Fall Short for Critical Engineering Documentation
by Mike Gianfagna on 05-29-2026 at 8:00 am
Categories: AI, EDA, llmda.ai

Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.

Modern LLMs can generate polished technical prose, summarize complex inputs, and connect to enterprise systems through agents, skills, and connectors. It’s easy to imagine a workflow where engineering teams simply connect an LLM to Jira, Confluence, design repositories, or internal specifications and ask it to generate a user guide, limitations section, technical reference manual, or release note.

But the reality is more complicated. A new white paper from llmda.ai examines the true complexity and cost involved. A link to the white paper is coming but first let’s examine some details. Engineering documentation is not just a writing problem. It is a precision production process for technical truth. And that distinction changes everything. And that’s why generic LLMs fall short for critical engineering documentation.

Engineering Documentation Is Not Ordinary Content

Unlike marketing copy, internal notes, or general knowledge articles, hardware and systems engineering documentation must be correct, repeatable, traceable, and governed. A single incorrect register definition, interface description, timing constraint, or product limitation can create real downstream consequences.

Documentation errors can lead to design confusion, validation gaps, customer escalations, support burdens, schedule delays, and reputational damage. That means automation cannot simply produce content that sounds right. It must produce content that is grounded in authoritative sources, aligned to the correct product revision, reviewable by the right stakeholders, and suitable for formal publishing.

This is where generic LLM approaches begin to hit limits.

The Hidden Cost of “Just Use Claude”

The white paper explains that the real cost of using a general-purpose LLM is not token consumption. Tokens are usually the smallest part of the equation.

The larger cost is the internal platform an organization must build around the LLM to make it safe for engineering documentation. A generic model may provide the language engine, but the enterprise still needs to build ingestion pipelines, retrieval systems, grounding logic, citation traceability, template enforcement, approval workflows, publishing pipelines, access controls, audit logs, monitoring, and version alignment.

In other words, the company does not just adopt an LLM. It becomes an internal documentation platform vendor.

This is especially important because engineering documentation is deeply tied to product lifecycle management. Documents must track Rev A versus Rev B. They must align with RTL, IP metadata, design specifications, validation reports, and release notes. They must be updated incrementally and consistently. They must also support structured formats such as Word, PDF, DITA, ReST, and other publishing outputs.

Generic LLMs were not designed to provide this full enterprise layer out of the box.

Prompting Becomes Programming

The white paper also highlights a subtle but important operational problem: prompting becomes programming, but without the guarantees of software engineering.

For example, asking an LLM to “generate the Limitations section from Jira tickets” may work in a demo. But in production, Jira fields change. Ticket formats vary. Metadata may be missing. Release labels may be inconsistent. Internal comments may contain sensitive or unverified information. The model may classify bugs incorrectly, omit critical constraints, or elevate ambiguous internal language into published documentation.

The point is made that LLMs are not useless. They are powerful drafting tools. The problem is that high-stakes engineering documentation requires determinism, repeatability, and auditability. A probabilistic prompt-driven workflow is difficult to test, difficult to reproduce, and difficult to govern at scale.

llmda Spectra™ – Why Purpose-Built Matters

The white paper estimates that building a llmda Spectra-like documentation automation system around a generic LLM could require a dedicated multidisciplinary team of six to eight engineers, including backend, machine learning, DevOps, security, workflow, and publishing expertise. Annual staffing costs are estimated at roughly $1.5 million to $2.5 million, with a typical 12- to 24-month time-to-value.

The opportunity cost may be even higher. Every engineer assigned to internal documentation infrastructure is an engineer not working on silicon innovation, system architecture, performance optimization, customer features, or other product-differentiating work. Depending on product velocity and market timing, the white paper estimates that delayed revenue opportunities could reach $5 million to $50 million.

That is the central economic argument: the “cheap” LLM path can become expensive when organizations must build the missing enterprise infrastructure themselves.

The alternative presented in the white paper is llmda Spectra, a platform built specifically for engineering documentation automation. Spectra is positioned not as a general-purpose assistant, but as a governed documentation system designed for source-grounded generation, deterministic workflows, structured engineering outputs, role-based access control, revision-aware versioning, collaboration, sign-off, tool execution, and publishing integration.

This distinction matters. A drafting assistant can help individuals move faster. A documentation platform helps organizations produce reliable, reviewable, publishable engineering content at scale.

To Learn More

Generic LLMs have an important role to play in engineering productivity. They can accelerate drafting, summarization, brainstorming, and individual workflows. But when documentation becomes part of the product lifecycle, the requirements change.

Engineering teams need more than fluent text. They need source-grounded truth, repeatable generation, governed workflows, secure collaboration, structured outputs, and auditable decisions.

That is why the white paper’s conclusion is direct: use LLMs where they help, but do not rebuild an engineering documentation platform from scratch when a purpose-built solution already exists. If this discussion resonates with your needs when building complex systems, you must download this white paper.

You can access your copy here to better understand why generic LLMs fall short for critical engineering documentation.

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May 29, 2026May 28, 2026

Re-Spins Get You Fired, Says Intel CEO Lip-Bu Tan

Re-Spins Get You Fired, Says Intel CEO Lip-Bu Tan
by Daniel Nenni on 05-29-2026 at 6:00 am
Categories: Foundries, Intel Foundry

Intel CEO Lip-Bu Tan’s statement that “re-spins get you fired” reflects the enormous pressure facing semiconductor companies as chip complexity, manufacturing costs, and competitive demands continue to rise. In the semiconductor industry, a “re-spin” occurs when a chip design must be revised and manufactured again because of errors discovered after tape-out or during silicon validation. These mistakes can cost millions of dollars, delay product launches by months, and damage customer confidence. Tan’s warning highlights how critical execution has become for Intel as it attempts to regain leadership in the global semiconductor industry.

“I have a culture right now I have just implemented. It has to be A0 to production,” Tan told the JP Morgan Global Technology, Media and Communications Conference, “A0 is when you tape out, first time pass. Intel does not have that culture, so I tell that, first time pass A0. B0, you keep your job. Anything above that, you are fired.”

“People initially thought that I’m just joking,” he told the J P Morgan conference, “now I started to implement, they started to say that, ‘Okay, Lip-Bu, you are very serious, you really look into all the design, all the bugs that we’ve tried to fix, and then all the IP that we use. You make sure that we certify and make sure we do that before we go to tape-out.”

“Those are kind of the culture we need to have,” said Tan.

Intel built its dominance on engineering excellence and manufacturing discipline. For decades, the company led the industry through advanced process technology and strong x86 processor designs. However, in recent years Intel struggled with manufacturing delays, roadmap changes, and execution problems that allowed competitors such as AMD, NVIDIA, and TSMC to gain significant ground. Under Tan’s leadership, Intel is trying to restore confidence among customers, investors, and partners. His comments about re-spins send a clear internal message that costly design mistakes are unacceptable.

The financial consequences of a chip re-spin are severe. Modern semiconductors contain billions of transistors and are produced using extremely advanced manufacturing nodes. Mask sets for leading-edge chips can cost tens of millions of dollars, especially at technologies such as 3nm and 2nm. If a flaw is discovered after production begins, engineers may need to redesign parts of the chip and restart portions of the manufacturing cycle. This creates additional expenses while delaying product launches and reducing competitiveness.

Timing is especially important in high-growth markets such as artificial intelligence, cloud computing, and advanced data centers. Missing a product launch window by even a few months can shift market share to rivals. Intel has already experienced this challenge while competitors accelerated their positions in AI accelerators and high-performance computing. Tan’s statement reflects the reality that execution speed and product reliability are now strategic weapons in the semiconductor business.

The complexity of chip design also means that verification and validation have become more important than ever. Modern processors require coordination among thousands of engineers working across architecture, software, packaging, manufacturing, and testing. Detecting errors before tape-out is critical because correcting them later becomes dramatically more expensive. By emphasizing accountability, Tan is reinforcing the need for rigorous engineering discipline throughout Intel’s development process.

However, some critics might argue that such a strong message risks creating a culture driven by fear rather than innovation. Semiconductor design is one of the most difficult engineering disciplines in the world, and even the best companies encounter technical setbacks. Excessive pressure can discourage engineers from taking necessary risks or experimenting with bold new ideas. Successful leadership requires balancing accountability with an environment that still encourages innovation and collaboration.

Nevertheless, Intel’s current situation explains why management is emphasizing flawless execution. The company is investing heavily in manufacturing expansion, advanced packaging, and foundry services while attempting to compete aggressively in AI and high-performance computing. Customers and investors are closely monitoring whether Intel can execute its roadmap successfully. In this environment, re-spins are more than technical errors; they represent delays, lost revenue, and reduced confidence.

Bottom line: Lip-Bu Tan’s statement symbolizes the harsh realities of today’s semiconductor industry. As chip development becomes more expensive and competition intensifies, companies cannot afford repeated mistakes. For Intel, avoiding re-spins is not only about reducing costs but also about restoring credibility, accelerating innovation, and proving that the company can once again lead the semiconductor industry through disciplined execution and engineering excellence.

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May 28, 2026May 28, 2026

Caspia’s AI Makes You a Security Verification Expert

Caspia’s AI Makes You a Security Verification Expert
by Mike Gianfagna on 05-28-2026 at 10:00 am
Categories: AI, Caspia Technologies, Events, Security

Let’s face it, powerful, highly trained AI is making it easier to find security flaws in many systems. When the attack surface becomes the underlying hardware, the risks grow exponentially. Unlike software, hardware can’t easily be “patched”. Early, advanced security verification is the way to mitigate these risks, but doing it right requires the scarce skillset of advanced security experts.

Caspia Technologies is changing all that. Thanks to its sophisticated and easy to use security verification platform, any design team can apply expert security verification by adding Caspia tools to their existing and proven design flow. Caspia will explain how this all works in an important, must-attend webinar on June 24. More details are coming, but let’s examine what you will learn at this webinar and how Caspia’s AI makes you a security verification expert.

Webinar Presenters

This webinar is being presented in collaboration with SemiWiki and Caspia Technologies. Presenting for Caspia are:

Beau Bakken

Beau Bakken, who will provide an overview of the new AI-driven features of the latest release of CODAx, Caspia’s RTL static security enhancement tool. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go-to-market strategies. Beau has been with Caspia for over five years. Before that, he spent time at the National Science Foundation.

Dr. Zahin Ibnat

Dr. Zahin Ibnat will then present actual results that CODAx found in a popular root-of-trust design. She will explain the nature of the security flaws and run a live hands-on demo of CODAx. Zahin is an R&D Application Engineer at Caspia. She works with customers to ensure effective deployment of Caspia’s solutions.

Some of What Will Be Covered

You will learn details of the new CODAx AI-driven features, Asset Assist and Report Assist. These features significantly enhance the usability of CODAx, facilitating wider deployment across all design teams without requiring security expertise. Asset Assist performs automated asset identification on the target design using design-specific details to find a much broader list of security-relevant attributes. Report Assist addresses the process of understanding the impact of violations to develop a prioritized solution strategy.

You will learn how these new features can reduce weeks to months of security verification to minutes to hours, allowing existing design teams to perform advanced security verification more broadly and more effectively with no advanced training or changes to the existing design flow.

The results of a security audit of popular security IP block will also be presented. The Caliptra root-of-trust represents a production-grade, open-source security IP developed to serve as a foundational trust anchor in SoC designs. It contains over 700 design files, amounting to more than 300,000 lines of RTL code.

The demo will show the ease of use the new AI-driven features in CODAx. The impact is non-security engineers are now able to perform expert-level security analysis and remediation. The figure below is a high-level summary of some of the security features delivered by CODAx. The webinar will go into more detail of how these features work together to make every engineer a security expert.

CODAx Security Checks

To Learn More

Caspia recently issued a press release that provides more details about the new AI-driven security features of CODAx. More details about what was found in the Caliptra root-of-trust design are also presented. You can access the press release here. You don’t want to miss the upcoming webinar on June 24. Secure your spot at this important event today, so you can learn how Caspia’s AI makes you a security verification expert.

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CFrame60: Rewriting the Rules of Frame Compression

CFrame60: Rewriting the Rules of Frame Compression
by Daniel Nenni on 05-28-2026 at 8:00 am
Categories: Chips&Media, IP

Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality, CFrame60 introduces a flexible framework supporting both lossless and lossy compression while minimizing SRAM requirements and DRAM traffic. The architecture is optimized for ISP pipelines, NPUs, VPUs, GPUs, and display subsystems where power efficiency and latency are critical design constraints.

One of the key architectural advantages of CFrame60 is its ability to process both raster-scan and block-based pixel ordering. Traditional compression schemes such as AFBC and DSC often require large line buffers because the compressor and decompressor operate in different pixel orders than adjacent IP blocks. This mismatch forces the system designer to implement SRAM-heavy line conversion stages. In 4K YUV422 10-bit systems, these line buffers can exceed 160KB, significantly increasing silicon area and power consumption. CFrame60 eliminates this requirement by supporting native interoperability with raster-scan pipelines used in ISP and display engines as well as block-based ordering commonly found in video codecs.

The CFrame60 product family consists of three major configurations: CFrame60C, CFrame60V, and CFrame60R. CFrame60C targets general-purpose lossless and lossy compression for ISP, NPU, and display applications. CFrame60V extends the architecture to support video processing systems requiring mixed raster and block-mode operations. CFrame60R further adds random access and partial update capabilities for advanced memory-efficient workflows. This modular product segmentation enables SoC architects to optimize implementation cost according to workload requirements while maintaining software compatibility across the platform.

Random access functionality in CFrame60R is particularly important for modern imaging systems and AI-enhanced video pipelines. Conventional frame compression solutions typically require sequential decompression beginning from the start of the bitstream. In contrast, CFrame60R supports decompression at arbitrary Access Units (AUs), allowing direct retrieval of localized image regions. This capability dramatically reduces unnecessary memory reads and lowers latency in warping, distortion correction, and region-of-interest processing applications. Partial update support additionally allows modified AUs to be rewritten independently without recompressing the entire frame, making the architecture highly efficient for interactive graphics and dynamic overlays.

Another technical differentiator is the rate-control mechanism used in lossy mode. Many competing frame compression solutions rely on fixed bitrate allocation that can introduce visible artifacts in flat textures or high-frequency edge regions. CFrame60 incorporates image complexity detection to dynamically allocate compression resources based on local image characteristics. Internal benchmark comparisons against DSC 1.2, AFBC, and JPEG-XS demonstrate superior PSNR and SSIM metrics across standard DSC test sequences. In challenging textures such as fine text rendering, noise gradients, and sweep patterns, CFrame60 achieves visually lossless quality while maintaining compression ratios between 1/2 and 1/4.

The hardware implementation is also optimized for low-latency operation. CFrame60 requires only one to two lines of latency compared with competing architectures that may require 16 to 32 lines of buffering. This reduction directly improves responsiveness in real-time video systems and lowers memory subsystem pressure. The IP supports YUV400, YUV420, YUV422, YUV444, RGB, and Bayer formats with bit depths ranging from 8-bit to 16-bit, enabling deployment across camera, automotive, AI, and professional imaging markets. Standard interfaces include AXI4 and on-the-fly ready/valid streaming protocols, simplifying integration into heterogeneous SoC environments.

From a performance perspective, CFrame60 scales efficiently through multi-core operation. A single core supports 4K 60fps processing at frequencies ranging from 250MHz to 450MHz depending on chroma format, while eight-core implementations can scale up to 8K 120fps or 16K 30fps applications. Silicon area is also competitive, with encoder logic sizes ranging from approximately 85K to 165K gates depending on feature configuration and supported bit depth. Memory requirements remain comparatively small, contributing to reduced total SoC power consumption.

The broader significance of CFrame60 lies in its system-level efficiency. As AI-enhanced imaging, computational photography, and high-resolution video continue driving memory bandwidth growth, compression IP becomes increasingly critical to overall SoC scalability. By combining flexible processing order support, low SRAM dependency, high image quality, and random access capability, CFrame60 positions itself as a practical alternative to legacy display-oriented compression technologies. The roadmap toward CFrame70 further indicates expansion into ultra-high-ratio visually lossless compression targeting JPEG-XS-class applications while maintaining smaller silicon footprint and simplified operation models.

CONTACT Chips&Media

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