SemiWiki – Page 3 – The Open Forum for Semiconductor Professionals

May 28, 2026May 27, 2026

Quantum Simulation Using Decision Diagrams. Innovation in Verification

Quantum Simulation Using Decision Diagrams. Innovation in Verification
by Bernard Murphy on 05-28-2026 at 6:00 am
Categories: Quantum Computing
2 Comments

Quantum gate simulation complexity explodes as qubit counts increase. One way to manage this complexity in simulation on classical computers is through use of decision diagrams in place of matrices. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Advanced Simulation of Quantum Computations. The authors are from Johannes Kepler University in Austria. The paper was published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2019 and has 128 citations.

The key innovation in this paper is use of decision diagrams (DDs) to significantly reduce simplify matrices and vectors which otherwise explode exponentially with increasing qubit count. This DD direction is becoming very popular in research. Further, DDs are already well known in EDA for use in formal methods and synthesis for example, making this direction appealing for our audience.

Slightly long article this time, but Paul and Raul so obviously enjoyed the topic that I felt it would be wrong to condense their input!

Paul’s view

Many years ago, while working on my PhD, I found myself reading Randy Bryant’s seminal 1986 paper on ordered binary decision diagrams (OBDDs) for the efficient representation of Boolean expressions. It was one of those “wow, so cool!” moments for me. This month’s paper applies those same ideas to quantum simulation, and it’s definitely another “wow, so cool!” moment for me.

Quick recap on our first blog on Quantum simulation from December last year: an n-qubit quantum circuit operates probabilistically on all 2ⁿ possible values of those qubits. Simulating such a circuit involves forming a 2ⁿ “state vector” representing the probabilities of those qubits being in each of their 2ⁿ possible states, and then multiplying this state vector by a 2ⁿ by 2ⁿ “next state function” constructed based on the topology and connectivity of the quantum gates in the circuit. It’s conceptually very similar to how an analog circuit is simulated, just that the complexity of the problem is O(4ⁿ) vs. O(n²). The goal of a quantum algorithm is to iteratively twiddle the state vector probabilities till the right answer has close to 100% probability, and the wrong answers close to 0%.

In this month’s paper, the authors propose to construct an OBDD-like object to represent the state vector, and next state function called a quantum multi-valued decision diagram (QMDD). They observe that in practical quantum circuits, very few distinct probabilities exist in the state vector – most are zero, and the non-zero ones are often the same, or share common factors. So a BDD-like object can be constructed with very few distinct leaf nodes, especially if branches in the tree can be weighted with numerical factors. For the next state function matrix, case splitting on a qubit is done 4 ways, one for each quadrant of the matrix (think <current,next> state pair for each qubit). Again, lots of scope for compression here since matrices can be entirely composed of 1,-1,0 entries, provided some numerical factors can be applied to the 4 branches at each node of the QMDD.

Results on practical real world quantum applications are impressive. For a 30 bit quantum circuit, a classic array-based solution would need a O(10¹⁸) sized matrix. Using QMDDs on two of the most famous quantum algorithms, Grover’s algorithm for database lookup and Shor’s algorithm for integer factorization, QMDDs are only O(10³) size. Simulation based on QMDDs can run these algorithms on 30 qubits in less than a minute on a 32GB desktop machine, where all other known methods have long since blown up. Nice!

Raúl’s view

As Paul explained above, quantum computer simulation on conventional computers inherently has exponential complexity. Most quantum simulation approaches prior to the paper we review this month relied on straightforward array-based representations of state vectors and matrices. For example, the paper we reviewed in December uses such an approach, simulating up to 20 qubits on a PC. Even using supercomputers with thousands of nodes and petabytes of distributed memory practical simulations historically remained limited to 50 qubits.

This month’s paper proposes a significantly improved graph-based simulation approach derived from Quantum Multiple-Valued Decision Diagrams (QMDDs), a representation inspired by BDDs (Binary Decision Diagram) and previously used successfully in logic synthesis and verification. The key insight is that many quantum state vectors and unitary matrices contain substantial internal regularity that can be captured through recursive decomposition and shared substructures. By introducing weighted edges and normalization schemes, the decision diagram compactly encodes sub-vectors and sub-matrices, yielding much smaller data structures for many practically relevant quantum computations.

The paper further describes efficient algorithms for the key operations required in quantum simulation, including Kronecker products, matrix-vector multiplication, and quantum measurement (which collapses superposition). Because the decomposition closely matches the recursive structure of quantum operators, many operations reduce to localized manipulations of the decision diagram rather than traversal of exponentially large arrays.

As with conventional decision diagrams, the worst-case complexity remains exponential: in the absence of exploitable redundancy, the representation degenerates into a full binary tree with 2ⁿnodes. However, for highly structured quantum circuits, the representation often grows only linearly with the number of qubits, allowing simulations far beyond the reach of array-based techniques.

Researchers had explored graph-based representations based on BDDs before, e.g. Quantum Information Decision Diagrams (QuIDDs), but Advanced Simulation of Quantum Computations is cited as foundational and reported greatly improved results. The simulator achieved Grover algorithm simulations with 40 qubits using only approximately 52 MB of memory, and Shor algorithm simulations with 37 qubits using about 260 MB, all on a small four-core desktop machine. Quantum Fourier Transform (QFT) circuits showed especially favorable scaling, with successful simulations up to 64 qubits.

To put this in context, Intel’s qHiPSTER simulator projected in 2016 that simulating 48–49 qubits would require between 4 and 10 petabytes of distributed memory. More recently, the Jülich Research Center reported a full simulation of a 50-qubit universal quantum computer in 2025 using approximately 2 petabytes of memory.

Subsequent research exploiting structural regularities in quantum circuits through these techniques has demonstrated near-linear scaling behavior for structured implementations of Shor’s and Grover’s algorithms, enabling simulations exceeding 100 qubits. More recently, researchers reported the factorization of the number 1011 using a 42-qubit simulation of Shor’s algorithm running for approximately five hours on a Windows laptop.

In the end, however, you can’t escape the fundamental exponential complexity of quantum computation relative to classical von Neumann machines. Advanced simulation techniques can significantly extend the practical limits of quantum simulation, making it a useful tool for the design, development, debugging, and verification of quantum algorithms and architectures — but not a replacement for the real thing. This is similar to simulation in EDA: indispensable for building complex systems, much slower than the hardware being modeled.

Also Read:

Quantum Gathering Momentum Amid Concerns for the Grid

PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026

Sensing. A Quantum Tech Ready for Market?

May 27, 2026May 27, 2026

SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability

SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
by Admin on 05-27-2026 at 10:00 am
Categories: Defacto Technologies, EDA
1 Comment

With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.

Indeed, for a complex SoC project, the number of possible configurations to evaluate can reach into the millions, with parameters that are deeply interdependent with objectives (power, performance, area, time-to-market) that are fundamentally in tension from one to another. Manual or semi manual design exploration, even when supported by experienced architects, remains highly complex.

Today we present the SoC PLANNER design solution which has reached the end of its R&D development stage after three years of collaborative work. SoC PLANNER addresses this gap. Funded by BPI France, SoC PLANNER provides a breakthrough design exploration solution which starts from the KPI and SoC design data to explore right to both RTL design implementation and design verification flows. These open new possibilities since it shortcuts many of the iterations between SoC design architects and both design implementation and design verification teams.

The SoC PLANNER R&D project brings together several technologies with complementary expertise from French research lab CEA, EDA software companies, Defacto Technologies and Innova Advanced Technologies. By integrating CEA’s A-DECA (Automated Design space Exploration for Computing Architectures), Defacto’s SoC Compiler, and Innova’s PDM (Project and Design Management) into a unified platform.

A-DECA allows automated exploration & optimization of computing architectures. SoC Compiler enables RTL generation and PDM, the management and planification of complex EDA flow. From automated design space exploration to the generation of the RTL ready for both logic synthesis and design verification, SoC PLANNER covers the full upstream pre-synthesis design chain, while uniquely considering an eco-design footprint score as part of the design exploration step. For large SoC design projects, the outcome is a measurable reduction in design cycles, resource consumption, and time to first silicon.

SoC PLANNER-based Design Exploration

The SoC PLANNER design solution is made simple and intuitive. A user simply provides design parameters, including the ranges to explore and the targeted KPIs. Also, a user can set up the various metrics and whether the priority is low power, performance, area efficiency, or a balanced trade-off between them. From there, the design exploration engine takes over autonomously, estimating area, performance (bandwidth, latency, etc.) and power across the configuration space, it generates automatically filtered configurations along with their corresponding RTL code, bridging the gap in a single, seamless flow between architectural exploration and design implementation in the SoC PLANNER platform. As a notable addition into the SoC PLANNER-based flow, to each design configuration an eco-design footprint score is assigned. To our knowledge, this metric is unique in the chip design space and can be also considered into the exploration strategy.

A first version of the SoC PLANNER solution is ready for validation by early adopters offering to design teams beyond PPA exploration the immediate access to sustainability-aware design configurations. In the following sections, SoC PLANNER flow is illustrated through two use cases: a low power subsystem for a deep neural network, and an HPC (High Performance Computing) SoC subsystem.

SoC PLANNER-based Design Exploration: Low Power Use Case

This use case focuses on PNeuro, a programmable and energy-efficient architecture for deep neural network (DNN) inference acceleration in embedded edge AI systems. The platform combines a host processor, shared memory, and a scalable multi-cluster accelerator composed of configurable Neural Compute Blocks (NCBs), enabling exploration of performance, power, energy, and silicon area trade-offs.

The architecture exposes a large design space including cluster organization, memory hierarchy, clocking, bandwidth, and memory access characteristics. These parameters are evaluated against key industrial metrics such as inference latency, power consumption, energy efficiency, and implementation area.

SoC PLANNER starts with the fully autonomous exploration, running multi-objective analysis across the entire parameter space to identify the Pareto-optimal configurations. The results consistently show configurations that cut latency and energy in tandem, keeping both dynamic and static power in check. The top-ranked configurations were then then automatically translated into RTL, ready for synthesis and simulation.

The automated flow provided a 30–40% reduction in exploration time compared to manual evaluation, which represents a significant productivity gain. Beyond time savings, the Pareto analysis gives design teams a structured view of the trade-off landscape, enabling KPI-driven selection rather than an experience-based design process.

SoC PLANNER-based Design Exploration: HPC Use Case

As a second validation, an HPC SoC is considered. The architecture is built on the top of a scalable network-on-chip connecting a variable number of CPUs with multiple peripheral IPs, including memory controllers and I/O interfaces. The design space contains hundreds of possible configurations, including parameters such as the number of cores, cache sizes, and external memory and controller settings. The objective is to identify the best trade-off configurations across various KPIs including throughput, latency, and power.

After the exploration, the Pareto front identified configurations that optimally balance the target KPIs within the defined constraints, clearly separating optimal solutions from non-viable ones across the search space. The best RTL configurations are then automatically generated.

One of the key outcomes of this use case is the significant gain in exploration efficiency and engineering productivity. While exhaustive manual evaluation of hundreds of configurations would require around 150 hours, SoC PLANNER identifies optimal solutions in less than 2 hours, achieving a 75× speedup.

The generated results were validated against existing industrial design flows, demonstrating both the accuracy of the KPI estimations and the relevance of the selected configurations.

In summary, SoC PLANNER offers a concrete answer to one of the industry’s most pressing challenges. For both use cases, SoC PLANNER delivers what traditional methodologies could not deliver: the ability to explore vast design spaces in much shorter time, leads to optimal configurations across conflicting objectives, and automatically produce RTL-ready outputs; all within a single, integrated flow.

Conclusion

Chip complexity is growing faster than the tools and teams, design costs at advanced nodes are climbing fast, and the window between architectural decision and silicon availability keeps compressing. Facing these challenges, incremental improvements to existing workflows are no longer enough. SoC PLANNER solution offers a concrete, validated response to these pressures. By unifying into a single flow design exploration engine, pre-synthesis, RTL generation tool, and eco-design scoring, it addresses key design selection challenges. The two presented use cases confirm a much faster design exploration and a direct path from KPIs to synthesis-ready RTL configurations.

This project is funded by BPI France and is part of the France 2030 program.

Also Read:

WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language

Defacto at the 2025 Design Automation Conference #62DAC

SoC Front-end Build and Assembly

May 27, 2026May 27, 2026

Engineering the Next Era of Semiconductor Innovation

Engineering the Next Era of Semiconductor Innovation
by Kalar Rajendiran on 05-27-2026 at 8:00 am
Categories: 3D IC, AI, Chiplet, EDA, Siemens EDA

The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens, NVIDIA, and Amazon Web Services described how engineering itself is being reshaped by AI-powered workflows and hyperscale infrastructure.

The conference highlighted a growing realization across the industry: semiconductor design is no longer just about building faster chips. It now requires engineers to think at the level of systems, software, physics, manufacturing, and even autonomous machines.

From Traditional EDA to System-Level Engineering

Opening the event, Jeff Applebaum reflected on how dramatically engineering has evolved over the past few decades. Early chip design relied heavily on manual processes and limited tooling. Today, engineers are working on designs that are exponentially more complex, while also facing pressure to deliver products faster than ever before.

That shift was expanded upon by Jean-Marie St. Paul, who emphasized that hardware innovation has once again become central to the technology industry. As AI workloads grow and advanced packaging technologies such as 3D ICs become mainstream, chip designers must now consider thermal behavior, mechanical stress, power delivery, and system-level integration alongside traditional logic and verification challenges.

According to Siemens, this is fundamentally changing the role of EDA. The future of semiconductor development extends beyond schematic capture and simulation into areas such as digital twins, thermal modeling, industrial automation, and mechanical simulation. Semiconductor devices are increasingly being designed as part of larger intelligent systems rather than standalone components.

Siemens positioned itself as uniquely suited to support this transition because of its broader industrial portfolio, which spans software, automation, manufacturing infrastructure, and simulation technologies. The company’s long-term strategy is to connect the entire product lifecycle from chip design all the way to factory deployment through integrated digital workflows.

AI Becomes an Engineering Platform

Artificial intelligence was the dominant theme of the conference, particularly during the keynote by Da Yang of NVIDIA. He described AI not simply as a productivity tool, but as the foundational infrastructure for the next industrial revolution.

NVIDIA’s vision centers on a layered AI ecosystem built on accelerated computing. At the infrastructure level are massive GPU-powered supercomputers designed to train and run AI models at unprecedented scale. On top of that sits a growing stack of CUDA libraries, frameworks, and domain-specific AI applications tailored to industries such as semiconductor design and manufacturing.

These technologies are already producing significant gains in EDA workflows. NVIDIA highlighted major acceleration in tasks such as SPICE simulation, optical proximity correction, and parasitic extraction. Workloads that previously consumed hours or even days can now be completed dramatically faster through GPU acceleration and AI-assisted optimization.

But the larger shift lies in how AI interacts with engineers. The industry is moving beyond generative AI into what NVIDIA described as “agentic AI”. Such agentic systems are capable of reasoning, planning, and autonomously executing engineering tasks.

Instead of simply responding to prompts, these AI agents can coordinate workflows, analyze results, optimize designs, and interact with multiple engineering tools with minimal human intervention. The goal is not to replace engineers, but to augment their productivity and allow them to focus on higher-level problem solving.

This evolution is already beginning to reshape EDA workflows. AI copilots embedded into engineering tools can help automate repetitive tasks, accelerate debugging, and improve decision-making throughout the design process.

From Digital Intelligence to Physical AI

NVIDIA also introduced its broader vision for “physical AI,” which extends artificial intelligence into the real world through robotics, factory automation, and intelligent infrastructure.

The concept relies heavily on digital twins and simulation environments. Engineers can train AI systems in virtual environments that accurately replicate physical systems before deploying those models into factories, robots, or industrial equipment.

This approach has major implications for semiconductor manufacturing. AI-driven systems could optimize production lines, identify defects in real time, improve process control, and automate large portions of fab operations. NVIDIA described this as the beginning of a new industrial era in which AI moves beyond software applications and becomes embedded into physical operations.

The partnership between NVIDIA and Siemens is central to this vision. By integrating NVIDIA’s AI frameworks and Omniverse simulation technologies into Siemens’ industrial and EDA platforms, the companies aim to create end-to-end workflows that connect chip design, simulation, manufacturing, and deployment.

The Rising Cost of Delay

While NVIDIA focused on AI and intelligent systems, Nafea Bshara from AWS’s Annapurna Labs addressed another major industry challenge: time-to-market.

Bshara argued that in the AI era, even a small delay in delivering a new chip generation can create enormous financial consequences. As AI hardware generations increasingly deliver 2× or greater performance improvements, infrastructure operators cannot afford to remain on older platforms for extended periods.

A single-quarter delay, he explained, can translate into billions of dollars in wasted capital expenditures, increased energy consumption, and reduced efficiency at hyperscale data center operators.

This pressure is forcing semiconductor companies to rethink how they develop chips. Traditional on-premises compute infrastructure often cannot scale quickly enough to support modern design workloads, especially during peak verification and signoff periods.

Why the Cloud Matters for EDA

AWS presented cloud infrastructure as a solution to these bottlenecks. The company described what it calls “speed-of-light” chip development, where engineering teams can instantly scale compute resources based on workload demands.

Rather than waiting for limited on-premises servers, engineers can launch thousands of cloud instances in minutes, dramatically reducing queuing delays and improving iteration speed.

AWS also emphasized the importance of optimizing EDA tools for distributed and parallel execution. Working closely with Siemens EDA, AWS has helped accelerate key workloads such as design rule checking and simulation across large-scale cloud environments.

The result is faster turnaround times, more engineering iterations per day, and shorter overall development cycles. According to AWS, this flexibility is especially important as chip complexity continues to rise and AI workloads demand ever-larger verification runs.

Bshara also challenged the perception that cloud computing is prohibitively expensive for semiconductor development. In many cases, cloud infrastructure represents only a small percentage of total design costs while providing significant productivity gains and faster time-to-market.

Redefining the Engineer’s Role

Despite the emphasis on automation and AI, the conference repeatedly reinforced the importance of human engineers. AI systems may accelerate workflows and automate tasks, but engineers remain responsible for defining problems, validating outcomes, and making critical architectural decisions.

What is changing is the nature of engineering work itself. Engineers are increasingly becoming orchestrators of intelligent systems rather than operators of isolated tools. Success now requires expertise that spans hardware, software, AI, cloud infrastructure, and system-level design.

The industry is also becoming more collaborative. Semiconductor innovation increasingly depends on partnerships between EDA vendors, cloud providers, AI companies, foundries, and system integrators. The keynote presentations from Siemens, NVIDIA, and AWS collectively underscored how interconnected the ecosystem has become.

Summary

The Siemens EDA User2User conference offered a clear view of where the semiconductor industry is headed. AI is becoming deeply integrated into engineering workflows. Cloud infrastructure is removing traditional compute limitations. Digital twins and simulation environments are connecting virtual models with physical systems. And intelligent automation is beginning to transform manufacturing itself.

The result is a new model of engineering that is faster, more connected, and increasingly autonomous.

For semiconductor companies, the challenge is no longer simply building better chips. It is learning how to operate within a rapidly evolving ecosystem where AI, cloud computing, and physical infrastructure are converging into a single intelligent platform for innovation.

Also Read:

Library Characterization gets a Boost from AI

Europe is Getting Serious About ASIC Innovation

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

May 27, 2026May 27, 2026

SRAM compilers targeting automotive SoCs on advanced nodes

SRAM compilers targeting automotive SoCs on advanced nodes
by Don Dingee on 05-27-2026 at 6:00 am
Categories: IP, Synopsys

Automotive versus consumer grade reliability

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close to where it is used and minimizing moves. With all this on-chip memory, advanced SRAM compilers can differentiate automotive SoCs, especially those implementing AI, which demand performance and reliability. A Synopsys white paper details the benefits of its SRAM compilers targeting automotive SoCs on 5nm and 3nm process nodes, describing the trends, challenges, and solutions.

More SRAM blocks are good, but too many can worsen automotive reliability

In traditional Von Neumann processor architectures, the solution to data latency has been cache memory, with up to three levels in large CPU-centric designs. A well-designed cache can prevent critical, frequently used data from facing competition for bandwidth on an already overcrowded bus. However, Von Neumann never met an AI application. AI models of more than trivial complexity don’t lend themselves to caching, with unique incoming frames of streaming data and unpredictable, potentially vast intermediate result sets as data sift through layers of weighting and summation.

For that matter, Von Neumann never met a car filled with electronic content, either. Automotive electronics are transforming. The traditional domain-based approach, in which a controller chip handles a specific function or a small set of functions, remains in use. A newer architecture is gaining momentum: zonal controllers, which are responsible for operations within a specific section of the car. In theory, zonal architectures can reduce wiring harness complexity and cost. However, zonal SoC complexity can increase, with combinations of CPUs, GPUs, I/O blocks, and, to handle AI tasks, neural processing units (NPUs).

Both domain-based and zonal architectures are pushing designers to adopt distributed SRAM within an SoC to simplify routing and bring data closer to the points of computation, enabling greater throughput. Distributing SRAM is crucial for AI implementations, where constantly moving intermediate results too far across a chip can become a performance bottleneck. Placing smaller SRAM chunks closer to small groups of multiply-accumulate units in AI accelerators, or polygon-processing cores in GPUs, improves performance.

According to Synopsys’ white paper, an advanced automotive SoC might have up to 50% of its area occupied by embedded SRAM, often with some concentrated and some distributed in smaller blocks. These sheer amounts of SRAM make power, performance, and area (PPA) optimization a high priority. Another side effect of large amounts of SRAM operating in harsh environmental conditions with relatively long target life is that defective parts per million (DPPM) standards quickly come into play, far more than in consumer electronics design.

Aggressive process nodes require sophisticated SRAM compilers

Another important trend in automotive SoCs is moving to more aggressive process nodes to handle increasing complexity, particularly in zonal architectures, but also applicable to domain-based architectures. TSMC offers its N5A process tuned for automotive needs at 5nm, and the latest N3A automotive process at 3nm for even higher automotive computational loads, including AI inference. These are advanced nodes just behind cutting-edge processes for benign-environment SoCs, with appropriate steps to help designers achieve automotive-level reliability and functional safety (FuSa) requirements while meeting PPA goals.

Synopsys supports both TSMC N5A and N3A automotive processes, with a portfolio of SRAM compilers that offer a wide array of memory functions. Which compiler(s) designers choose for an automotive project depends on specific goals, falling into several categories:

High-speed compilers using high-current bit cells for maximum performance
Ultra-high-density compilers using small-area, low-power bit cells
High-density compilers optimized for medium speed and power efficiency
Pseudo two-port architectures for further power and area reduction

Their white paper launches into a discussion of using these SRAM compilers to reduce leakage and dynamic power, using techniques such as dynamic voltage and frequency scaling (DVFS). Lower power directly translates to lower thermal dissipation and a corresponding improvement in long-term reliability. There are also customer stories, including one showing how eliminating a performance bottleneck through timing improvements achieved higher SRAM clock rates, and two that show improvements across all three dimensions of PPA.

Also in the white paper are specific steps to address ultra-low DPPM requirements with SRAM in TSMC N5A and N3A, and how Synopsys memory compilers provide an ASIL-D-ready solution for ISO 26262 certification. It’s a concise discussion with an encouraging message: design teams can move to advanced process nodes with confidence and use SRAM compilers to solve PPA issues they are likely to encounter in higher-complexity automotive SoC designs. To learn more, download the Synopsys white paper:

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs

Also Read:

The Great Divide: A Tale of Three Hardware Emulation Architectures

Synopsys and TSMC Deepen AI Design Alliance: What It Means

How to Overcome the Advanced Node Physical Verification Bottleneck

May 26, 2026May 27, 2026

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win

CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win
by Daniel Nenni on 05-26-2026 at 10:00 am
Categories: Ceva, IP

CEVA, the leading licensor of wireless connectivity and smart sensing technologies, is advancing its full-stack wireless strategy with the introduction of next-generation Bluetooth High Data Throughput (HDT) capabilities and a major integrated RF subsystem design win. The announcement underscores CEVA’s growing role in enabling highly integrated wireless SoCs for consumer, industrial, automotive, and IoT applications where performance, power efficiency, and silicon integration are becoming critical competitive differentiators.

Bluetooth technology is entering a new era as demand accelerates for higher bandwidth wireless audio, spatial computing, gaming peripherals, industrial edge devices, and AI-enabled wearables. While traditional Bluetooth Low Energy (BLE) has focused primarily on ultra-low-power communications, emerging applications increasingly require significantly higher throughput without sacrificing battery life. CEVA’s latest Bluetooth platform directly addresses this challenge through a scalable architecture that combines advanced baseband processing, optimized protocol stacks, and tightly integrated RF design.

At the center of CEVA’s strategy is support for Bluetooth High Data Throughput, an emerging capability designed to dramatically increase wireless data rates compared to conventional BLE implementations. HDT enables new classes of applications including lossless wireless audio, low-latency XR streaming, multi-stream sensor aggregation, and high-speed firmware updates. These use cases require not only enhanced PHY performance, but also intelligent coexistence management, adaptive scheduling, and advanced interference mitigation.

CEVA’s full-stack wireless approach integrates digital signal processing, modem IP, software protocol stacks, and RF subsystem technology into a unified platform. This architecture simplifies SoC development for semiconductor companies by reducing integration complexity and accelerating time-to-market. Rather than sourcing Bluetooth stack software, DSP cores, and RF IP from multiple vendors, customers can deploy a pre-validated CEVA platform optimized across all wireless layers.

A key aspect of the announcement is CEVA’s integrated RF design win, which validates the company’s strategy of moving beyond standalone IP licensing toward complete wireless subsystem solutions. Historically, many semiconductor companies have relied on discrete RF front-end development combined with externally sourced digital connectivity IP. However, advanced process nodes and increasingly compact device form factors are driving the need for deeper RF-digital co-optimization.

The integrated RF subsystem combines low-noise amplifiers, power amplifiers, frequency synthesizers, RF transceivers, and calibration technologies with CEVA’s Bluetooth baseband and software stack. This level of integration improves power efficiency, reduces board area, lowers BOM cost, and simplifies certification requirements. It also enables tighter control over RF performance metrics such as sensitivity, adjacent channel rejection, and coexistence with Wi-Fi and ultra-wideband radios.

The design win itself represents an important milestone because it demonstrates growing customer demand for turnkey connectivity platforms rather than isolated IP blocks. Semiconductor vendors targeting wearables, hearables, smart home devices, and industrial IoT products increasingly seek integrated wireless solutions that reduce engineering risk while enabling rapid product differentiation.

Bluetooth HDT is especially important for the wireless audio market, where higher-quality codecs and spatial audio experiences require more bandwidth than conventional Bluetooth architectures can efficiently deliver. CEVA’s platform supports advanced audio processing pipelines alongside optimized transport layers capable of sustaining higher throughput with deterministic latency. This is increasingly relevant as device makers compete to deliver premium audio experiences with lower power consumption.

Another important market driver is edge AI. Smart cameras, industrial sensors, and wearable health devices are generating significantly larger data streams that must be transmitted efficiently between devices and edge processors. Bluetooth HDT provides a compelling low-power alternative for short-range high-bandwidth communications, particularly in applications where Wi-Fi power consumption may be excessive.

From a technical perspective, CEVA’s expertise in DSP architectures gives the company a unique advantage in wireless connectivity. Signal integrity, channel equalization, interference suppression, and adaptive modulation all require substantial real-time processing capability. CEVA’s specialized DSP cores are optimized for these workloads while minimizing silicon area and energy consumption.

The company’s broader strategy aligns with an industry-wide shift toward platform-based semiconductor development. As wireless standards become more complex, OEMs and chipmakers increasingly prefer validated subsystem solutions that combine hardware, software, and RF technologies. This reduces integration cycles and allows engineering teams to focus on application-level innovation rather than low-level wireless implementation.

The integrated RF design win also highlights the importance of analog and mixed-signal expertise in next-generation wireless systems. While digital integration often receives the most attention, RF performance remains one of the most difficult challenges in advanced wireless SoCs. Variability across process nodes, antenna constraints, thermal considerations, and coexistence requirements all place pressure on RF subsystem design.

Bottom line: By combining Bluetooth HDT innovation with integrated RF technology, CEVA is positioning itself as a strategic enabler for the next generation of connected intelligent devices. As wireless applications continue evolving toward higher bandwidth, lower latency, and greater energy efficiency, semiconductor companies will increasingly require tightly integrated full-stack connectivity solutions. CEVA’s latest advancements demonstrate how the company is expanding beyond traditional IP licensing into comprehensive wireless platform enablement for the AI-driven edge computing era.

For more information, visit https://www.ceva-ip.com/product/ceva-waves-bluetooth/.

Also Read:

All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

Ceva IP: Powering the Era of Physical AI

May 26, 2026May 27, 2026

Trusted Convergence Governance: Preserving Admissibility Integrity Across Heterogeneous Semiconductor Systems

Trusted Convergence Governance: Preserving Admissibility Integrity Across Heterogeneous Semiconductor Systems
by Moh Kolb on 05-26-2026 at 8:00 am
Categories: 3D IC, Chiplet

As semiconductor systems evolve toward heterogeneous integration, chiplets, 2.5D and 3D packaging, distributed observability, runtime adaptation, Fleet Learning, and lifecycle convergence governance, the industry is entering a fundamentally new operational reality.

Convergence decisions are no longer driven only by pre-silicon simulation, static signoff, or isolated qualification criteria. Increasingly, they are influenced by operational evidence generated throughout the lifecycle of the system itself.

Telemetry, firmware traces, validation results, DFT infrastructure, workload behavior, qualification outputs, manufacturing data, and field operational evidence are no longer peripheral engineering artifacts. They are becoming active participants inside convergence governance.

This transition creates a major architectural challenge for advanced heterogeneous systems:

Convergence governance is only as trustworthy as the evidence allowed to participate in the convergence process.

Historically, the semiconductor industry has focused heavily on interoperability, observability, runtime telemetry, and operational adaptation. These efforts remain essential. However, increasingly coupled heterogeneous systems now require something more fundamental: trust continuity inside the convergence loop itself.

This is the role of Trusted Convergence Governance (TCG).

TCG preserves admissibility integrity, synchronization validity, provenance continuity, realization-state consistency, and causality traceability before operational evidence is allowed to influence convergence decisions.

Figure 1 illustrates TCG as a bounded admissibility gate between observable/interoperable data and convergence-authoritative evidence.

SEGA-AI™ is not positioned as another analytical layer. It is a deterministic realization-governance architecture for preserving convergence across the full lifecycle of high-performance heterogeneous computing systems.

Figure 1. Trusted Convergence Governance as a bounded admissibility gate between observable/interoperable data and admissible convergence evidence.

Interoperability Is Not Trust

One of the most dangerous assumptions in modern distributed engineering systems is the belief that interoperable data automatically becomes trustworthy convergence evidence.

It does not.

Interoperability guarantees that engineering data can move across tools, domains, systems, organizations, and lifecycle stages. But it does not guarantee that the resulting convergence decisions remain trustworthy.

A heterogeneous semiconductor system may successfully exchange telemetry, firmware traces, qualification outputs, runtime observability data, manufacturing evidence, and operational feedback while still lacking provenance continuity, synchronization integrity, realization-state validity, or causal traceability.

Under these conditions, the system may remain operationally connected while no longer remaining convergence-authoritative.

This distinction becomes increasingly important because operational evidence now directly influences runtime intervention, firmware adaptation, Fleet Learning, convergence refinement, realization assumptions, and future closure criteria.

The challenge is therefore no longer simply data movement.

The challenge is trust-preserved convergence governance.

The Need for Bounded Admissibility

Traditional telemetry architectures often assume that all operational data is useful. Within the SEGA-AI™ framework, however, operational evidence must pass through bounded admissibility governance before participating in convergence decisions.

The purpose is not to block data. The purpose is to qualify whether the data has the authority to influence convergence.

A separate evidence-maturity model can classify how data progresses toward decision authority. However, the focus of Trusted Convergence Governance is the trust mechanism itself: preserving provenance, synchronization, realization-state validity, causality, fidelity, and chain of custody before evidence is allowed to affect convergence closure.

In this model, admissible evidence is not simply observable telemetry.

It is operational or engineering evidence that satisfies bounded governance criteria, including:

provenance continuity
synchronization integrity
realization-state validity
measurement fidelity
causal relevance
chain-of-custody preservation
bounded authority for decision use

Evidence that fails these checks may still be useful for monitoring, debugging, or exploratory analysis. But it should not automatically become convergence-authoritative.

This distinction matters because operational perturbations may propagate recursively across firmware behavior, thermal behavior, runtime scheduling, SI/PI stability, System EM Corridor behavior, package mechanics, and distributed synchronization environments.

A corrupted, stale, desynchronized, or non-admissible evidence stream may influence convergence decisions incorrectly while remaining fully interoperable.

The result is a dangerous condition in which systems remain connected while no longer preserving trustworthy convergence states.

TCG Is Not Generic Cybersecurity

Trusted Convergence Governance should not be confused with generic cybersecurity enforcement.

Cybersecurity protects systems against unauthorized access, tampering, intrusion, and attack. Those protections are essential, but they are not sufficient for convergence governance.

TCG addresses a different question:

Is this evidence trustworthy enough, synchronized enough, realization-consistent enough, and causally valid enough to influence convergence decisions?

A data stream may be secure but still non-admissible.

It may come from an authorized source but be temporally stale.

It may be complete but synchronized to the wrong runtime epoch.

It may be statistically correlated but physically non-causal.

It may be valid in one realization state but invalid after firmware intervention, package drift, workload migration, thermal excursion, or manufacturing variation.

TCG therefore extends governance beyond access control and data transport. It protects the decision integrity of the convergence loop.

Cryptographic signatures or hardware roots of trust may support evidence chain of custody, but the core TCG function is broader: determining whether evidence is synchronized, realization-consistent, causally valid, and admissible for a specific convergence decision.

Realization-State Consistency

One of the most important elements of TCG is realization-state consistency.

In advanced heterogeneous systems, evidence does not exist in isolation. It belongs to a specific realization state: a particular configuration of die, package, interposer, substrate, board, firmware, workload, thermal condition, voltage condition, manufacturing history, aging profile, and system operating mode.

If evidence loses this context, its decision authority becomes compromised.

For example, telemetry collected during one workload regime may not remain valid after workload migration. Thermal behavior measured under one cooling condition may not remain valid under a different rack environment. SI/PI behavior observed before firmware adaptation may not remain valid after runtime policy changes. Package stress data from one assembly configuration may not remain valid after material, substrate, or underfill variation.

This is why convergence governance cannot rely only on data availability.

It must preserve the realization context in which the evidence was generated.

TCG ensures that operational evidence remains tied to the correct system state before it influences convergence decisions.

Causality Before Pattern Recognition

As AI-assisted operational systems continue scaling, another critical distinction emerges.

Pattern recognition alone does not guarantee convergence validity.

A system may identify statistical correlations, anomaly signatures, behavioral clusters, or workload patterns while still lacking physics-grounded causality continuity, realization-state admissibility, or convergence-authoritative evidence.

SEGA-AI™ therefore prioritizes physics-grounded causality preservation over isolated statistical pattern matching.

This distinction becomes increasingly important because heterogeneous convergence behavior now emerges from tightly coupled physical interactions involving thermal-current propagation, package deformation, System EM Corridor behavior, runtime scheduling, firmware intervention, PDN behavior, synchronization continuity, and manufacturing variation.

A causality matrix generated from non-admissible evidence may remain mathematically coherent while becoming physically invalid.

For example, a statistical correlation may attribute a localized voltage drop to a firmware workload pattern. A physics-grounded causality review may instead show that the event was driven by transient thermal deformation, localized package-stress shift, and a resulting change in the effective power-delivery path. In that case, the statistical pattern is not wrong as an observation, but it is incomplete as convergence evidence.

This is why TCG does not ask only whether a pattern is detectable.

It asks whether the evidence behind that pattern is admissible, synchronized, realization-consistent, and physically causal enough to influence convergence decisions.

The objective is not only to detect what happened.

The objective is to determine whether the evidence is trustworthy enough to explain why it happened, whether that explanation is valid in the current realization state, and whether it can safely influence future convergence decisions.

Fleet Learning Requires Trust-Preserved Feedback

Fleet Learning introduces another major governance challenge.

In the SEGA-AI™ framework, Fleet Learning is not merely analytics. It is a governed realization-feedback mechanism through which operational evidence refines convergence assumptions, realization constraints, firmware policies, admissibility boundaries, runtime governance logic, and future closure criteria.

This creates a recursive governance problem:

Who validates the validator?

If convergence refinement depends on operational evidence, then the evidence used for refinement must itself remain governed.

Runtime telemetry may become desynchronized. Firmware policies may diverge. Workload traces may lose causal context. Distributed observability environments may become incomplete. Manufacturing records may become disconnected from field behavior. Qualification assumptions may drift away from real operating conditions.

Under these conditions, Fleet Learning may begin refining convergence assumptions using non-admissible evidence.

The result is not simply inaccurate telemetry.

The result becomes convergence drift driven by non-authoritative operational evidence.

Trusted Convergence Governance prevents this by ensuring that Fleet Learning remains bounded, traceable, admissibility-preserving, causality-grounded, synchronization-valid, and operationally trustworthy.

The Operational Role of TCG

The semiconductor industry has spent years solving interoperability and data-continuity challenges across fragmented engineering ecosystems. Those efforts remain necessary and valuable.

However, interoperability alone cannot guarantee trustworthy convergence, convergence-authoritative operational states, admissibility-preserved refinement, or deterministic lifecycle governance.

The next operational layer above interoperability is Trusted Convergence Governance.

TCG ensures that operational evidence, runtime observability, firmware traces, DFT infrastructure, qualification data, manufacturing records, and Fleet Learning inputs remain provenance-preserved, synchronization-valid, realization-consistent, causality-grounded, and admissibility-qualified before they influence convergence decisions.

Within SEGA-AI™, TCG can be implemented through bounded validation gates that combine provenance records, realization-state identifiers, synchronization epochs, chain-of-custody checks, physics-consistency tests, admissibility thresholds, and gate-authority rules before evidence is allowed to influence convergence decisions.

In practical terms, TCG introduces a trust gate between observable data and convergence authority.

That gate asks:

Where did this evidence come from?
Is its provenance preserved?
Is it synchronized to the correct system state?
Is it tied to the correct realization configuration?
Is the evidence physically causal or only statistically correlated?
Is the chain of custody intact?
Is the evidence fresh enough to influence this decision?
Does the evidence have bounded authority for this type of intervention or refinement?

Only after satisfying these conditions should operational evidence be allowed to participate in convergence closure, runtime intervention, Fleet Learning refinement, or lifecycle governance.

Conclusion

Trusted Convergence Governance addresses a fundamental gap in advanced semiconductor systems.

The industry can no longer assume that observable data is trustworthy, that interoperable data is admissible, or that connected telemetry is convergence-authoritative.

As AI infrastructure, chiplets, 2.5D and 3D integration, advanced packaging, firmware adaptation, and fleet-scale operation continue to converge, the integrity of the evidence loop becomes as important as the integrity of the physical system itself.

TCG preserves that evidence loop.

It ensures that operational evidence remains provenance-preserved, synchronization-valid, realization-consistent, causality-grounded, and admissibility-qualified before it influences convergence decisions.

Ultimately, deterministic convergence depends not only on evidence continuity, but on admissibility integrity across the complete realization ecosystem.

Also Read:

Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)

Beyond Tool Interoperability: The Emerging Governed Convergence Problem in Semiconductor Design

Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance

May 26, 2026May 27, 2026

Are You Ready for Spec-Driven Verification?

Are You Ready for Spec-Driven Verification?
by Bernard Murphy on 05-26-2026 at 6:00 am
Categories: AI, EDA, Moores Lab (AI)

Quick recap: verification is checking that your implementation of a design matches the in-house design/test specification. In contrast, validation means checking that the implementation matches design intent as defined by a customer specification, use cases, etc. Let’s focus on verification; for simplicity I’ll use “design specification” as a proxy for both design and test. This spec is developed by an in-house architect who reads the customer spec, maybe augmented by discussion with customers and/or application engineers, and translates it into a representation more closely aligned with in-house platforms, IP and expertise. Most often this will be one or more PDF documents with descriptions of objectives, tables, block diagrams, timing diagrams, state machine diagrams, register maps, and often explicit or implicit references to other documents. Verification teams read this document to guide building their verification collateral.

This mapping from human understanding to tests is neither a one-time step nor error-free. Customer requirements evolve, architect understanding evolves and human reading of requirements, from architect to implementation to verifier teams, all present multiple opportunities for misinterpretation. Can automating spec interpretation, through agentic processing, mitigate these problems? Yes, if handled carefully.

Systematically eliminating interpretation errors

Analysis must start with a detailed knowledge base built on an understanding of the spec – likely represented by more than one document. In an ideal spec-driven flow, a design team should be able to upload PDFs, timing and block diagrams, protocol standard specs and design collateral. From this a spec-driven verification system should build a robust knowledge base from which it can generate test collateral.

That collateral should include a readable test plan, progressing from basic tests, to bring up tests, to stress tests, to complex feature coverage. These should particularly stress bug-prone areas, for example recent design updates as detected in RTL commit info. Together with the test plan it should generate a testbench architecture and full UVM testbenches, including UVM agents, clocks and resets, with appropriate monitors, drivers, memory models, coverage properties and scoreboard reference models as required by the spec.

You should be able to see, side by side with a generated test objective, a more detailed breakdown of how the the verification agent intends to implement that test. I have emphasized before the importance of building trust in agentic systems, an essential characteristic in any worthwhile verification flow. If you notice a mistake, you should be able to correct that mistake and have the system learn from that correction.

Regression tests then should provide an at-a-glance summary of any failures, triage clustering, automated root cause analysis and localization to RTL, testbench or spec errors. When a coverage point is claimed, you want to see the corresponding pages in the spec, again building trust that the system truly understood the objective. Also with opportunity to correct mistakes.

What if the spec is wrong?

A systematic approach to verification must consider the possibility of errors in any phase of this pipeline, from spec to design to verification. What might spec problems look like? There could be inconsistencies within the spec itself, or between the spec and the design. There may also be ambiguities in the spec which could lead to more than one possible implementation in the design, or multiple possible test implementations. These should be detected and corrected (by you) up front. Another possibility is holes in the spec – behavior implicit in how functionality is defined but not specified in detail. I’m not sure yet how these might be handled.

MooresLab at DAC2026

I have written about MooresLab before, a fairly new venture founded by design alumni from Microsoft. They have been busy advancing their MooreIP full-stack AI platform: a verification agent (VerifAgent™), a signoff agent, a debug agent, a coverage agent, along with planned spec agent and design agent components. In my most recent discussion with Shelly Henry (CEO of MooresLab). I was favorably impressed not only by the range of features covered in this agentic tool suite but also by the level of investment in methods to build user trust. A consideration which I think will separate the leaders from the also-rans in this space.

On the spec agent, remember the live newspapers in the Harry Potter series? Imagine specs with similar dynamic graphics!

Well worth checking MooresLab at booth #826 in this year’s Long Beach DAC. In the meantime, you can get more background HERE.

Also Read:

CEO Interview with Dave Kelf, CEO of Breker Verification Systems

2026 Outlook with Shelly Henry of MooresLabAI

We Need to Turn Specs into Oracles for Agentic Verification

May 25, 2026May 27, 2026

TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade

TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade
by Daniel Nenni on 05-25-2026 at 10:00 am
Categories: Foundries, TSMC

TSMC’s Lithium Iron Battery Generation Upgrade Project

As semiconductor manufacturing becomes increasingly dependent on uninterrupted power and energy efficiency, battery reliability has emerged as a critical operational issue for advanced fabs. Taiwan Semiconductor Manufacturing Company, better known as TSMC, is addressing this challenge through an ambitious global initiative called the “Lithium Iron Battery Generation Upgrade Project.” The program represents one of the semiconductor industry’s most comprehensive battery modernization efforts, covering approximately 408,000 lithium iron phosphate batteries installed across the company’s domestic and international fabrication facilities.

The project is designed to improve both operational resilience and environmental safety. TSMC has been gradually replacing traditional lead-acid batteries in uninterruptible power supply systems with lithium iron batteries because of their higher efficiency, longer lifecycle, and lower environmental impact. The transition also supports the company’s broader sustainability goals, including reduced electricity consumption and lower carbon emissions. Earlier initiatives using LFP batteries reportedly enabled annual electricity savings of approximately 17.1 million kilowatt-hours.

TSMC’s battery upgrade journey has unfolded in several stages. The company first introduced first-generation lithium iron batteries in 2017 after conducting extensive in-fab production verification. These systems primarily monitored battery voltage through sampling boards to maintain safe operation. In 2018, TSMC adopted second-generation systems in response to the International Electrotechnical Commission’s IEC 62619 safety standards for industrial lithium battery applications. The upgraded Battery Management System (BMS) added monitoring capabilities for temperature, state of charge, and battery health, enabling improved operational oversight.

The real transformation began in 2019 when TSMC started developing third-generation lithium iron battery systems with suppliers and technical experts. These new systems significantly expanded monitoring functionality by adding real-time current tracking and integrating directly with the fab’s Supervisory Control and Data Acquisition infrastructure. Through this integration, battery data can be transmitted continuously to centralized monitoring platforms for remote diagnostics and predictive analysis.

The third-generation BMS can precisely monitor critical battery parameters, including voltage, current, temperature, state of charge, and state of health. According to TSMC, the system can immediately identify abnormal operating conditions and pinpoint fault locations, improving emergency response efficiency by approximately 25 percent. In high-volume semiconductor manufacturing environments, where even a brief power disruption can affect wafer production worth millions of dollars, this level of visibility and rapid response capability is especially important.

Safety validation has become another cornerstone of the project. In 2024, TSMC conducted thermal runaway experiments on lithium iron batteries to evaluate battery behavior under extreme conditions and verify the effectiveness of BMS protection mechanisms. Thermal runaway is one of the primary safety concerns associated with large-scale battery systems because overheating in a single cell can potentially trigger cascading failures. By performing controlled testing, TSMC aimed to confirm that its upgraded systems could prevent hazardous events and maintain stable operations in demanding industrial settings.

By the first quarter of 2026, TSMC had fully upgraded all first- and second-generation lithium iron battery management systems to the third-generation standard across its facilities. The company is also deploying an additional layer of protection through lithium iron battery breaker interlocking trip devices. These devices are designed to automatically disconnect power when the BMS detects abnormalities, minimizing the risk of equipment damage or fire-related incidents. Installation of the trip devices is expected to be completed by 2027.

The significance of the project extends beyond battery management. Semiconductor fabs are among the world’s most energy-intensive manufacturing environments, and ensuring reliable power infrastructure is increasingly important as AI-related chip production expands globally. TSMC’s investment in advanced UPS battery systems aligns with its larger environmental and operational strategy, including commitments to renewable energy adoption and sustainable manufacturing practices.

The “Lithium Iron Battery Generation Upgrade Project” illustrates how advanced manufacturing companies are beginning to treat energy storage systems not merely as backup infrastructure, but as intelligent, networked safety platforms. By combining advanced battery chemistry, real-time analytics, SCADA integration, and automated protection mechanisms, TSMC is setting a new benchmark for operational safety and energy resilience in semiconductor manufacturing. As fabs become larger, more automated, and increasingly dependent on uninterrupted power, projects like this may become standard practice across the global semiconductor industry.

Also Read:

ASML High-NA EUV is Not Ready for High-Volume Production

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling

May 25, 2026May 27, 2026

Library Characterization gets a Boost from AI

Library Characterization gets a Boost from AI
by Daniel Payne on 05-25-2026 at 8:00 am
Categories: EDA, Siemens EDA

The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized .lib models for everything from standard cells to complex memories, however using the traditional brute-force SPICE approach is taking too much time. Engineers are facing characterization cycles that stretch into weeks, consumed by the massive simulation demands of Liberty Variation Format (LVF) and the need to characterize over hundreds of PVT corners.

Siemens EDA recently addressed this challenge with the expansion of its Solido Characterization Suite, introducing AI-powered tools designed to accelerate the library lifecycle from generation to validation. The era of manual, schedule-volatile characterization is ending, replaced by generative and agentic AI workflows.

At the heart of the suite is the new Solido Characterizer. For foundries and design teams, the goal is to provide faster throughput without sacrificing SPICE-level accuracy. Siemens has achieved a 7x greater throughput by combining two critical innovations: an AI-driven characterization engine and the industry’s first purpose-built library simulator, Solido LibSPICE.

Solido LibSPICE provides a 2x+ performance boost by optimizing simulations specifically for library IP. When paired with the suite’s advanced LVF techniques that achieve a 5x speedup on their own, the result is a reduction in the simulation phase of characterization. Early adopters like GlobalFoundries have already noted that the tool maintains production accuracy while enabling speedups within internal flows.

While Characterizer handles the initial SPICE-backed circuit simulations, Solido Generator is where the scale happens. Generator uses machine learning to build an analytical model of a library based on “anchor” PVT corners. Once the model is trained, it can produce new PVT .libs in just minutes, performing at speeds 100x+ faster than SPICE.

This is a new methodology for multi-corner libraries. Instead of running SPICE for every single voltage and temperature variation, Generator uses reinforcement learning to adaptively model the space, boosting accuracy where it’s most critical while saving simulation time elsewhere. It supports all standard data structures, including NLDM, CCS, and LVF, ensuring that the AI-generated models are signoff-ready.

Speed is not helpful if the data is flawed, and at advanced nodes, errors can be increasingly subtle. Solido Analytics replaces the multi-week manual verification process with an AI outlier detection engine that can validate a library in just a few hours.

Traditional rule-based checks often miss spikes or noise results in LVF data, which can impact timing by 100% or more at 3nm. Solido Analytics uses advanced information visualization and automated analysis to find issues undetectable by traditional methods. It even allows engineers to visualize LVF moments, like standard deviation and skewness through probability density functions and normal quantile plots, making complex statistical data much more intuitive.

Solido Analytics

The suite isn’t just for the characterization teams, it’s also for the IP users. The Solido Library Profiler allows physical design teams to perform PPA (Power, Performance, Area) comparisons across different libraries early in the flow, so your team can choose the best library.

Solido Library Profiler

Selecting the right IP can require running multiple iterative cycles of synthesis and Place & Route (P&R), which is incredibly resource-intensive. Library Profiler uses smart auto-alignment to map differences down to the pin and arc level, allowing teams to choose the optimal library before they ever kick off an STA run. This effectively eliminates a major bottleneck in the early design phase.

The most powerful development is the integration of the Fuse EDA AI system, which brings generative and agentic AI capabilities to the suite. This allows for a more live debugging experience, where the software can pinpoint issues, monitor in-progress runs, and even suggest informed re-runs to maximize productivity.

Moving toward even more complex modeling standards, the Solido Characterization Suite provides a scalable, cloud-ready framework that is capable of running on tens of thousands of CPUs in order to meet the project schedule. This shift to AI-driven characterization isn’t just a luxury, it’s a necessary methodology to keep the semiconductor roadmap on track.

Summary

There’s a better way to perform library characterization using AI techniques from Siemens called the Solido Characterizer, promising faster characterization times while preserving accuracy. Your teams can build and deliver LVF libraries in record time using statistical characterization that reduces the number of required simulations. Generator techniques create portions of the library with AI, instead of using full SPICE characterization, while keeping SPICE in the loop.

The new Solido LibSPICE simulator is optimized for characterization, providing a 2x speed up. Debugging of Liberty files becomes more productive using Solido Analytics. Running characterization in the cloud with AWS and Azure provide the scale to meet your schedules.

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May 25, 2026May 29, 2026

Power-SOI: The Reliability Engine Behind Functional Safety ICs

Power-SOI: The Reliability Engine Behind Functional Safety ICs
by Daniel Nenni on 05-25-2026 at 6:00 am
Categories: Foundries, Soitec

Power-SOI technology is rapidly emerging as a foundational platform for next-generation functional safety integrated circuits used in autonomous vehicles, industrial automation, humanoid robotics, and other mission-critical systems. The growing convergence of high-voltage power management and low-voltage digital intelligence has created new reliability challenges that conventional bulk silicon BCD technologies increasingly struggle to address. As systems move toward higher levels of autonomy and electrification, semiconductor reliability is becoming directly tied to human safety, making the underlying process technology strategically important.

Modern safety-critical electronics operate under rigorous functional safety standards such as ISO 26262 for automotive systems and IEC 61508 for industrial applications. These standards require extremely low hardware failure rates, often below 10 FIT (Failures In Time), particularly for ASIL-D and SIL-4 systems. Achieving these metrics becomes exceptionally difficult when power management ICs are exposed to high temperatures, electromagnetic interference, voltage transients, and radiation-induced disturbances. Traditional bulk BCD technologies rely on junction isolation, where parasitic bipolar structures inherently exist within the silicon substrate. These parasitic elements introduce risks such as latch-up, leakage current, substrate noise coupling, and thermal instability.

The primary advantage of Power-SOI lies in its use of dielectric isolation through a buried oxide (BOX) layer combined with Deep Trench Isolation (DTI). This architecture physically separates active devices into isolated silicon islands, fundamentally changing the reliability behavior of the integrated circuit. Unlike bulk silicon, where devices share a conductive substrate, SOI eliminates most parasitic current paths that contribute to catastrophic failures.

One of the most significant benefits of Power-SOI is intrinsic latch-up immunity. In conventional CMOS or bulk BCD structures, parasitic p-n-p-n thyristor structures can be triggered by transient currents or voltage spikes, causing destructive short circuits between supply rails. In safety-critical automotive or robotics applications, such latch-up events can lead to loss of control, thermal runaway, or permanent device destruction. Power-SOI eliminates the physical conditions required for latch-up because the BOX layer blocks vertical current flow while DTI suppresses lateral carrier injection. As a result, latch-up can effectively be removed from the FMEDA analysis, directly improving system FIT calculations and simplifying safety certification.

Another major reliability improvement comes from superior high-temperature operation. In power electronics for EVs, robotics, and industrial drives, junction temperatures commonly exceed 150°C. Bulk silicon leakage currents rise exponentially at elevated temperatures due to minority carrier diffusion within the substrate, potentially causing analog drift, thermal instability, or false safety triggers. Power-SOI minimizes substrate leakage because the BOX layer isolates the active devices from the silicon handle wafer. Leakage currents are dramatically reduced, allowing precision analog circuits such as voltage monitors, ADCs, watchdogs, and bandgap references to maintain accuracy under extreme thermal stress.

Power-SOI also delivers substantial improvements in electromagnetic interference immunity and transient robustness. High-speed switching converters and motor drives generate severe voltage ringing and negative transients during operation. In bulk technologies, these transients can forward-bias isolation junctions, injecting minority carriers into the substrate and corrupting nearby digital logic. The dielectric isolation of SOI prevents this carrier propagation, enabling robust operation even under negative switching transients exceeding -50V. This isolation is particularly important in integrated motor drives and GaN-based power stages, where switching speeds continue to increase dramatically.

In humanoid robotics and collaborative automation systems, Power-SOI enables compact, high-density smart joint architectures that combine motor drives, sensing, and AI processing into a single module. These applications demand high current capability, low noise sensitivity, and guaranteed safe torque-off functionality. The ability of Power-SOI to isolate precision analog sensing circuits from noisy PWM switching stages significantly improves force sensing accuracy and collision detection response times. Additionally, the reduced soft error susceptibility of SOI enhances the reliability of embedded AI accelerators and local neural network processing within robotic actuators.

Bottom line: The technology roadmap for Power-SOI continues to advance rapidly, with process nodes scaling from 180nm toward 65nm and below while transitioning from 200mm to 300mm wafer manufacturing. This scaling enables higher digital integration, embedded safety processors, advanced diagnostics, and monolithic integration of wide-bandgap technologies such as GaN. As autonomous systems become more sophisticated and safety requirements become stricter, Power-SOI is increasingly viewed not merely as an alternative semiconductor technology, but as a strategic enabler for future fail-operational electronics platforms.

Get Whitepaper Here

Also Read:

Apple’s iPhone 17 Series 5G mmWave Antenna Module Revealed to be Powered by Soitec FD-SOI Substrates

Podcast EP331: Soitec’s Broad Impact on Quantum Computing and More with Dr. Christophe Maleville

Podcast EP321: An Overview of Soitec’s Worldwide Leadership in Engineered Substrates with Steve Babureck