SemiWiki – Page 3 – The Open Forum for Semiconductor Professionals

June 18, 2026June 16, 2026

Feed Forward Intelligence: Enabling Testability in the Chiplets Era

Feed Forward Intelligence: Enabling Testability in the Chiplets Era
by Kalar Rajendiran on 06-18-2026 at 6:00 am
Categories: AI, Chiplet, EDA, PDF Solutions

The semiconductor industry is entering a new era in which advanced packaging and chiplets-based architectures are becoming the primary drivers of system-level innovation. As traditional process-node scaling becomes increasingly complex and expensive, manufacturers are turning to heterogeneous integration, combining multiple dies within a single package to deliver higher performance, lower power consumption, and greater design flexibility.

This architectural shift is transforming semiconductor test.

Compared to traditional monolithic devices, chiplets-based products generate much larger volumes of data across multiple manufacturing and test stages, including wafer fabrication, wafer sort, assembly, package test, final test, and system-level validation. Each stage produces information that can influence downstream decisions. Yet in many manufacturing environments, that information remains trapped within the operation that generated it.

As advanced packaging grows in complexity and chiplets-based architectures become common, the challenge is no longer simply collecting data. It is making that data available where and when it can improve manufacturing outcomes.

This is where PDF Solutions believes the industry needs a new approach: Data Feed Forward (DFF).

The Need for Data Feed Forward

Chiplets-based manufacturing introduces more dies, more interfaces, more test insertions, and more opportunities for variation. Decisions made during wafer sort can affect assembly outcomes. Assembly choices can influence package test results. Information gathered early in the flow may be critical to optimizing downstream operations.

At the same time, semiconductor manufacturing is increasingly distributed across a global ecosystem of foundries, OSATs, integrated device manufacturers, and OEMs. Data generated at one site often does not follow the product to the next stage of production.

The result is a fragmented environment in which valuable intelligence remains isolated in local databases and AI models operate with only a partial view of device history.

PDF Solutions addresses this challenge through its Data Feed Forward (DFF) architecture. DFF is designed to collect, transform, transport, and apply manufacturing and test information throughout the semiconductor supply chain. Rather than treating each test insertion as an isolated event, it enables intelligence generated upstream to be used in downstream decisions, even when those decisions occur at different facilities or organizations.

The goal is straightforward: turn upstream test results into downstream process intelligence.

Operationalizing AI Across the Manufacturing Flow

DFF is more than a data movement framework. It is an operational infrastructure for deploying AI-driven test methodologies at scale.

The process begins by collecting manufacturing and test data from production operations. That information is then transformed into actionable intelligence through analytics, feature engineering, business rules, or machine-learning models. Predictions and recommendations are securely transported to the next point of use and applied directly to manufacturing and test decisions.

Most importantly, outcomes are written back into the system, creating a closed-loop environment for traceability, model validation, and continuous improvement. This write-back capability allows manufacturers to compare predictions with actual outcomes, refine models over time, and continuously improve operational performance.

The result is an infrastructure that moves AI from experimentation into production.

Exensio as the Foundation

Central to this approach are PDF Solutions’ products Exensio® Test Operations and Exensio® StudioAI.

Exensio Test Operations provides the operational foundation for collecting, monitoring, controlling, and optimizing semiconductor test processes in real time. By ingesting data from test and manufacturing equipment across multiple sites, the platform creates a trusted repository of information that supports feed-forward intelligence throughout the production flow.

Exensio StudioAI extends these capabilities through what PDF Solutions describes as ModelOps for Test. The platform enables data scientists and engineers to train, validate, deploy, govern, and continuously improve machine-learning models using manufacturing data collected throughout the supply chain. Whether customers use open-source algorithms or their own proprietary models, StudioAI provides a framework for operational deployment and lifecycle management.

Together, the two platforms create the infrastructure required to operationalize AI within semiconductor test environments.

From Lot-Level Decisions to Per-Device Intelligence

One of the most significant outcomes of DFF is the ability to make decisions at the individual device level.

Historically, many manufacturing decisions were based on aggregate information from lots or wafers. Feed-forward intelligence enables manufacturers to evaluate each device according to its unique manufacturing history and predicted behavior.

This creates opportunities to optimize testing, quality screening, and product configuration. Test coverage can be adjusted based on predicted risk. Devices can be graded according to expected performance. Burn-in resources can be allocated selectively rather than uniformly. AI models can predict trim targets before execution, helping prevent costly errors and improving process control.

The objective is simple but powerful: apply the right test to the right device at the right time.

Benefits Across Efficiency, Quality, and Performance

The value of DFF can be viewed through three lenses: efficiency, quality, and performance.

From an efficiency standpoint, feed-forward intelligence enables manufacturers to reduce redundant testing, optimize coverage, and lower test costs. Predictive burn-in is a particularly compelling example. By analyzing upstream manufacturing and test data, AI models can identify devices likely to pass burn-in, devices likely to fail, and devices that genuinely require additional screening. This improves resource utilization while maintaining quality objectives.

Quality benefits arise from connecting information across the production flow. Predictive trim targeting, drift detection, and improved visibility across manufacturing sites allow engineers to identify issues earlier and respond more quickly. In increasingly distributed supply chains, DFF helps ensure that quality becomes a coordinated, end-to-end process rather than a series of isolated inspections.

Performance improvements stem from richer and more contextual AI models. By combining signals from wafer fabrication, wafer sort, assembly, package test, and final test, manufacturers can create more accurate predictions than would be possible from any single insertion. This cross-stage signal fusion supports advanced applications such as package grading, assembly optimization, adaptive test strategies, and real-time AI inference at the tester.

Building the Future of Semiconductor Test

As advanced packaging continues to reshape the semiconductor industry, competitive advantage will increasingly depend on the ability to operationalize intelligence across the manufacturing ecosystem. The challenge is no longer collecting more data. It is ensuring that information generated anywhere in the supply chain can influence decisions everywhere it matters.

PDF Solutions’ Data Feed Forward architecture, together with Exensio Test Operations and Exensio StudioAI, is designed to provide the operational backbone for this new generation of AI-driven test methodologies. By connecting manufacturing intelligence across sites, organizations, and test insertions, DFF enables semiconductor companies to improve efficiency, enhance quality, and optimize performance in increasingly complex chiplets-based systems.

In the advanced packaging era, the winners will not simply be the organizations that collect the most data. They will be the ones that can transform that data into actionable intelligence and feed it forward throughout the lifecycle of every device.

Learn more at

Exensio Test Operations

Exensio StudioAI

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June 17, 2026June 25, 2026

Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions

Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions
by Daniel Nenni on 06-17-2026 at 2:00 pm
Categories: 3D IC, Chiplet, EDA, Synopsys

Synopsys Announces Availability of the First Wave of Multiphysics Fusion Solutions

Market Leaders Including Cisco, MediaTek, NVIDIA, and Samsung Foundry Demonstrate Measurable Impact, Advancing the Shift from Overdesign to Co-design

Synopsys has announced the availability of the first wave of its Multiphysics Fusion Solutions, extending its vision of a unified engineering environment that connects EDA, semiconductor physics, system simulation, and artificial intelligence-driven optimization. The announcement addresses one of the most significant challenges facing advanced semiconductor and system design: accurately modeling the interaction of electrical, thermal, mechanical, optical, and electromagnetic effects across increasingly complex products.

As semiconductor technologies advance into the angstrom era and heterogeneous integration becomes mainstream, traditional design methodologies are reaching their limits. Modern chips are no longer isolated electronic devices. They operate within highly integrated systems that include advanced packaging, chiplets, high-bandwidth memory, photonics, power delivery networks, and complex cooling infrastructures. These systems exhibit tightly coupled multiphysics behavior that can directly impact performance, reliability, power consumption, and time-to-market.

The Synopsys Multiphysics Fusion Solutions portfolio is designed to provide a unified digital twin environment where engineers can analyze and optimize multiple physical domains simultaneously. Rather than performing separate simulations for electrical, thermal, mechanical, and electromagnetic effects, the Fusion platform enables concurrent analysis with shared data models and interoperable workflows.

At the heart of the approach is the integration of traditionally separate simulation technologies into a common framework. Electrical simulation can be directly correlated with thermal analysis to identify hotspots that affect transistor performance. Mechanical stress modeling can be linked to package reliability studies. Electromagnetic simulations can be combined with signal integrity and power integrity analysis to identify potential issues before fabrication.

The need for this capability is becoming increasingly urgent as advanced packaging technologies such as 2.5D and 3D integrated circuits gain widespread adoption. Through-silicon vias (TSVs), silicon interposers, and stacked-die architectures create new interactions between heat, power delivery, and mechanical stress. A thermal hotspot in one die can affect the performance and reliability of neighboring dies, while package warpage can influence electrical connectivity and long-term reliability.

Synopsys is also leveraging artificial intelligence to accelerate multiphysics analysis. AI-assisted optimization can rapidly explore design tradeoffs across multiple domains, helping engineers identify optimal solutions that balance performance, power, area, cost, and reliability. This capability is especially valuable as simulation workloads continue to grow exponentially with design complexity.

Another important aspect of the Multiphysics Fusion strategy is the creation of a consistent digital thread across the semiconductor development process. Data generated during device design, package development, board implementation, and system validation can be shared more effectively, reducing the need for manual data translation and minimizing opportunities for errors. This unified approach improves collaboration among traditionally siloed engineering teams.

The first wave of Fusion solutions targets several critical applications, including advanced packaging, multi-die systems, photonics, thermal management, and reliability analysis. These areas are among the fastest-growing segments of the semiconductor industry and represent key enablers for artificial intelligence infrastructure, high-performance computing, automotive electronics, aerospace systems, and next-generation communications platforms.

Why It Matters

The significance of Synopsys’ Multiphysics Fusion Solutions extends beyond simulation efficiency. The semiconductor industry is entering an era where system-level interactions often determine product success more than transistor-level scaling alone. As Moore’s Law slows and system complexity increases, innovation increasingly comes from integration, packaging, and heterogeneous architectures.

Traditional point tools cannot adequately capture the coupled physical effects that drive performance and reliability in these systems. Engineering teams need a holistic view of how electrical, thermal, mechanical, and optical phenomena interact throughout the design lifecycle. The ability to identify issues early in development can prevent costly redesigns, improve yield, accelerate qualification, and reduce overall development risk.

Bottom line: For AI data centers, advanced automotive systems, and high-performance computing applications, thermal and power challenges are becoming primary design constraints. Multiphysics simulation provides the insight needed to optimize these systems before silicon is manufactured. As a result, Synopsys’ Fusion strategy represents an important step toward the industry’s broader transition from isolated design tools to comprehensive digital engineering platforms that enable faster innovation and more predictable product outcomes.

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June 17, 2026June 16, 2026

RISC-V and AI: The Architecture Shift Is Now

RISC-V and AI: The Architecture Shift Is Now
by Daniel Nenni on 06-17-2026 at 10:00 am
Categories: IP, RISC-V
2 Comments

The semiconductor industry has experienced several defining transitions over the last three decades. We moved from single-core to multicore processors, from ASIC-centric designs to IP-based SoCs, and from monolithic integration to heterogeneous architectures. Today, another transition is underway, one that may ultimately prove just as significant: the convergence of AI-driven computing and the rise of RISC-V.

The latest SHD Group RISC-V Market Report suggests that this transition is accelerating much faster than many expected. Forecasts now project RISC-V-based SoC shipments reaching nearly 36 billion units by 2031, generating more than $300 billion in associated semiconductor revenue. While forecasts should always be viewed cautiously, the underlying drivers behind this growth are increasingly difficult to ignore.

The story is no longer about replacing Arm or x86. The real story is about enabling heterogeneous computing.

Modern SoCs are no longer centered around a single CPU architecture. Instead, they combine multiple compute elements including CPUs, GPUs, DSPs, NPUs, AI accelerators, security processors, and increasingly domain-specific engines optimized for particular workloads. In this environment, engineers are selecting processor architectures based on function rather than ideology.

This shift plays directly to the strengths of RISC-V.

Unlike proprietary instruction set architectures, RISC-V provides designers with an open and extensible foundation that can be customized for specific applications. Whether the requirement is a deeply embedded controller, an AI management processor, a safety processor in automotive systems, or a high-performance application core, RISC-V can be adapted without the licensing constraints that have historically limited architectural innovation.

Artificial intelligence has become the catalyst accelerating this trend.

AI workloads increasingly demand hardware specialization. The era when a general-purpose processor could efficiently execute every workload is ending. Neural networks, transformer models, vector processing, sparse computation, and edge inference all benefit from customized hardware acceleration.

RISC-V enables designers to create custom instruction extensions that target these workloads directly. Rather than forcing AI accelerators to conform to a fixed ISA, hardware architects can optimize processing pipelines around application requirements while maintaining software compatibility. This flexibility has become one of the architecture’s most compelling advantages.

Not surprisingly, some of the industry’s largest companies are embracing this approach.

NVIDIA’s announcement that RISC-V processors are deployed throughout its silicon portfolio may prove to be one of the most important validation events in the architecture’s history. The significance extends far beyond unit volumes. When the dominant supplier of AI infrastructure adopts RISC-V broadly, it sends a strong signal to both semiconductor vendors and system companies that the architecture is production-ready at scale.

The implications extend well beyond CPU IP vendors.

EDA companies are increasingly incorporating AI-driven automation into design flows to manage rapidly rising complexity. At the same time, advanced SoCs are integrating hundreds of IP blocks, multiple compute domains, sophisticated network-on-chip fabrics, and increasingly complex software stacks. High-end designs are projected to exceed 12 million K-gates by 2031, placing enormous pressure on design methodologies, verification environments, and system integration tools.

This creates opportunities across the semiconductor value chain.

IP vendors gain new markets. EDA vendors gain new complexity challenges to solve. Foundries benefit from larger and more sophisticated devices. System companies gain greater architectural freedom. Perhaps most importantly, startups can now enter processor markets without first negotiating access to proprietary architectures.

That does not mean challenges disappear. Software maturity, ecosystem consistency, verification requirements, and long-term compatibility remain critical concerns. The success of RISC-V will ultimately depend not only on the ISA itself but on the strength of the ecosystem surrounding it.

Fortunately, that ecosystem has reached a level of maturity that would have seemed unlikely just a few years ago.

The question today is no longer whether RISC-V will become important. The question is how large a role it will play as AI reshapes the semiconductor industry. Based on current market activity, customer adoption, and ecosystem investment, the answer appears increasingly clear: RISC-V is becoming one of the foundational technologies of the AI era.

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June 17, 2026June 16, 2026

MIPI Alliance Accelerates Automotive AI Connectivity with A-PHY Compliance Program

MIPI Alliance Accelerates Automotive AI Connectivity with A-PHY Compliance Program
by Daniel Nenni on 06-17-2026 at 8:00 am
Categories: IP

The automotive semiconductor industry is undergoing a major architectural transition as vehicles evolve into centralized, software-defined computing platforms capable of supporting advanced driver assistance systems (ADAS), autonomous driving, and AI-enabled cockpit applications. This shift is driving demand for deterministic, high-bandwidth, low-latency in-vehicle networking technologies, particularly at the sensor interconnect layer. Against this backdrop, the MIPI Alliance has launched a formal compliance program for its A-PHY specification, a move designed to accelerate ecosystem interoperability and strengthen deployment confidence across the automotive supply chain.

MIPI A-PHY is a long-reach Serializer/Deserializer (SerDes) physical layer specification optimized for automotive applications requiring multi-gigabit connectivity between cameras, displays, sensors, and centralized compute platforms. Unlike conventional short-reach PHY technologies used in consumer electronics, A-PHY was engineered specifically for automotive environments characterized by high electromagnetic interference (EMI), wide operating temperature ranges, strict functional safety requirements, and cable lengths extending up to 15 meters.

At the physical layer, A-PHY uses a highly robust embedded-clock architecture combined with advanced forward error correction (FEC), retransmission mechanisms, and adaptive equalization to maintain ultra-low packet error rates under harsh automotive conditions. The specification targets bit error rates (BER) on the order of 10^-19 at the application layer, a critical requirement for safety-relevant ADAS and autonomous driving workloads.

A-PHY supports asymmetric high-speed data transport, enabling downstream transmission rates ranging from 2 Gbps to 16 Gbps per lane while simultaneously supporting lower-bandwidth upstream control traffic. This architecture is particularly well suited for image sensor aggregation where large volumes of video data flow from edge sensors toward centralized AI processors. Modern ADAS camera modules generating uncompressed or lightly compressed high-resolution video streams require deterministic throughput with extremely low latency, making traditional automotive buses increasingly inadequate.

One of A-PHY’s key differentiators is its ability to transport native MIPI protocols including CSI-2 and DSI-2 transparently across long automotive cable assemblies. This preserves compatibility with the broader MIPI imaging and display ecosystem while enabling automotive-grade reach and reliability. The technology effectively extends the mobile imaging ecosystem into automotive applications, leveraging years of industry investment in MIPI camera and display interfaces.

The newly announced compliance program introduces a formalized interoperability and certification framework covering electrical, protocol, channel, and system-level validation. Compliance testing includes transmitter and receiver characterization, channel loss tolerance, jitter analysis, electromagnetic compatibility (EMC), signal integrity validation, forward error correction performance, and interoperability verification across multi-vendor implementations.

From a system architecture perspective, the compliance initiative is critical because automotive OEMs increasingly rely on heterogeneous supply chains. Camera modules, image sensors, processors, serializers, deserializers, connectors, and cabling infrastructure frequently originate from different vendors. Without rigorous compliance validation, interoperability challenges can create costly qualification delays and increase system integration risk.

The MIPI Alliance compliance framework is therefore intended to establish deterministic interoperability across the ecosystem, reducing engineering overhead for Tier 1 suppliers and automotive OEMs. Standardized conformance testing also improves scalability for software-defined vehicle architectures where sensor counts and aggregate bandwidth requirements continue to increase rapidly.

The importance of high-speed automotive SerDes technologies is growing alongside the industry transition toward centralized zonal architectures. Traditional vehicles relied on distributed electronic control units connected via CAN, LIN, FlexRay, or Automotive Ethernet. However, next-generation AI-enabled vehicles increasingly consolidate perception, sensor fusion, and decision-making into centralized compute clusters powered by GPUs, NPUs, and domain controllers.

This architectural shift dramatically increases demand for high-bandwidth sensor interconnects capable of supporting multiple 8-megapixel or higher-resolution cameras, LiDAR arrays, radar systems, and immersive cockpit displays. A single autonomous driving platform may process tens of gigabits per second of real-time sensor data. A-PHY is positioned as a foundational transport layer capable of supporting these next-generation sensor fusion architectures.

Several semiconductor vendors are actively building products around the A-PHY ecosystem. Valens Semiconductor has emerged as an early leader through its VA7000 chipset family, which targets ADAS and autonomous vehicle connectivity platforms. Analog Devices has also supported A-PHY adoption through high-speed automotive connectivity solutions, while Synopsys provides IP and verification tools supporting integration into automotive SoCs.

The compliance program also carries important implications for automotive functional safety. High-speed sensor connectivity links increasingly carry mission-critical perception data directly impacting braking, steering, and autonomous navigation decisions. A-PHY’s error correction mechanisms, redundancy capabilities, and deterministic reliability characteristics align closely with ISO 26262 safety requirements and ASIL-rated system architectures.

From an ecosystem perspective, the launch of the compliance program represents a maturation point for A-PHY as it moves from specification development toward large-scale automotive deployment. Certification infrastructure helps accelerate OEM qualification cycles, improve supplier interoperability, and reduce validation complexity across increasingly sophisticated vehicle platforms.

Bottom line: As automotive AI workloads continue scaling, the industry’s networking bottleneck is shifting closer to the sensor edge. The MIPI Alliance’s A-PHY compliance initiative positions the specification as a strategic enabling technology for next-generation autonomous and software-defined vehicle architectures, where reliable multi-gigabit connectivity becomes as important as compute performance itself.

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June 17, 2026June 15, 2026

PowerArtist RTL Power Estimation Folds into Keysight

PowerArtist RTL Power Estimation Folds into Keysight
by Bernard Murphy on 06-17-2026 at 6:00 am
Categories: EDA, Keysight EDA

PowerArtist exploring and fixing hotspots in a GPU

Back in the late 1990s, Sente launched a product called WattWatcher to estimate power from design RTL and simulation activity. This was revolutionary for its time since alternatives, while very accurate, only offered power analysis at the gate level. Gate-level analysis is great for fine-tuning power but is unhelpful for achieving the larger gains possible through architectural optimizations. These improvements can only be explored effectively at RTL (or earlier), which has driven the industry-wide shift toward shift-left design optimization.

Over time, this capability evolved through multiple transitions—Sente to Apache Design Solutions, then to Ansys, and most recently into Synopsys, eventually leading to a spinout into Keysight. This evolution reflects a broader industry realization: power must be addressed early, not late. Modern SoC complexity demands tools that provide actionable insight at RTL. Here I’ll focus on recent successes for PowerArtist, based on a recent webinar.

This is where PowerArtist is positioned today. Rather than being just another power analysis tool, it enables designers to make architecture-level decisions early, when the impact on power, performance, and area is the highest. By combining fast analysis with workload-aware accuracy, PowerArtist brings implementation-relevant insights into the earliest stages of design, helping teams avoid costly late-stage iterations.

Power case studies against realistic workloads

Power remains a challenging metric to manage during design. It is influenced not only by implementation details but also by real-world use cases. A design may meet typical power targets, yet unexpected workloads can cause spikes that lead to system failures.

To address this, PowerArtist emphasizes workload-driven power analysis, bridging the gap between architectural intent and real usage conditions.

For example, joint work with Intel demonstrated emulation-driven power tracking on a GPU using real workloads. They were able to save 3% in dynamic power by improving clock-gating efficiency and 1.5% overall power. While these numbers may appear modest, they are highly significant for already optimized designs—highlighting the value of early visibility.

At earlier stages of design, the impact is even larger. An AMD presentation found 27% saving in dynamic power and 56% improvement in clock gating efficiency for an IP. This reinforces a key message: the earlier you start doing these analyses, the bigger the gains you will find.

A more specialized example was reported by NVIDIA, focusing on RAM access efficiency for a GPU. Such accesses can consume 10–20% of total power. By optimizing unnecessary reads, they reduced dynamic power between 6% and 20% and achieved a net power reduction of 3.5% to 4%.

Estimating glitch power

Glitches can happen when delays are imbalanced in convergent logic, where a gate output can temporarily toggle before stabilizing. These glitches can contribute significantly to dynamic power consumption—up to 40% in some cases.

Traditionally, detecting these imbalances has been a gate-level problem. But that limitation is unacceptable given the power impact. Glitch-aware sensitivity must shift left.

PowerArtist addresses this gap by enabling glitch-aware analysis at RTL. Using fast synthesis and delay modeling, designers can identify glitch risks without lengthy implementation cycles. This allows teams to detect hidden inefficiencies early, avoid costly late-stage fixes, and improve overall design quality.

Bottom Line:

The broader takeaway is clear: power optimization is no longer a back-end problem. The industry is moving toward a methodology where power is analyzed with real workloads, optimization happens at RTL, and complex effects like glitches are addressed early.

PowerArtist aligns strongly with this shift. By combining shift-left analysis, workload awareness, and advanced capabilities like glitch estimation, it acts not just as a power analysis tool, but as a design optimization platform.

As designs become more power-constrained and performance-driven, this shift is essential. PowerArtist enables that transformation, helping teams achieve better power outcomes while accelerating design convergence.

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June 16, 2026June 16, 2026

Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026

Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026
by Daniel Nenni on 06-16-2026 at 2:00 pm
Categories: Foundries, Intel Foundry

At the 2026 VLSI Symposium, Intel Foundry provided a detailed update on its process technology roadmap, highlighting the continued maturation of Intel 18A, the introduction of Intel 18A-P, and several advanced research initiatives that extend beyond current gate-all-around (GAA) transistor architectures. The presentation underscored Intel’s strategy of combining manufacturing execution with differentiated process technologies to strengthen its position in the foundry market.

The absolute best slide from the pre-briefing was the first one above. This insight comes directly from Lip-Bu Tan and his experience at Cadence, working closely with TSMC and the world’s leading semiconductor companies.

It is a shame that Samsung Foundry has not fully embraced this approach as well. The recipe is actually quite simple: tell customers what you are going to do, do it, and then tell customers what you have done.

Anyone who has attended a TSMC Technical Symposium has seen this playbook in action. TSMC consistently communicates a clear roadmap, executes against it, and then returns to demonstrate measurable results. That discipline and transparency are a big part of why customers trust TSMC and continue to invest in its ecosystem.

Intel reported that its 18A process is now ramping in two U.S. fabrication facilities, with defect density continuing to decline ahead of internal projections. The company indicated that Intel 18A is already powering multiple client products, with data center applications expected to follow. This progress is significant because Intel 18A represents the company’s first production node integrating RibbonFET gate-all-around transistors and PowerVia backside power delivery, two technologies widely viewed as critical enablers for advanced logic scaling.

A major announcement at VLSI 2026 was Intel 18A-P, the first performance-enhanced derivative of the Intel 18A family. Unlike a simple process shrink, 18A-P introduces new transistor options, improved power delivery structures, and enhanced thermal characteristics while maintaining backward compatibility with existing Intel 18A designs.

The process offers measurable improvements in power, performance, and area (PPA). Intel reported up to 18% lower power consumption at iso-performance and approximately 9% higher performance at iso-power based on a fully routed Arm core test vehicle. Additional enhancements include 20-40% improvements in thermal resistance and 10-30% lower via resistance on performance-critical interconnect layers.

One of the most notable innovations in Intel 18A-P is the introduction of a dual-contact Power Boost structure. This approach combines traditional front-side contacts with direct backside contacts enabled through PowerVia technology. By reducing parasitic resistance and improving current delivery, Intel can achieve higher transistor drive strength while simultaneously improving energy efficiency.

Intel also expanded the available threshold-voltage (Vt) options. A new intermediate Vt category positioned between Ultra-Low Vt (ULVT) and Low Vt (LVT) provides circuit designers with additional flexibility when balancing leakage power against performance. The company noted a 33% tightening of skew corners and reduced process variation, enabling more predictable timing closure and design optimization.

Thermal management was another focus area. Intel 18A-P incorporates both design and materials innovations aimed at improving heat dissipation. Enhanced thermal conductivity and advanced EDA-driven thermal optimization techniques are intended to support increasingly power-dense compute workloads, particularly in artificial intelligence and high-performance computing applications.

The symposium also featured new quantitative data regarding the advantages of combining Backside Power Delivery (BSPD) with Gate-All-Around transistors. Intel reported approximately 10× dynamic voltage droop reduction and 5-6% frequency improvements, or alternatively more than 15% dynamic power reduction. Additional benefits include routing simplification, improved area efficiency, and better translation of transistor-level performance gains into actual circuit-level frequency improvements.

Looking beyond current production technologies, Intel presented several advanced research projects. Among them was the development of Complementary FETs (CFETs), which stack PMOS and NMOS devices vertically to extend transistor density scaling beyond conventional GAA structures. Intel demonstrated a monolithic CFET inverter with a contacted poly pitch of 45 nm, highlighting progress toward future logic generations.

The company also showcased a ruthenium-based interconnect architecture featuring air-gap integration. This approach achieved approximately 35% capacitance reduction compared with traditional copper-based interconnects, potentially enabling higher operating frequencies while reducing signal delay and power consumption.

Another research highlight involved the integration of gallium nitride (GaN) power devices with silicon CMOS logic on 300 mm wafers. By combining power management and logic control on a single die, Intel aims to improve system efficiency while reducing packaging complexity and overall solution cost.

Bottom line: Collectively, these announcements demonstrate Intel Foundry’s dual focus on near-term manufacturing execution and long-term technology innovation. With Intel 18A entering production, 18A-P advancing performance capabilities, and a robust research pipeline spanning CFETs, advanced interconnects, and heterogeneous integration, Intel continues to position itself as a leading developer of next-generation semiconductor process technologies.

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June 16, 2026June 17, 2026

GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck

GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
by Admin on 06-16-2026 at 10:00 am
Categories: EDA, Siemens EDA

As semiconductor manufacturing pushes toward advanced nodes with tighter feature sizes, the optical proximity correction (OPC) workflow is adopting curvilinear masks to achieve the larger process windows that traditional Manhattan geometries cannot deliver.

Traditional Manhattan masks constrain shapes to vertical and horizontal edges, forcing OPC algorithms to approximate curves using many small straight segments. Curvilinear masks use cubic Bezier splines—smooth mathematical curves—to represent shapes naturally, enabling more precise control around corners and curved features where lithography is most challenging. However, this transition introduces a computational challenge that threatens to slow the entire optical proximity correction workflow.

The problem centers on mask rule check (MRC), the validation step that ensures mask designs can be manufactured without defects. For curvilinear masks, MRC can represent a large portion of overall OPC runtime. When teams cannot validate mask manufacturability quickly, they face extended iteration cycles and delayed convergence, creating schedule risk precisely when advanced nodes demand faster time-to-market.

OPC methodologies are transitioning to GPU acceleration to reduce computation time and cost. Use of GPU processing alters the traditional paradigm where mask designs are broken into chunks distributed across CPU cores; instead, a grouping of cores is assigned to share a GPU machine. As seen in Figure 1, CPU cores delegate OPC tasks that benefit from the massive parallelism offered by GPUs, while serial tasks remain local to the CPU. The primary limitation is GPU memory (VRAM), which must hold all relevant data for all tiles being processed. Moving data on and off the GPU adds significant overhead and should be avoided.

Figure 1. Many-core CPUs share the same GPU. In this example, 16 CPU cores share a single GPU for efficient processing of heavily parallelized tasks, illustrating how CPU and GPU resources are orchestrated in mask rule checking.

Why curvilinear MRC becomes a bottleneck

With Manhattan geometries, calculating the minimum distance between two parallel mask segments is computationally efficient and exact. The answer is simple: the absolute value of the difference between two coordinates. No approximation, no error tolerance, no complexity.

Curvilinear masks don’t share this simplicity. Computing the minimum distance between two arbitrary cubic Bezier curves requires solving a multivariate optimization problem with no efficient closed-form solution. Common methods use iterative approximation methods that are both computationally expensive and inherently approximate. As illustrated in Figure 2, the key MRC problem for cubic Beziers is that we no longer have access to an exact answer. With cubic Beziers, error tolerance and approximation become core to MRC and must be weighed vs. runtime when designing an MRC flow at scale.

Figure 2. Comparison of minimum distance calculations for curvilinear masks (left), which require iterative multivariate solvers and Manhattan masks (right), solved with straightforward arithmetic. The shift to Bezier-based curvilinear layouts dramatically increases computational complexity in mask rule checking.

The addition of curvature adds complications depending on whether we are comparing Bezier sections within a polygon (internal) or between different polygons (external). These categories involve additional constraints in the form of a normal vector comparison (angle tolerance) and a perimeter check (separation distance).

The recursion problem blocking GPU acceleration

GPUs excel at massively parallel workloads, making them ideal for MRC where each curve pair can be evaluated independently. However, the empirical methods traditionally used for Bezier distance computation rely on recursion, which fundamentally restricts GPU acceleration.

Recursion creates unpredictable memory access patterns and divergent execution paths that undermine the parallel processing model GPUs require. When different threads follow different recursive paths, GPU streaming multiprocessors sit idle waiting for divergent threads to converge, making the massive parallelism that makes GPUs powerful inaccessible.

A GPU-native approach to Bezier MRC

We developed a GPU-native MRC solution that eliminates recursion while delivering superior performance and higher accuracy than traditional CPU approaches. The algorithm is specifically designed for the parallel execution model GPUs require, avoiding the recursion problem.

The approach achieves speedups ranging from 14x to 37x compared to CPU baselines, depending on accuracy specification. This performance improvement comes with an order of magnitude higher accuracy. As shown in Figure 3, for external violations, the error distributions are tightly centered around zero, with more than 90 percent of observed errors confined within one database unit (dbu), the minimum resolvable coordinate increment in the layout.

Figure 3. Histograms of MRC error for external (left) and internal (right) violations under three accuracy specifications.

This tight error distribution demonstrates numerical stability matching or exceeding brute-force reference implementations. Internal violation results exhibit a broader error distribution due to increased geometric complexity incorporating additional constraints such as angle tolerance and intra-shape separation distance evaluation.

The algorithm handles localized angle tolerance, a capability that challenges recursive methods. When validating MRC violations, teams must verify not just the minimum distance between curves but also the angle between them at the closest points. The GPU-native approach performs these coupled evaluations efficiently within the same parallel framework.

Scaling to production with intelligent batching

GPU memory represents the primary constraint when deploying MRC at production scale. Large tiles generate substantial numbers of curve pairs that must be evaluated, and all relevant data must fit in GPU VRAM to avoid expensive data transfer overhead.

We addressed this limitation through a batching mechanism that partitions the workload into smaller subsets processed sequentially. This reduces peak VRAM requirements by an order of magnitude compared to unbatched configurations, enabling memory savings without compromising runtime performance.

Increasing the number of batches leads to significant reduction in peak GPU memory consumption, achieving an order of magnitude improvement compared to the unbatched configuration. For large tile sizes, batching does not adversely affect runtime performance. The observed GPU speedup remains essentially unchanged across different batch counts because GPU streaming multiprocessors remain fully utilized, even when only a subset of curve pairs resides in memory at any given time.

Implications for curvilinear OPC workflows

This GPU-native MRC flow directly addresses one of the primary computational bottlenecks in curvilinear OPC workflows. By delivering substantial performance improvements and superior accuracy within a scalable framework, it lowers runtime for curvilinear OPC in high-volume production environments.

The algorithmic advantages extend beyond immediate performance metrics. The elimination of recursion and the batching strategies developed here provide a foundation for future GPU-native computational lithography algorithms. As the semiconductor industry continues pushing toward lower k1 process nodes and GPU hardware evolves with increasing VRAM capacities, these architectural considerations will remain relevant for scaling to increasingly complex mask designs.

Teams adopting curvilinear masks no longer face the choice between validation accuracy and iteration speed. The GPU-native approach delivers both, removing a critical barrier to curvilinear OPC deployment at production scale. When MRC validation runs 14x to 37x faster with higher accuracy, teams can iterate more rapidly and converge with greater confidence that their masks will manufacture successfully.

Learn more: Download the white paper “GPU-native Bezier mask rule check for high-volume production” to explore the algorithmic innovations and validation results in detail.

Authors: Ethan Maguire and Moatsm Elde.

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June 16, 2026June 15, 2026

A tower-like heterogeneous packaging architecture for the AI era

A tower-like heterogeneous packaging architecture for the AI era
by Moh Kolb on 06-16-2026 at 6:00 am
Categories: 3D IC, AI

VEMC: The Vertical System EM Corridor. AI packaging is moving beyond the flat package.

For years, advanced packaging has been described mostly in planar terms: chiplets placed side by side, connected through interposers, bridges, redistribution layers, substrates, and short-reach electrical links. This view remains important. It supports today’s GPU, HBM, chiplet, and 2.5D integration architectures.

But future AI platforms may require something more.

As packages grow larger, bandwidth rises, power density increases, and heterogeneous integration expands, the package may no longer be only a flat routing surface. It may become a vertical realization environment.

This leads to an important concept:

the Vertical System EM Corridor.

A System EM Corridor is the physical path where signal integrity, return current, power integrity, electromagnetic behavior, thermal behavior, mechanical stability, and package geometry interact. In many current systems, this corridor is largely lateral. Signals move across an interposer or substrate. Power enters through board or package structures. Optical engines, when used, are often attached near the edge or placed close to a switch, ASIC, or optical I/O block.

In larger AI systems, that corridor may need to extend vertically.

Glass substrates and through-glass vias make this idea especially interesting. Glass can offer dimensional stability, low electrical loss, flatness, and fine interconnect scaling potential. TGVs can create vertical signal, power, and reference transitions through the package body.

But vertical routing is not enough.

Every high-speed signal needs a return path. If signal TGVs are not supported by nearby ground-reference TGVs or controlled reference transitions, the result can be higher loop inductance, impedance discontinuity, field spreading, reflection, and signal integrity degradation.

So the real issue is not simply whether glass can provide vertical vias.

The real issue is whether the vertical electromagnetic path can become a trusted realization path.

From Vertical Routing to Vertical Realization

A future large AI package may include compute, memory, power delivery, optical transition zones, redistribution layers, and reference structures across multiple vertical regions. Some traffic will remain electrical, especially very short and dense links such as GPU-to-HBM or nearby die-to-die communication. Other traffic, especially longer package-level, package-to-package, board-level, or rack-level movement, may become a better candidate for optical transition.

The future is unlikely to be “all copper” or “all optics.”

It will likely be a hybrid hierarchy:

local electrical links for short dense communication,
vertical electrical corridors for controlled package-level routing,
selective optical transition where distance, bandwidth, and energy justify conversion,
and system-level optical fabrics where copper movement becomes limiting.

That means future AI packaging must answer a harder question:

Where should electrical remain, where should optical begin, and how can the full vertical path produce trusted system output?

This is where the Vertical System EM Corridor becomes more than a package concept. It becomes part of a realization model.

The goal is not only to connect structures. The goal is to create a trusted physical path from design intent to working system behavior.

Power Delivery Also Becomes Vertical

The same concept applies to power.

AI systems are increasingly limited not only by compute, but by power delivery. As current demand rises and transient behavior becomes more aggressive, the power corridor must move closer to the silicon.

This is where chiplet-proximate power architecture becomes important. Power delivery may need to move from the board toward the package, from the package toward the compute region, and from lateral delivery toward vertical proximity.

In a vertical realization architecture, power is not simply supplied from below. It may be distributed through controlled vertical paths, local power regions, embedded decoupling, and package-proximate conversion zones.

That creates a new convergence problem:

signal routing, power routing, return-current control, thermal extraction, optical transition, and mechanical stress are no longer separable.

They interact inside the same physical volume.

Optical Transition Zones

Optics may play a role, but selectively.

The Vertical System EM Corridor does not require every link to become optical. Instead, it creates locations where optical transition becomes meaningful.

For example, electrical links may handle local GPU-to-HBM or GPU-to-nearby-die movement, while optical conversion may be introduced for longer paths across a large package, across a module, or between packages.

In that case, the optical engine is not just an add-on.

It becomes a transition zone inside the realization corridor:

electrical launch → optical conversion → optical routing or fiber coupling → optical/electrical recovery → system fabric

This transition must be managed across electrical, optical, mechanical, thermal, manufacturing, and reliability constraints.

That is why optical interconnect is not only an optical device problem. It is an electro-optical realization problem.

Why This Is Not Just 3D Packaging

The Vertical System EM Corridor is related to 2.5D and 3D integration, but it is not the same concept.

2.5D and 3D packaging describe physical placement and interconnect methods.

The Vertical System EM Corridor describes the physical realization path through which electrical, optical, power, thermal, mechanical, and lifecycle behavior must remain coherent enough to support trusted system output.

A stacked package can still fail if the corridor is not controlled.

A glass substrate can still fail if the return path is discontinuous.

An optical interconnect can still fail if thermal drift, alignment, coupling loss, or test coverage is not controlled.

A power architecture can still fail if local transients, resonance, or thermal stress are not managed.

The question is no longer only:

Can we stack it?

The better question is:

Can the vertical corridor be trusted at scale?

From Integration to Trusted Realization

The industry is moving quickly toward language such as integration, co-design, convergence, optical fabric, glass substrate, chiplet architecture, and advanced packaging. That movement is important.

But integration is only the first step.

The harder step is trusted realization.

A vertical AI package must do more than combine compute, memory, power, optics, and interconnect. It must produce system behavior that remains stable, manufacturable, reliable, and scalable under real operating conditions.

This is the difference between an integrated package and a trusted realization output.

An integrated package connects the pieces.

A trusted realization output shows that the connected system can operate as intended across the full physical path.

Why This Matters Now

AI hardware is forcing packaging to become system architecture.

HBM integration, GPU-to-GPU movement, CPU-GPU coupling, package-to-package signaling, optical I/O, power delivery, thermal extraction, and manufacturing yield are no longer independent problems.

They are becoming one physical realization problem.

That is why the Vertical System EM Corridor matters.

It provides a way to think about future AI systems not as flat packages with more components, but as vertically realized platforms where compute, memory, power, signal, optical, thermal, and reliability paths must be controlled together.

The future AI package may not be only wider.

It may become deeper.

And the winning platforms will not be the ones that simply add more layers, more vias, or more optical channels.

They will be the ones that make the vertical realization path trusted at scale.

Closing Thought

The next frontier in advanced packaging may not be a single material, a single interconnect, or a single optical device.

It may be the ability to build a Vertical System EM Corridor: a controlled physical realization path where electrical connectivity, return-current continuity, power delivery, optical transition, thermal behavior, mechanical stability, manufacturability, and reliability can coexist inside one trusted system architecture.

In short:

Flat integration connects components.

Vertical realization creates trusted system output.

That may define the next AI platform.

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June 15, 2026June 22, 2026

Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI Silicon

Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI Silicon
by Daniel Nenni on 06-15-2026 at 10:00 am
Categories: Akeana, IP, RISC-V

The momentum behind RISC-V continues to accelerate as Akeana announced a strategic collaboration with Samsung Electronics aimed at reducing time-to-market for next-generation server and agentic AI silicon. The partnership combines Akeana’s high-performance RISC-V compute platform with Samsung Foundry’s advanced process technologies and ecosystem infrastructure, providing customers with a streamlined path from architecture to production.

As hyperscale computing, enterprise AI, and autonomous AI agents drive demand for increasingly specialized silicon, the industry is moving beyond traditional CPU-centric architectures. Companies developing AI infrastructure now require customizable compute platforms capable of supporting domain-specific acceleration, large memory footprints, high-bandwidth interconnects, and scalable software ecosystems. RISC-V has emerged as a compelling alternative due to its open instruction set architecture, flexibility, and growing ecosystem support.

Akeana has positioned itself as a provider of enterprise-class RISC-V infrastructure IP rather than simply another CPU core vendor. Its portfolio includes 64-bit high-performance processor cores, cache-coherent interconnect technology, memory subsystem IP, and system-level architecture components designed for datacenter, networking, and AI applications. By focusing on complete compute platforms, Akeana addresses one of the key challenges facing RISC-V adoption: reducing integration complexity for sophisticated SoC designs.

The collaboration with Samsung Electronics strengthens this strategy by aligning Akeana’s IP with Samsung Foundry’s advanced manufacturing capabilities and ecosystem programs. Samsung has invested heavily in enabling design ecosystems through its SAFE™ (Samsung Advanced Foundry Ecosystem) initiative, which brings together EDA vendors, IP providers, packaging partners, and design services companies. Integration within this ecosystem can significantly shorten design cycles by providing customers with pre-validated IP and optimized implementation flows.

For AI silicon developers, time-to-market has become a critical competitive factor. Generative AI and emerging agentic AI workloads are evolving rapidly, forcing semiconductor companies to shorten development schedules while simultaneously increasing design complexity. Traditional custom processor development often requires years of architecture, verification, software enablement, and physical implementation effort. By combining pre-validated RISC-V platforms with an established foundry ecosystem, customers can focus resources on workload-specific differentiation rather than foundational infrastructure.

Agentic AI represents a particularly interesting target market. Unlike conventional AI inference systems, agentic AI platforms require continuous planning, reasoning, orchestration, and communication between multiple software agents. These workloads place significant demands on memory hierarchy, interconnect bandwidth, security mechanisms, and heterogeneous compute resources. As a result, future AI systems are likely to incorporate combinations of general-purpose processors, vector engines, accelerators, and specialized AI cores connected through highly scalable fabrics.

This trend creates an opportunity for RISC-V-based architectures. The open nature of the ISA allows developers to introduce custom instructions and domain-specific extensions without the licensing constraints associated with proprietary architectures. For companies building AI infrastructure silicon, this flexibility can enable performance and power optimizations tailored to emerging workloads.

Samsung also benefits from the partnership as foundries increasingly seek differentiated ecosystem offerings beyond process technology alone. Leading-edge manufacturing remains essential, but customers now evaluate complete platform readiness, software support, IP availability, and ecosystem maturity when selecting silicon development partners. Supporting enterprise-grade RISC-V solutions broadens Samsung’s appeal to AI, cloud, networking, and datacenter customers seeking alternatives to traditional architectures.

The broader significance of the collaboration extends beyond a single partnership announcement. It reflects the continuing evolution of RISC-V from an academic and embedded computing architecture into a viable foundation for high-performance computing and AI infrastructure. As more ecosystem participants—including foundries, EDA vendors, software providers, and IP companies—align around server-class RISC-V solutions, barriers to adoption continue to decline.

Bottom line: For semiconductor companies developing next-generation server processors and AI accelerators, the combination of Akeana’s infrastructure IP and Samsung’s manufacturing ecosystem could provide a faster path to production silicon. In an industry increasingly defined by AI-driven innovation cycles, accelerating design execution may prove just as important as architectural innovation itself.

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June 15, 2026June 15, 2026

Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio

Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio
by Daniel Nenni on 06-15-2026 at 8:00 am
Categories: Chips&Media, IP

Chips&Media has announced a strategic licensing agreement with Ambarella for its latest-generation video CODEC intellectual property (IP), marking a significant milestone in the evolution of edge AI, computer vision, and physical AI systems. The agreement follows an extensive technical evaluation process and further expands the long-standing collaboration between the two companies in advanced multimedia and AI-enabled semiconductor technologies. The partnership is expected to address rapidly growing markets including autonomous driving, intelligent security, industrial automation, robotics, and Internet of Things (IoT) applications.

At the center of the agreement is Chips&Media’s newest video CODEC architecture, designed to meet the demanding requirements of next-generation vision systems. The IP delivers support for 8K video processing while optimizing critical semiconductor design metrics including power consumption, performance, memory bandwidth utilization, and silicon area efficiency—commonly referred to as PPBA optimization. These characteristics are increasingly important as edge AI devices process higher-resolution video streams while operating under strict power and thermal constraints.

Modern edge AI systems depend heavily on efficient video compression and decompression capabilities. Cameras deployed in autonomous vehicles, smart cities, industrial facilities, and robotic platforms generate massive volumes of visual data that must be analyzed in real time. Advanced CODEC IP reduces storage and transmission requirements while maintaining image quality, enabling AI inference engines to process video streams more efficiently. As vision-centric applications move from cloud-centric architectures to distributed edge computing platforms, video processing has become a foundational element of overall system performance.

Ambarella has established itself as a leader in edge AI semiconductor solutions, particularly in computer vision processors for automotive and intelligent sensing applications. The company’s recent emphasis on “Physical AI” reflects a broader industry shift toward systems capable of perceiving, understanding, and interacting with the physical world in real time. These applications require the seamless integration of image sensors, video processing engines, AI accelerators, and low-latency communications. The addition of Chips&Media’s latest CODEC technology strengthens Ambarella’s ability to deliver highly integrated system-on-chip (SoC) platforms optimized for these emerging workloads.

The collaboration also highlights the growing importance of specialized semiconductor IP in accelerating product development. Rather than developing video processing subsystems from scratch, SoC vendors increasingly rely on proven third-party IP blocks to reduce risk, shorten development cycles, and improve design efficiency. Chips&Media has built a strong reputation in the video processing market through its WAVE family of CODEC solutions, including support for advanced standards such as AV1 and emerging next-generation video technologies. Its latest architectures are engineered to deliver higher bandwidth efficiency, lower latency, and improved video quality metrics compared to previous generations.

From a market perspective, the agreement arrives at a time when demand for intelligent vision systems is accelerating across multiple industries. Autonomous vehicles require real-time video analytics for perception and decision-making. Industrial robots depend on high-resolution imaging for navigation and quality inspection. Smart security platforms increasingly leverage AI-based object detection and behavioral analysis. In each of these applications, efficient video CODEC technology directly impacts system responsiveness, power efficiency, and overall cost of ownership.

Bottom line: As edge AI and physical AI continue to converge, the partnership between Chips&Media and Ambarella demonstrates how specialized IP providers and system semiconductor companies can work together to advance next-generation intelligent systems. By combining industry-leading video processing technology with advanced edge AI architectures, the two companies are positioning themselves to address the growing demand for scalable, high-performance vision platforms across automotive, industrial, robotics, and IoT markets worldwide.

Contact Chips&Media

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