SemiWiki – Page 4 – The Open Forum for Semiconductor Professionals

May 22, 2026May 29, 2026

CEO Interview with Vivek Raghunathan of Xscape Photonics

CEO Interview with Vivek Raghunathan of Xscape Photonics
by Daniel Nenni on 05-22-2026 at 4:00 pm
Categories: CEO Interviews, Chiplet, Photonics

Vivek Raghunathan has over 18 years of experience in silicon photonics. He was a Sr. Principal Engineer, Product Architect and Program Leader for Integrated Silicon Photonics at Broadcom driving key core technology development required to co-package optics with switches and demonstrated industry’s first 25.6T Ethernet switch co-packaged with silicon photonics chiplets. Prior to joining Broadcom, he was a Principal Engineer at Rockley Photonics where he led silicon photonics product integration for their data-com product line. He started his career at Intel where he led next generation GPU to HBM interconnect technology development and the commercialization of their first Silicon-photonics-based transceivers. He received his PhD from MIT in Material Science and Engineering.

Tell us about your company?

Xscape Photonics develops custom multi-color silicon photonics fabric solutions to solve escape bandwidth bottlenecks in AI hardware. The company has grown from a seed first planted decades ago at Columbia University, where several of our founders first proposed, and then helped practically develop, our multi-color laser platform from academic research into a market-ready product.

We have raised $95M in total investment that includes notable investors like Addition, IAG, Nvidia and Cisco. Our leadership team brings years of experience working for some of the largest and most influential technology companies today, including Broadcom, Intel, Cisco, Lumentum and NeoPhotonics.

What problems are you solving?

Xscape Photonics is solving the problem in data center networks of Escape Bandwidth: the maximum amount of optical data that can be moved off-chip and into the system at a time. This problem creates a bottleneck for agentic AI workloads and leads to inefficient data flow, wasted energy and idle GPUs (low GPU utilization). To solve this problem, we are replacing outdated legacy copper interconnects with multi-color silicon photonics that maximize data bandwidth and throughput on each individual fiber.

What application areas are your strongest?

Our products enable next-generation, optics-based AI interconnects for data center fabrics to connect different scales of GPUs, switches and memories: scale-up, scale-out and scale-across. Our laser platform can support multiple system architectures, including Co-Packaged Optics, Near-Package Optics and Pluggable Optics.

What keeps your customers up at night?

Our customers are constantly optimizing hardware for maximizing Tokens/s/MW and minimizing cost of token generation. However, the energy consumption, operating costs and low throughput of existing networks results in a 10-50X drop in Tokens/s/MW for large context and Agentic AI applications. This calls for rewiring networks with a new solution.

Additionally, customers are looking for solutions that are scalable and available as early as possible. Xscape’s platform addresses all the concerns: Power, cost, scale, and time to market.

What does the competitive landscape look like and how do you differentiate?

The optical interconnect landscape is expansive, with startups like Xscape Photonics, Lightmatter, Ayar Labs and Celestial AI developing new solutions alongside industry titans like NVIDIA, Broadcom and AMD. The depth and breadth of competition today is an indicator of how valuable this technology is to enabling real AI advancements and ROI.

What sets Xscape Photonics apart from anyone else in the field is our CombX technology, a programmable laser source that can scale our data center fabric platform, ChromX, to hundreds of different wavelengths or colors. Whereas our competitors largely rely on external or hybrid laser sources, Xscape Photonics is developing the first multi-color laser source on chip that can truly scale bandwidth performance by 40X, compared to other state of the art solutions, and deliver 10X value at application level for the end customer.

What new features/technology are you working on?

We are building ChromX, the industry’s first programmable multi-wavelength (up to 128 colors and beyond) photonics platform for custom AI data center fabrics. Two products supporting that platform are available today: EagleX and FalconX.

EagleX is a plug-and-play technology evaluation kit for the ChromX platform. It offers a high channel count, 200-GHz spacing, high power channel and up to 16 colors in a PM-fiber output.

FalconX is the industry’s first fully redundant ELSFP module capable of emitting up to eight wavelengths of light for ultra-fast, high-capacity and low-power optical data transmission. FalconX can generate up to 8 O-band wavelengths, with greater than 1W total optical power in an output fiber, from a single off-the-shelf DFB pump laser.

How do customers normally engage with your company?

Xscape Photonics is headquartered in Silicon Valley, so we are fortunate to count many of our customers as our neighbors. We partner with Accelerator and networking providers and deliver final solutions to Hyperscaler. We are also keen to take advantage of our presence at the most significant industry events; most recently, at OFC 2026 in Los Angeles.

Also Read:

CEO Interview with Baratunde Cola of Carbice

CEO Interview with RP Singh of Seasia Infotech

CEO Interview with Adi Gelvan of Speedata

May 22, 2026May 29, 2026

CEO Interview with Baratunde Cola of Carbice

CEO Interview with Baratunde Cola of Carbice
by Daniel Nenni on 05-22-2026 at 2:00 pm
Categories: CEO Interviews

Baratunde Cola is the CEO and founder of Carbice, an Atlanta, Georgia-based company that develops scalable interface solutions to protect semiconductors and electrical components from overheating in any physical environment. He received his bachelor’s and master’s degrees from Vanderbilt University and his doctorate from Purdue University, all in mechanical engineering. He also served as the starting fullback on his college football team while earning his degrees. Cola has invented more than 30 patents and published numerous highly cited papers related to energy transfer and nanotechnology in publications including Nature Nanotechnology and the Journal of Applied Physics. In 2017, he was named the top scientist or engineer in the United States under 35 years old by the National Science Foundation. He is an award-winning public speaker and frequent keynote presenter.

Tell us about your company.

Carbice is an energy solutions company built on foundational materials technology developed in 2011 at Georgia Tech. We make thermal interface materials (TIMs) based on metal foil and carbon nanotubes that solve one of the most persistent and underappreciated problems in electronics: efficiently removing heat. Our flagship product, Carbice Pad, is a vertically aligned carbon nanotube array bonded to aluminum foil that conforms to surfaces, transfers heat exceptionally well, and holds up under the mechanical stresses that traditional TIMs can’t handle. In addition to the Carbice Pad, we have developed products for specific industries, including the Space Pad for space applications and the Ice Pad for PC enthusiasts. We also have solutions in development that help eliminate torque loss in bolts and enable “tape-on” spot cooling on PCB boards and bus bars. As a whole, our solutions support data centers, aerospace, defense, and high-powered computing.

What problems are you solving?

At the most fundamental level, we’re solving a mechanical contact problem – compression set and shear flow – that has never been solved. Heat can only move as fast as the interface allows, and most interfaces in electronics today are bottlenecks filled with voids, gaps, and inconsistencies that develop over time. Traditional TIMs like thermal grease or phase-change materials pump out over time, dry out, or just don’t make reliable contact at the pressures and temperatures modern chips operate at. Emerging solutions like liquid metal and graphite pads have similar mechanical failure modes.

There’s also a mechanical problem that doesn’t get enough attention: high-power GPUs physically bow and flex under load. We call it the trampolining effect. That flexing breaks contact between the chip and the TIM, which drives up temperatures at the exact moment you need them at their lowest. Our Carbice pads are engineered to maintain contact through that flexing. That’s not something that greases or pads built for previous generations of thermal loads can reliably do.

What application areas are your strongest?

AI infrastructure and space are where we’re seeing the most momentum right now.

On the data center side, the thermal demands from modern AI accelerators have fundamentally changed the math. Rack densities are climbing, chip TPDs are pushing into the hundreds of watts, and the industry is scrambling to keep up. We’re engaged with customers building next-generation AI data center campuses, including a partnership with DarkNX, where our solutions are part of the thermal architecture from the ground up.

In space, we became the first thermal interface solution deployed on the International Space Station as part of NASA’s HALO program. Space is the most unforgiving qualification environment there is, with extreme temperature swings, vacuum, radiation, and zero margin for failure. Our Space Pad was designed to meet that bar, and it has.

We’re also embedded in aerospace platforms through partnerships with companies like Blue Canyon Technologies and SWISSto12.

What keeps your customers up at night?

Delivering thermal budget at market speed and scale. Every customer we talk to, whether they’re designing a satellite payload or a liquid-cooled AI server rack, is running out of thermal headroom. Chips are getting more powerful faster than cooling infrastructure can adapt. And the cost of getting it wrong is high: throttled performance, shortened component life, or outright failure.

In the data center world specifically, customers are also anxious about efficiency. Power usage effectiveness (PUE) is under pressure from both an economic and a sustainability standpoint. Better thermal interfaces help the whole system run more efficiently, and that has direct operational cost implications at scale.

In aerospace and defense, the concern is reliability under extreme conditions. You can’t send a technician to fix a satellite. You can’t swap out a thermal pad in a deployed military system. Our customers need materials that perform consistently over the years in environments that would destroy conventional solutions.

What does the competitive landscape look like and how do you differentiate?
The TIM market has traditional players making greases, pads, and phase-change materials that have been around for decades. They’re good products, optimized for the thermal loads of a previous era. The challenge is that those loads have changed dramatically, and incremental improvements to conventional materials have real limits.

Carbon nanotubes combined with metal foil in our technology give us a fundamentally different starting point. The ease of use, the thermal conductivity potential, the mechanical compliance, the long-term stability: these aren’t marginal improvements, they’re a different class of solution. We’re not competing on price per gram. We’re competing on system-level performance and reliability, and for customers whose applications genuinely push the limits, that’s where the decision gets made.

Our other differentiator is depth of knowledge. This technology emerged from rigorous academic research, and the science behind what we do is something we understand at a level that’s hard to replicate quickly.

Customers often tell us that we also have the best lead times in the industry because of our very efficient 23,000 sq ft of domestic manufacturing in Atlanta, GA combined with unmatched product robustness in storage.

What new features/technology are you working on?

We’re expanding our product line to address a wider range of form factors and application requirements through Carbice Lab, our avenue for custom and application-specific development. As chip architectures evolve, with more chiplets, more heterogeneous integration, and tighter packaging, the thermal interface requirements get more complex. We’re building the tools and processes to meet customers where they are.

We can do some very unique things with our product because of the robust metal foil core. Everyone wants a metal TIM, and we have the best technology in that class, combining foil with carbon nanotubes to control dynamic contact because it will never pump out or delaminate. We are working on a few things closer to the silicon that we feel will disrupt the performance and cost curve of packaging AI chips tremendously.

How do customers normally engage with your company?

Most engagements start with a customer thermal-system requirement. A customer is designing a new system, hitting a wall on thermal performance, or qualifying materials for a demanding application. They come to us, we understand the requirements, and we figure out together whether an existing product is the right fit or whether something custom makes more sense.
For customers who want to evaluate our materials before committing, we offer sample programs and application support through Carbice Lab.

Customers often send us their systems, and we do testing for them in our labs before they commit their team resources. We work closely with engineering teams through the qualification process to ensure their success.

We’re a relatively small team, which means customers get direct access to people who actually understand the technology.

Also Read:

CEO Interview with RP Singh of Seasia Infotech

CEO Interview with Adi Gelvan of Speedata

CEO Interview with Nagesh Gupta of llmda.ai

Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley

Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley
by Daniel Nenni on 05-22-2026 at 10:00 am

Daniel is joined by Stuart Audley, vice president and general manager of product management at Caspia Technologies, where he focuses on agentic security workflows. He has decades of experience designing and deploying cryptographic hardware and security IP for top defense and leading semiconductor companies. He previously led advanced security platform development for FPGAs and ASICs at The Athena Group and Mercury Systems.

Dan explores the growing need for security analysis with Stuart, who describes the forces at play in the industry that make it critical to ensure designs are as secure and attack-hardened as possible. The growing capabilities of AI are both a growth driver for semiconductors and an increasing threat vector as those AI workloads become more capable of finding ways to attack hardware. Caspia’s primary focus is advanced security verification, and Stuart explains how the company’s technology integrates into current design flows to reduce risk.

The conversation then shifts to agentic workflows and their associated impact on the process. Stuart describes two fundamental parts of the process. One is the agent/human interaction where the methods a design engineer uses to interact with the AI tools are developed. The second is the agent/design interaction, which facilitates autonomous analysis of the design. Stuart describes several agentic development projects at Caspia. Topics such as static analysis of RTL to find and fix security weaknesses are covered. Stuart also covers several new agents that focus on automating the development of formal assertions for security analysis.

You can learn more about Caspia here and request a meeting to dig deeper here.

You can also visit Caspia in booth 759 at the DAC Chips to Systems Conference in Long Beach, CA on July 27-29,2026.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

May 22, 2026May 23, 2026

ASML High-NA EUV is Not Ready for High-Volume Production

ASML High-NA EUV is Not Ready for High-Volume Production
by Daniel Nenni on 05-22-2026 at 8:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, TSMC
16 Comments

Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just a technical decision. It is now a value proposition decision.

As things stand today, the answer appears to be no: the benefits of High-NA EUV do not justify the cost and risk at 1.4nm.

One of the biggest industry shifts is that foundry customers now have a voice in process technology decisions, and you can thank TSMC for that. TSMC’s collaborative business model gives major customers direct input on manufacturing roadmaps. The top TSMC customers I have spoken with are not ready to embrace High-NA EUV given the current economics and manufacturing risks.

TSMC has said as much publicly during the last two Technology Symposiums. In briefings at both the 2025 Symposium and last month’s event, Dr. Kevin Zhang, Senior Vice President and Deputy Co-COO, made it clear that High-NA EUV is simply too expensive relative to the expected benefit.

Intel had planned to introduce High-NA EUV at the 14A node under former CEO Pat Gelsinger. That was a classic IDM-style decision made largely without customer feedback. Under Lip-Bu Tan, however, customers are expected to have far greater influence over technology choices—which likely means Intel will move closer to the TSMC customer-first model. Samsung may not have much choice either. Foundry customers have spoken.

To be clear, ASML’s High-NA EUV technology works. The question is not technical feasibility. The real question is whether it can achieve the yield, uptime, and economics required for profitable high-volume manufacturing.

The core technical challenge is that High-NA EUV dramatically reduces process margins. Standard EUV tools operate at a numerical aperture (NA) of 0.33, while High-NA increases this to 0.55. The higher NA improves resolution and enables smaller transistor features, but it also significantly reduces depth of focus. In practical terms, wafers must remain almost perfectly flat during exposure. Even tiny variations in wafer topography, thermal distortion, or vibration can create pattern defects that reduce yield.

Photoresists are another major obstacle. High-NA systems require thinner resist films because thicker films exceed the narrow focus window. However, thinner resists absorb fewer EUV photons, increasing stochastic defects such as broken lines, missing holes, and edge roughness. These defects occur randomly and are extremely difficult to eliminate through standard process optimization. At advanced nodes, even a very small number of stochastic defects can make chips unusable.

EUV also faces a fundamental photon problem. Unlike deep ultraviolet lithography, EUV operates with relatively low photon counts. At High-NA dimensions, statistical fluctuations in photon absorption become significant enough to impact pattern fidelity. Electron blur following photon absorption further reduces precision. As the industry approaches the angstrom era, these random physical effects become increasingly difficult to control.

Mask technology introduces another layer of complexity. High-NA EUV uses anamorphic optics, meaning image scaling differs between horizontal and vertical directions. This requires entirely new mask architectures and correction algorithms. EUV masks are already among the most complex manufactured objects in the semiconductor industry, and High-NA masks push defect tolerances even further. Some defects are only visible under EUV illumination, making inspection extraordinarily difficult.

Pellicles remain another unresolved issue. These thin protective membranes shield masks from contamination, but High-NA systems require much higher source power levels, creating severe thermal stress. Existing pellicle materials can warp or degrade under sustained exposure. New materials are under development, but they are not yet fully qualified for continuous high-volume manufacturing.

Throughput and uptime are equally critical. Semiconductor fabs depend on extremely high utilization rates because downtime directly impacts profitability. High-NA tools are still early-generation systems and have not demonstrated the long-term reliability of mature EUV platforms. Even relatively small interruptions can create major economic consequences in leading-edge fabs operating 24/7.

Cost may ultimately be the largest barrier of all. Each High-NA EUV scanner costs approximately $350 million to $400 million, making it the most expensive manufacturing tool ever built. Beyond the scanner itself, fabs require major infrastructure upgrades involving power delivery, cooling, vibration isolation, and cleanroom redesign. The total investment required for High-NA production is enormous, and foundries must determine whether the incremental scaling benefits justify the expense.

TSMC appears to have already made that calculation. Rather than rushing into High-NA deployment, the company is extending existing 0.33 NA EUV systems through multipatterning and process optimization. That decision reflects concerns not only about technical maturity, but also about economic return.

The broader ecosystem is another issue. Lithography does not operate in isolation. Etch, deposition, metrology, inspection, design software, packaging, and yield-learning infrastructure must all evolve together. High-NA EUV introduces new interactions throughout the manufacturing flow, meaning the entire semiconductor ecosystem must mature before stable high-volume yields become realistic.

Bottom line: High-NA EUV is stuck in the difficult transition between laboratory success and industrial maturity. The technology has clearly demonstrated capability in research environments and pilot production, but successful semiconductor manufacturing requires much more than technical proof points. Yield stability, uptime, defect reduction, ecosystem readiness, infrastructure investment, and economic viability must all improve before High-NA EUV can become mainstream production technology.

Also Read:

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing

Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer

TSMC Process Simplification for Advanced Nodes

May 22, 2026May 23, 2026

What Winemakers and Chip Designers Have in Common

What Winemakers and Chip Designers Have in Common
by Daniel Nenni on 05-22-2026 at 6:00 am
Categories: 3D IC, AI, Analog Bits, Chiplet, Events, IP, Semiconductor Services, Silicon Catalyst

Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem, and that directly reflects the company’s culture and leadership.

According to Mahesh, modern artificial intelligence systems and industrial wine production appear unrelated at first glance. One produces digital intelligence through silicon computation while the other transforms grapes into wine through biological fermentation. Yet both industries are fundamentally governed by the same engineering challenge: controlling thermodynamic instability. In both cases, precision heat management, energy distribution, and analog feedback mechanisms determine final system quality and operational efficiency.

Wine fermentation is inherently an exothermic chemical process. As yeast metabolizes sugars into ethanol and carbon dioxide, heat is released continuously. If temperature rises beyond carefully controlled thresholds, yeast behavior becomes unstable, producing undesirable flavor compounds, accelerating oxidation, and potentially halting fermentation entirely. Modern wineries therefore function as closed-loop thermal control systems rather than simple agricultural facilities. Stainless steel fermentation tanks integrate cooling jackets, distributed thermal sensors, programmable flow valves, and automated refrigeration systems designed to maintain temperature within narrow tolerances.

Thermal gradients inside fermentation vessels are especially problematic because biological activity is nonlinear. Higher temperatures accelerate yeast metabolism, which in turn generates additional heat, creating positive thermal feedback. Without intervention, localized hotspots emerge, causing flavor inconsistency and microbiological instability. As a result, winery energy consumption is dominated not by mechanical processing, but by active thermal regulation.

The semiconductor industry faces a remarkably similar challenge at vastly smaller physical scales and far higher power densities. Modern AI accelerators are no longer limited primarily by computational throughput. Instead, thermal extraction and power delivery increasingly define achievable performance. High-performance GPUs used for large language models can dissipate hundreds of watts per device, while hyperscale AI clusters consume megawatts of power within tightly packed data center environments.

This shift has transformed AI infrastructure into an industrial heat-management problem. Thermal hotspots inside advanced processors create localized transistor variability, timing uncertainty, leakage current increases, and reduced operational reliability. The challenge intensifies further with advanced packaging technologies such as 2.5D interposers, chiplets, and vertically stacked high-bandwidth memory. These architectures improve bandwidth and computational density, but simultaneously trap heat within multilayer structures where thermal extraction becomes increasingly difficult.

At advanced process nodes, semiconductor operation is no longer purely digital. Analog behavior increasingly dominates system stability. Power delivery networks, phase-locked loops, voltage regulators, droop detectors, and process-voltage-temperature sensors all operate within highly sensitive analog margins. Millivolt-scale voltage fluctuations can alter transistor switching behavior, while nanosecond-scale timing jitter can propagate across high-speed interfaces and memory fabrics.

This phenomenon represents what many engineers describe as “the revenge of analog.” Digital abstraction assumes deterministic binary operation, yet physical semiconductor devices remain governed by continuous electrical and thermal physics. IR drop across power grids, electromagnetic coupling, thermal drift, and leakage variation introduce nonlinear behaviors that cannot be fully abstracted away through digital logic alone.

The parallel with biological fermentation becomes increasingly compelling at this level. Both yeast cells and transistors become unpredictable when exposed to excessive thermal gradients. In wine production, slight changes in acidity, oxygen exposure, or fermentation temperature can dramatically alter flavor chemistry. In AI systems, small variations in voltage ripple, localized heating, or current density can degrade timing closure, reduce yield, or trigger system instability under peak computational load.

Both industries therefore operate as continuous compensation systems fighting entropy. Neither achieves perfect control. Instead, both rely on dynamic sensing, feedback correction, and energy balancing to maintain operational equilibrium near unstable boundaries. Wineries continuously adjust coolant flow and thermal balance during fermentation cycles. AI systems dynamically redistribute workloads, regulate voltage domains, and throttle thermal hotspots to maintain reliability.

The engineering convergence becomes even more evident in modern system architecture. Vertical wineries with densely layered fermentation infrastructure resemble advanced 3D semiconductor packaging. In both environments, increasing density improves efficiency and performance while simultaneously complicating heat removal. Thermal management evolves from a secondary operational concern into a primary architectural constraint.

Bottom line: Both wine production and AI computation are controlled energy transformation systems. One converts biological energy into flavor complexity while the other transforms electrical energy into machine intelligence. In each case, the true engineering challenge lies not in generating power, but in controlling its consequences. As computational density continues to increase and AI infrastructure scales globally, thermal engineering, analog precision, and intelligent power management will become the defining technologies of the semiconductor era.

Contact Analog Bits

Contact Silicon Catalyst

Also Read:

Analog Bits Demos Real-Time On-Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium

2026 Outlook With Mahesh Tirupattur of Analog Bits

Podcast EP322: A Wide-Ranging and Colorful Conversation with Mahesh Tirupattur

May 21, 2026May 21, 2026

Semiconductors Historic Start to 2026

Semiconductors Historic Start to 2026
by Bill Jewell on 05-21-2026 at 2:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

The global semiconductor market grew 25% in the 1st quarter of 2026 from the 4th quarter of 2025 to reach $299 billion, according to WSTS. The 1st quarter of 2026 was up 79% from a year earlier. The 25% quarter-to-quarter growth was the highest in the over 40-year history of WSTS data, surpassing the 20% growth in the 2nd quarter of 2009. The 79% growth versus a year earlier was also a WSTS record, beating the previous record of 60% year-to-year growth in 1st quarter 2010.

The strong 1st quarter 2026 increase from the 4th quarter of 2025 was driven by AI. Nvidia, the dominant leader in AI processors, grew 20%. The five major memory companies (Samsung, SK Hynix, Micron Technology, Kioxia, and Sandisk) all cited AI as the growth driver in their spectacular quarter-to-quarter growth rates, ranging from 57% at SK Hynix to 97% at Sandisk. The combined revenues of Nvidia and the memory companies increased 49%. In the 1st quarter of 2026, the revenues of Nvidia and the memory companies totaled $208 billion, accounting for 70% of the revenues of the top twenty companies. The other companies in the top twenty saw revenue growth of only one percent. Eight of these other companies had declines, ranging from -0.2% at AMD to -14% at Qualcomm.

The dominance of the AI-related companies is reflected in the outlook for 2nd quarter of 2026 revenue change from the 1st quarter of 2026. Nvidia expects 12% growth. The memory companies which provided revenue guidance show robust growth expectations: Micron Technology 40%, Kioxia 75% and Sandisk 34%. Samsung Semiconductor and SK Hynix did not provide revenue guidance, but both expect strong AI memory demand to continue. Both Micron and Kioxia cited increasing memory prices as a major contributor to revenue increases. The combined revenues of Nvidia and the memory companies will likely experience revenue growth of over 30% in the 2nd quarter of 2026 from the 1st quarter.

The 2nd quarter 2026 outlook for the other companies is much less optimistic. Of the eleven companies providing guidance, two expect revenue to decline versus 1st quarter. Qualcomm’s guidance is for 9.7% decline and MediaTek’s guidance is for a 3.0% decline. Both companies cite weakening smartphone sales due to shortages of memory. Of the nine companies guiding revenue growth, most cite AI-driven data center demand as a key driver. The combined revenue expectations for these eleven companies amount to four percent increase in the 2nd quarter of 2026 from the 1st quarter.

The dominance of AI has led to a shortage of semiconductors for other applications. Two key historical drivers of semiconductor demand, PCs and smartphones, should decline in 2026. IDC’s latest forecast is a 12.9% drop in smartphone unit shipments and an 11.3% drop in PC unit shipments in 2026. These will be some of the steepest ever declines in these devices, but for the first time will be due to a supply shortage rather than a demand shortage.

The powerful start of the semiconductor market in 2026 should lead to historic growth for the full year. Recent forecasts range from 52.8% from IDC to our 80% at Semiconductor Intelligence. Gartner, Omdia, and the Cowan LRA model are in a narrow range of 62% to 65%. In the over forty-year history of WSTS, the largest market increase was 42% in 1995 in the beginning years of the internet boom. Earlier estimates of the semiconductor market have not shown growth rates this high since the early years of the semiconductor industry in the 1950s.

This AI-driven market is different from most previous semiconductor market booms. The idea is that AI applications will grow rapidly and require huge growth in AI data centers. There is not a direct connection between the end user and semiconductor market as there was in the PC boom and the smartphone boom. The closest equivalent to the AI boom is the dot-com boom in 1990s. The brisk growth of the internet required a huge increase in communications infrastructure which in turn drove semiconductor demand. The collapse of the dot-com boom in 2000 revealed the size of communications infrastructure exceeded the requirements to support the internet. The dot-com bust did not significantly impact the growth of internet users and applications. Similarly, AI can continue to flourish even if there is a correction in the growth of AI data centers. The next few years will certainly be interesting times for the semiconductor industry.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

CapEx Up for Foundry, Memory

AI Drives Strong Semiconductor Market in 2025-2026

AI Bubble?

May 21, 2026May 29, 2026

Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes

Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes
by Daniel Nenni on 05-21-2026 at 8:00 am
Categories: Bronco AI, EDA

A single bug on a full-chip SoC can pull engineers off roadmap work for days or even weeks. It involves massive waveforms, thousands of files of RTL and UVM, and dense specs that aren’t always perfect. Finding these bugs have always been a matter of engineer-hours and how well knowledge diffuses through the organization.

Bronco changes that equation. At major public chip companies, Bronco Debug works through SoC-level bugs on a regular basis and delivers root-cause analyses in under 15 minutes, hands-free. These same failures take engineering teams multiple days to solve. This is what a routine Bronco debug session looks like.

WATCH REPLAY NOW

Time to Value

Bronco Debug instruments directly into your overnight regression. The moment a simulation fails, the agent is already there — pulling the run log, waveform, code, spec, and relevant project history. By the time your DV engineer sits down in the morning, a Jira-ready ticket is waiting: root cause, evidence to back it up, and specific files or fixes to look at.

Initial deployment takes days, not months. Bronco has been up and running on full-chip SoCs within a week of onboarding.

A Platform Across the Full Verification Journey

Debug is what we’re demo’ing here, but Bronco covers the full DV lifecycle:

Bronco Spec Intelligence — ingests massive specs (tables, diagrams, natural language) and automatically flags ambiguities, inconsistencies, and untested requirements
Bronco Planning — takes specs and builds or enriches a verification plan and test plan, checking for coverage holes early to avoid surprises and oversights later in the project.
Bronco Bring-Up — specialized agents for UVM and RTL bring-up at industry scale
Bronco Debug — from the first regression failure through root cause, across block-level designs and full-chip SoCs

What Makes It Work

Bronco runs on a three-layer stack:

State-of-the-art AI — large reasoning models with tool use, memory, and decision-making loops that generalize across companies, designs, and tasks.
Proprietary AI-native EDA — purpose-built for agents; this is what allows Bronco to navigate 10,000-plus-file SoCs, process massive waveforms, and run parallel debug threads across an entire regression in minutes
Bronco Knowledge Library — captures and indexes every bug, insight, and debug session into a customer-specific knowledge store; Bronco gets better the longer it runs on your project

How We Deploy

Bronco runs fully on-prem. Customer design data never leaves the secure environment, and Bronco never trains on customer data. The platform supports bring-your-own-model, whether it’s a third-party Enterprise AI or an on-prem self-hosted model, and integrates natively with standard EDA flows.

For teams with existing AI infrastructure, Bronco also supports bring-your-own-agent deployment: connect your existing agents or orchestration harnesses to the Bronco EDA stack and Knowledge Library, and use Bronco as the DV infrastructure layer underneath.

See It For Yourself

At an upcoming SemiWiki webinar, Bronco AI will demonstrate the Debug Agent end-to-end on a representative full-chip SoC — from a failing regression to an annotated root cause, in real time. Attendees can ask questions on deployment, security posture, and integration with existing flows.

WATCH REPLAY NOW

Bronco AI pairs state-of-the-art AI agents with a proprietary EDA suite purpose-built for agent-driven chip development. The platform is deployed at large public chip companies and startups alike, automating Design Verification from spec review and verification planning through post-regression debug.

Also Read:

Bronco Debug Stress Tested Measures Up

Verification Futures with Bronco AI Agents for DV Debug

Superhuman AI for Design Verification, Delivered at Scale

May 21, 2026May 18, 2026

Europe is Getting Serious About ASIC Innovation

Europe is Getting Serious About ASIC Innovation
by Bernard Murphy on 05-21-2026 at 6:00 am
Categories: AI, Automotive, EDA, Siemens EDA
2 Comments

I was born in the UK (then still a part of Europe), so always eager to see them succeed. But I must admit that past behavior has reinforced the view that the EU’s only active “contribution” to progress is regulation. However this seems to be changing in multiple interesting ways. On a grand scale, the Nordic economic model is taking off, exemplified by Sweden. That country, known for a heavy emphasis on socialism and very high taxes, is now moving to a blend of capitalism and socialism (as reported recently in the Wall Street Journal) – lower taxes, scaling back all-embracing social safety nets, and becoming more pro innovation. Closer to our domain, the EU is getting more aggressive in encouraging innovation in ASIC startups, my guess in part to accelerate growth and in part to reduce dependency on the US. There are signs that the policy makers already recognize they need to be part of that movement if they want to stay relevant.

European ASIC activity

The big players are still NXP, Infineon and ST. They too are growing beyond their comfort zones, for example with NXP now offering hardware and software to support agentic systems at the edge for industry and automotive applications. My focus here is on the nascent ASIC startup ecosystem in Europe, very much on the leading edge of innovation.

A quick personal perspective on why this is happening now. Clearly Europe has been losing out in economic growth through tech. This has been a reality for many years however a clear catalyst to move them from the status quo to action is a view that Europe can no longer depend on the US for defense or trade and that therefore they should become much more self-reliant.

For example: companies like Fractile (UK) have a $220M raise to build a new class of inference engines, Axelera has raised $250M, Arago in France aims to accelerate inference in datacenters and Vertical Compute in France has plans to reduce memory load in AI systems.

Quintaris in German, a collaboration between Bosch, Infineon, NXP, Nordic Semi and Qualcomm, is targeting application processors for automotive, later for IoT and datacenters and Semidynamics in Spain already have a strong reputation for developing ultra-customizable Risc-V systems coupled with AI accelerators.

There are several ventures promoting leading edge systems based on photonic or neuromorphic tech and new approaches to natural language processing, including Optalysys in the UK, Inmotive/Innatera in the Netherlands, and Cortical.io in Austria.

The European Chips Act (adopted late 2023) is further stimulating this activity through sovereign guarantees and funds to match VC investment. They are shooting for EU global market share in chips to be 20% by 2030, a suitably aggressive goal.

Of course we could argue that European policy makers will get in their own way and kill this initiative in the cradle. As I mentioned earlier there are promising signs that they will not be given that opportunity. The Nordic economic model and Germany’s plans for defense spending supporting home-grown tech are high profile examples. Defense particularly is a compelling priority likely to override bureaucratic resistance.

Another Initiative: European Chips Design Platform

Policy makers love their organizations, committees and acronyms. The European Chips Act created a legislative framework called the Chips Joint Undertaking (Chips JU) as a vehicle to sponsor public-private partnership to execute the Act’s goals. The Chips JU European Chips Design Platform (EuroCDP) provides access tools and technologies at predefined pricing levels, making it easier for startups, small companies and academic institutions to exploit the same tech used by large ASIC enterprises.

This is not the only such plan for EDA tool access but as the Chip JU scope expands I can see enhanced access further helping accelerate European innovation. Unsurprising then that Siemens as a big player in Europe is supporting this effort by providing access to their EDA tools through this program.

You can read the Siemens press release HERE and learn more about the EuroCDP initiative HERE.

May 20, 2026May 20, 2026

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC
by Daniel Nenni on 05-20-2026 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Events, Foundries, Siemens EDA, TSMC

SIemens EDA TSMC Teshnical Symposium 2026

At the recent TSMC Technology Symposium 2026, Siemens EDA reinforced its position as one of the key ecosystem partners supporting TSMC in the race toward AI-driven semiconductor design, advanced packaging, and next-generation process technologies. The annual forum has become one of the semiconductor industry’s most important gatherings, bringing together foundry customers, EDA suppliers, IP vendors, and packaging innovators to align around future technology nodes and design methodologies.

A major theme throughout the event was the growing impact of artificial intelligence on chip development. Siemens EDA used the symposium to highlight expanded collaboration with TSMC focused on AI-powered automation across the semiconductor workflow. The companies announced joint work involving automated Design Rule Check fixing, AI-assisted physical verification, and intelligent design optimization using Siemens’ recently introduced Fuse EDA AI System.

The partnership reflects a broader industry shift. Semiconductor complexity is increasing dramatically as AI accelerators, high-performance computing devices, automotive processors, and chiplet-based architectures push beyond the limits of traditional design methods. Designers are now managing multi-die systems, advanced 3D packaging, massive data throughput requirements, and power delivery challenges simultaneously. As a result, AI-enabled EDA tools are becoming critical to reducing development cycles and improving productivity.

Siemens emphasized that its AI technologies are being integrated directly into production-proven tools such as Calibre and Aprisa. According to the company, TSMC is collaborating with Siemens to improve multi-step automation for DRC-centric physical verification while also helping engineers gain faster access to design insights and guided recommendations during implementation.

One of the most significant aspects of the announcement involved support for TSMC’s latest process technologies. Siemens reported certifications for its EDA tools on multiple advanced nodes including N3A, N3C, N2P, A16, and A14 technologies. These certifications are essential because semiconductor companies require validated design flows before committing billions of dollars to advanced-node tape-outs. By securing early enablement and certification, Siemens ensures that mutual customers can begin development with confidence on TSMC’s newest manufacturing platforms.

Another important focus at the forum was advanced packaging and 3D integration. TSMC continues expanding its 3DFabric and CoWoS packaging ecosystems to support increasingly complex AI systems. Siemens highlighted capabilities within its Calibre 3DStack platform that address interface checking, connectivity verification, inter-chiplet DRC validation, antenna analysis, and current density analysis for 3D systems. These capabilities are particularly important as AI processors move toward heterogeneous integration involving logic, memory, photonics, and specialized accelerators inside a single package.

Industry analysts noted that the symposium showcased an increasingly competitive environment among the three leading EDA vendors: Siemens, Synopsys, and Cadence. While all three announced expanded TSMC collaborations, Siemens differentiated itself through its emphasis on agentic AI orchestration and design-to-manufacturing integration. The company’s strategy appears centered on automating complex workflows that traditionally require extensive engineering intervention.

The timing of these announcements is significant. TSMC’s roadmap now includes multiple sub-2nm technologies, backside power delivery, advanced automotive nodes, and co-packaged optics initiatives. Each of these innovations introduces new design and verification challenges. Semiconductor companies are under intense pressure to reduce design turnaround time while maintaining power, performance, and reliability targets. AI-assisted automation is increasingly viewed as the only viable way to sustain productivity improvements at advanced nodes.

At the symposium, TSMC also reinforced the importance of its Open Innovation Platform (OIP) ecosystem, where Siemens remains a key partner. The OIP model enables close collaboration between foundry technologies and EDA tool providers, ensuring early process enablement and optimized design flows. Siemens’ long-standing participation in this ecosystem has allowed it to remain deeply integrated into TSMC’s technology roadmap.

The broader semiconductor industry context also shaped discussions at the event. According to industry commentary surrounding the symposium, AI demand is driving unprecedented semiconductor growth, especially in high-performance computing infrastructure. Advanced packaging capacity, power delivery innovation, and chiplet architectures are becoming central to competitive differentiation. As these challenges intensify, EDA vendors are evolving from traditional software providers into strategic enablers of AI-era semiconductor development.

For Siemens EDA, the TSMC Technical Forum served as more than a technology showcase. It was a strategic statement about the future direction of chip design. The company is positioning itself at the intersection of AI automation, advanced manufacturing enablement, and heterogeneous system integration. By strengthening collaboration with TSMC, Siemens aims to help semiconductor companies accelerate innovation while managing the escalating complexity of next-generation designs.

Bottom line: As AI continues reshaping the semiconductor industry, partnerships like Siemens and TSMC will likely become even more important. Future chip development will depend not only on transistor scaling, but also on intelligent automation, advanced packaging methodologies, and tightly integrated ecosystem collaboration. The announcements made at the TSMC Technical Forum suggest that Siemens EDA intends to play a central role in enabling that future.

Contact Siemens EDA

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A Different Angle on Co-Simulation for Systems

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May 20, 2026May 20, 2026

Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips

Semidynamics Secures a Strategic Investment to Advance Memory-Centric AI Inference Chips
by Daniel Nenni on 05-20-2026 at 8:00 am
Categories: IP, Semidynamics

In the rapidly evolving world of artificial intelligence hardware, memory bandwidth and data movement have become just as important as raw compute power. Addressing this challenge head-on, Semidynamics has announced a strategic investment aimed at accelerating the development of its next-generation memory-centric AI inference chips. The funding marks a significant milestone for the company as it positions itself at the forefront of high-performance, energy-efficient AI silicon.

The explosion of generative AI, large language models, recommendation engines, and edge intelligence applications has dramatically increased the demand for specialized semiconductor architectures. Traditional processor designs are increasingly constrained by the “memory wall,” where moving data between memory and compute units consumes more time and energy than the computations themselves. Semidynamics believes the solution lies in rethinking chip architecture from the ground up with memory efficiency as the primary design principle.

The new investment will support the expansion of Semidynamics’ engineering teams, accelerate product development, and strengthen partnerships across the AI and semiconductor ecosystem. Company executives emphasized that the funding is not simply about scaling operations, but about enabling a new generation of AI inference platforms optimized for real-world deployment.

AI inference, unlike AI training, requires delivering fast responses while maintaining low power consumption and cost efficiency. As enterprises move AI models from research labs into production environments, the economics of inference are becoming increasingly important. Data centers, automotive systems, industrial automation, robotics, and edge devices all require hardware capable of processing massive amounts of data with minimal latency and power draw.

Semidynamics’ approach centers on memory-centric design principles that reduce unnecessary data movement and maximize memory bandwidth utilization. By tightly integrating compute resources with advanced memory architectures, the company aims to deliver significantly higher performance-per-watt compared to conventional accelerator solutions. This strategy is particularly attractive for workloads involving transformer models and large-scale neural networks, where memory access patterns dominate system performance.

Industry analysts note that AI infrastructure spending continues to rise at an unprecedented pace, creating opportunities for innovative semiconductor startups that can address bottlenecks ignored by traditional architectures. While GPU-based solutions remain dominant, the market is increasingly open to specialized accelerators that target inference efficiency, edge deployment, and lower total cost of ownership.

Semidynamics’ technology roadmap reportedly includes scalable chiplet-based architectures, advanced interconnect technologies, and customizable AI processing capabilities. Such flexibility is becoming critical as customers seek solutions tailored to specific workloads rather than relying solely on one-size-fits-all accelerators. The company’s expertise in RISC-V and configurable processor technologies also positions it well within the growing open architecture ecosystem.

The investment comes at a time when geopolitical pressures and supply chain concerns are driving renewed interest in semiconductor innovation worldwide. Governments and private investors alike are prioritizing strategic technologies that can support AI competitiveness and digital sovereignty. For emerging chip companies, access to capital and ecosystem partnerships can be the difference between promising research and commercial success.

Semidynamics executives highlighted that the company’s mission extends beyond achieving benchmark performance numbers. Instead, the focus is on enabling sustainable AI deployment by reducing energy consumption and improving computational efficiency. As AI adoption expands globally, power efficiency is becoming a critical issue for hyperscale data centers and edge infrastructure alike.

The broader semiconductor industry is also undergoing a transition toward heterogeneous computing, where different processing elements are combined to optimize specific workloads. In this environment, memory architecture and interconnect design are becoming central differentiators. Semidynamics’ emphasis on memory-centric computing reflects a larger industry recognition that future AI systems will require new architectural paradigms.

Investors participating in the funding round expressed confidence in the company’s technical direction and market opportunity. They cited the growing demand for AI inference acceleration and the need for innovative solutions capable of overcoming current scalability limitations. The investment is expected to help Semidynamics move more rapidly from development into commercial deployment.

Bottom line: As AI applications continue to expand across industries, the competition to deliver efficient and scalable hardware solutions is intensifying. With this strategic investment, Semidynamics aims to establish itself as a key player in the next wave of AI semiconductor innovation, focusing on architectures designed not only for performance, but also for the realities of modern data-intensive computing.

Contact Semidynamics

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Semidynamics Inferencing Tools: Revolutionizing AI Deployment on Cervell NPU