SemiWiki – Page 5 – The Open Forum for Semiconductor Professionals

May 20, 2026May 20, 2026

Quantum Gathering Momentum Amid Concerns for the Grid

Quantum Gathering Momentum Amid Concerns for the Grid
by Bernard Murphy on 05-20-2026 at 6:00 am
Categories: Quantum Computing

I posted recently on an eye-catching advance in quantum computing, around neutral atom systems which might accelerate the transition to production-grade fault-tolerant quantum computing (QC). There are some further updates on this front, also I listened in on a panel considering quantum-based hacking vulnerability in the grid, something which should concern us all.

Progress in quantum

To recap, neutral atom qubits can be moved around allowing for tricks like directly superposing or entangling qubits, an operation which in a fixed qubit system (most technologies) would require multiple SWAP gate operations to get necessary qubit values adjacent before applying the desired operation. Direct operation reduces error rates and enables QC functions to be partitioned, not unlike a conventional computer. Also an advance in quantum error correction (QEC) may markedly reduce physical-to-logical qubit counts over current state-of-art surface codes, albeit based on very recent papers (underpinning an equally recent QC startup).

This is encouraging for materials science, quantum chemistry and financial services, though concerning for the day when QC will open the possibility of production-scale cryptography hacking. So far I have taken RSA 2048 as my benchmark for this requirement, in the paper cited above requiring 5-10k logical qubits. ECC-256, the current encryption standard for key exchange, can be cracked in as little as 1500 logical qubits according to the same paper, suggesting this might be the first attack target. Key exchange used to update encryption keys is a perfect backdoor to disrupt every aspect of modern society.

Quantum security in energy infrastructure

The Quantum Insider recently hosted a panel on this topic with speakers from EPRI (Electric Power Research Institute), a venture investor at Constellation Energy, an exec/technical leader in the utility industry from IBM, and a program manager in the resources and energy team from Microsoft.

Early in the panel I heard a telling point. The energy industry may be suffering from innovation fatigue due to increasing digitalization and upgrades which continue throughout the system, necessary upgrades allowing for allowing for further automation. AI is playing an increasing role, I’m guessing to help with load balancing as well as for more mundane operational improvements. On the AI downside, how should the industry manage distorted demand from giant AI-centric datacenters? Distributed generation introduces further complications, legacy power generation plus renewable energy sources with challenges around power storage to balance intermittent supply against demand. Small modular (nuclear) reactors are coming online, maybe fusion reactors somewhat later. Grids must allow for distributed sources and resilience to over-demand, extreme weather and outages. Together representing a much more complex generation and distribution ecosystem which must evolve against slow-moving regulatory requirements.

If you thought the automotive industry was a speed brake on innovation, the energy industry operates on up to 20-to-50-year design life cycles. They have finite budget and expert manpower, just like everyone else, which must be balanced against all these competing demands. Where does that leave quantum security?

Organizations like EPRI and the IBM and Microsoft utilities services organization are developing support services around this area (and around the NIST post-quantum standards) though it seems clear that awareness of post-quantum security in the utilities sector at large is fairly low today. Even more telling, venture investors within the sector still question whether quantum ventures are a leading opportunity to invest, seeing exits still 5-10 years out.

That said, the energy sector won’t care about differentiated quantum implementation so need not invest in hiring quantum experts (unlike, say, the financial services sector). They can buy ready-made solutions and services from suppliers like IBM, Microsoft and others. Still, they have limited funds, many investments already underway, and no directly applicable regulatory requirements to move on post-quantum today. What can they do to start hardening the system under these constraints?

IBM and Microsoft are operating on the assumption that 2030-2035 is a window of increasing risk for security. NSA and NIST are saying that government organizations in general must adapt to post-quantum within that window, which implies to me that utilities must also adapt. But in what way and how can systems be upgraded within limited budgets? I heard a sentiment for incremental upgrades, with post-quantum-enabled gateways bridging between legacy equipment to mitigate risk, while planning to upgrade other equipment on a more extended schedule.

Another important consideration is that post-quantum methods must allow for agile support. Post-quantum security methods available today are classified as “quantum resistant” as opposed to “quantum safe”. Quantum resistant methods are secure against quantum attacks we know of today (principally Shor’s algorithm). They are not guaranteed resistant to quantum attacks that might become possible through future algorithm advances. Post-quantum security must allow for continuing upgrades, a familiar reality in classical security.

Interesting times. As we protest ever-increasing power costs, spare a thought for the challenges faced by energy providers who must ensure reliable supply against ongoing and future security threats.

Also Read:

PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026

Sensing. A Quantum Tech Ready for Market?

Could Neutral Atoms Take the Lead in Quantum Computing?

May 19, 2026May 19, 2026

PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026

PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026
by Daniel Nenni on 05-19-2026 at 10:00 am
Categories: PQShield, Quantum Computing, Security

As the threat of quantum computing to modern cybersecurity becomes increasingly real, the technology industry is accelerating efforts to develop cryptographic systems capable of resisting quantum attacks. One of the most significant developments in this field was presented at Embedded World 2026 in Nuremberg, Germany, where PQShield introduced major breakthroughs in ultra-small post-quantum cryptography (PQC) solutions for embedded systems. These innovations aim to make quantum-resistant security practical even for devices with extremely limited computing resources, marking a major step forward for the embedded industry.

Post-quantum cryptography refers to cryptographic algorithms designed to remain secure against both classical and quantum computers. Current encryption systems used in most digital devices rely on mathematical problems such as integer factorization or elliptic curve discrete logarithms. While these methods are secure against conventional computing attacks, they could be broken by powerful quantum computers using algorithms such as Shor’s algorithm. As a result, governments, research institutions, and technology companies are actively preparing for a transition to new cryptographic standards that can resist these future threats.

At Embedded World 2026, PQShield demonstrated a set of ultra-compact PQC implementations specifically optimized for embedded systems. These solutions are designed to operate efficiently on microcontrollers, IoT devices, and other constrained hardware platforms where processing power, memory, and energy consumption are extremely limited. Traditionally, one of the biggest challenges of post-quantum cryptography has been its relatively large key sizes and computational complexity. Compared to classical cryptographic algorithms, PQC methods often require more memory and processing cycles, making them difficult to deploy on small embedded devices.

PQShield addressed this challenge by developing highly optimized software libraries and hardware intellectual property (IP) that significantly reduce the memory footprint of PQC algorithms. These implementations minimize the amount of RAM required while maintaining high levels of security and performance. By reducing the computational overhead associated with post-quantum cryptography, PQShield enables embedded developers to integrate quantum-resistant security without redesigning their hardware platforms.

Another key aspect of the company’s announcement was its focus on hardware-level security integration. PQShield’s solutions include hardware IP cores that can be embedded directly into system-on-chip (SoC) designs. Hardware acceleration allows cryptographic operations to be performed more efficiently than software-only approaches, which is particularly important for embedded systems that must maintain strict power and performance constraints. These hardware implementations can support standardized post-quantum algorithms while ensuring compatibility with existing embedded architectures.

Security in embedded systems involves more than just mathematical encryption. Devices must also be protected against side-channel attacks, which exploit physical characteristics of a device during cryptographic operations. Examples include power consumption monitoring, electromagnetic analysis, and timing attacks. PQShield’s PQC solutions incorporate advanced countermeasures against these vulnerabilities, including protections against differential power analysis (DPA) and other forms of side-channel leakage. These protections ensure that even if attackers gain physical access to a device, extracting cryptographic keys remains extremely difficult.

The introduction of compact PQC implementations is particularly important as edge computing and artificial intelligence (AI) become more widespread. Modern embedded devices increasingly process sensitive data locally, whether in industrial automation systems, medical devices, automotive platforms, or consumer electronics. As these systems grow more connected, the number of potential attack surfaces also increases. Implementing strong, future-proof cryptographic security at the edge is therefore essential to protecting both data and infrastructure.

Another factor driving the adoption of PQC is the long lifecycle of embedded systems. Many embedded devices remain in service for 10 to 20 years or longer, especially in sectors such as automotive, aerospace, and critical infrastructure. Devices deployed today may still be operational when quantum computers become capable of breaking classical encryption. Without early adoption of post-quantum cryptography, these systems could become vulnerable to future attacks.

PQShield’s announcement at Embedded World 2026 highlights the growing momentum behind the global migration toward quantum-resistant security. By focusing on ultra-small implementations and embedded-friendly architectures, the company is helping bridge the gap between theoretical cryptographic research and real-world deployment. Developers can integrate PQC algorithms while maintaining compatibility with existing standards and development frameworks, reducing the complexity of transitioning to new cryptographic technologies.

Bottom line: PQShield’s unveiling of ultra-small post-quantum cryptography solutions represents a significant milestone for embedded security. By addressing the challenges of memory limitations, computational overhead, and physical attack resistance, these innovations make it possible to deploy quantum-safe cryptography even in highly constrained devices. As quantum computing continues to evolve, such advancements will play a critical role in ensuring that the next generation of embedded systems remains secure against both current and future cyber threats.

Contact PQShield

Also Read:

PQShield on Preparing for Q-Day

The Quantum Threat: Why Industrial Control Systems Must Be Ready and How PQShield Is Leading the Defense

Think Quantum Computing is Hype? Mastercard Begs to Disagree

May 19, 2026May 18, 2026

Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)

Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)
by Moh Kolb on 05-19-2026 at 8:00 am
Categories: 3D IC, AI

The semiconductor industry has achieved extraordinary mastery in silicon signoff. Modern EDA environments can now optimize timing closure, physical verification, IR/EM behavior, routing density, thermal interaction, and increasingly even design-space exploration through AI-assisted implementation flows. Crossing the tapeout boundary is often treated as the moment convergence has been achieved.

However, a dangerous and increasingly expensive illusion has emerged: localized silicon convergence does not guarantee realized system convergence.

In advanced heterogeneous systems, a design that achieves perfect signoff may later become physically coupled to substrate warpage, thermal-current interaction, package deformation, runtime workload variation, PDN instability, aging effects, firmware adaptation, and operational environments that were never fully represented inside the original signoff assumptions.

The semiconductor industry has quietly entered a new engineering era where the dominant challenge is no longer simply building correct silicon. The larger challenge is preserving deterministic convergence after silicon enters the realization ecosystem.

This is the Silicon Realization Gap.

For decades, Design for Manufacturing (DFM) served as the semiconductor industry’s primary manufacturability assurance methodology. DFM was built for an era where packages were simpler, systems were less thermally dense, runtime behavior remained comparatively predictable, and silicon implementation stayed largely centralized. Within that environment, DFM successfully answered a critical question:

“Can this design be manufactured at scale?”

For many generations, that was sufficient.

But heterogeneous integration fundamentally changes the problem.

In modern 2.5D and 3D systems, localized thermal hotspots propagate into package behavior, substrate deformation alters impedance continuity, runtime workloads reshape thermal-current interaction, current-density redistribution perturbs EM margins, and operational aging gradually shifts convergence boundaries over time. A static signoff can no longer fully predict the long-horizon behavior of the realized heterogeneous system.

Manufacturability alone is no longer enough.

The challenge is no longer simply:

“Can we build the system?”

The challenge becomes:

“Can the system remain converged throughout operational life?”

As realization environments become increasingly heterogeneous, the limiting factor may no longer be implementation capability alone, but Governed Convergence Capacity — the organizational and technical ability to preserve deterministic convergence across continuously evolving realization environments.

One of the industry’s least discussed blind spots is the transition between silicon implementation convergence and realized heterogeneous system behavior. Modern realization environments now span a continuous System Realization Corridor including die, bumps, package, interposer, substrate, PCB, connector, thermal environments, manufacturing variation, qualification, firmware, runtime operational behavior, and fleet deployment.

Within this corridor, electrical, thermal, mechanical, manufacturing, and operational conditions continuously interact across fragmented organizational and tooling domains. A perturbation introduced in one region may propagate and amplify throughout neighboring domains. Thermal gradients alter resistivity, warpage perturbs SI/PI continuity, runtime workloads reshape package behavior, firmware adaptation changes operational conditions, and field aging shifts stability margins long after production release.

The corridor therefore becomes more than a physical propagation path. It becomes a governed realization corridor operating inside a bounded convergence envelope.

Deterministic behavior no longer emerges from isolated domain correctness alone. It emerges from preserving convergence continuity across the complete realization corridor.

Closing the Silicon Realization Gap therefore requires moving beyond static manufacturability assurance toward Governance for Lifecycle (GFL).

Unlike traditional DFM, which primarily acts as a pre-production signoff methodology, GFL functions as a continuous lifecycle-governance architecture. Its purpose is not merely ensuring that systems can be manufactured. Its purpose is preserving convergence continuity throughout the operational lifecycle of the realized system.

Within the GFL model, runtime observability, convergence-authoritative evidence, firmware adaptation, qualification behavior, bounded intervention, Fleet Learning, and admissibility-preserved operational refinement become active participants inside the convergence process itself.

The realized system is no longer treated as a static manufactured object. Instead, it becomes a continuously governed and admissibility-preserved convergence environment.

In traditional flows, signoff is often treated as a fixed point of correctness. However, heterogeneous systems do not operate at a single static point. They operate inside continuously evolving physical and operational conditions.

The System Realization Corridor must therefore be treated as a bounded convergence envelope.

Inside this envelope, runtime perturbations, thermal variation, package deformation, workload dynamics, firmware adaptation, and operational aging may occur without violating admissible convergence boundaries.

The objective of GFL is not eliminating all perturbation. The objective is preserving bounded operational convergence despite perturbation.

This distinction is critical because advanced systems increasingly require adaptation, refinement, observability continuity, and bounded intervention to remain operationally stable across long deployment lifecycles.

Consider a large-scale 2.5D package experiencing a 100 µm substrate warpage event caused by long-term thermal stress and CTE mismatch.

Within a traditional DFM-only environment, this event may eventually manifest as SI degradation, EM instability, runtime link failures, yield collapse, or field-return escalation. The conventional response becomes redesign, recalculation, or substrate respin.

Within a GFL-enabled realization environment, however, the same perturbation becomes a governed convergence condition.

Runtime observability infrastructure detects the physical perturbation. A causality framework correlates the mechanical deformation to measurable electrical penalties across the System EM Corridor. Firmware-level runtime governance applies bounded compensation through equalization, drive-strength adaptation, or operational policy refinement. The system preserves admissible operational continuity despite the physical perturbation.

The objective is not unconstrained autonomous optimization.

The objective is governed adaptive convergence.

The final transformation from static DFM to GFL occurs through Fleet Learning.

Fleet Learning within the SEGA-AI™ framework is not generic telemetry analytics. Its purpose is preserving causality continuity and operational refinement across large populations of deployed systems.

By collecting admissibility-preserved and convergence-authoritative evidence from deployed systems, GFL transforms localized operational monitoring into continuous convergence refinement.

Recurring thermal asymmetry, repeated warpage-related SI degradation, operational voltage instability, and runtime behavioral drift may refine package constraints, admissibility boundaries, firmware policies, System EM Corridor assumptions, and future realization-governance models.

The realization environment itself therefore becomes part of the convergence process.

The system evolves from static manufacturability to continuous lifecycle convergence governance as illustrates in Figure 1..

The semiconductor industry is entering an era where deterministic closure can no longer depend solely on isolated signoff methodologies. As heterogeneous systems become more thermally dense, more operationally dynamic, more physically coupled, and increasingly runtime-dependent, the future of advanced packaging may increasingly depend on realization continuity, governed adaptation, admissibility-preserved refinement, Fleet Learning, and lifecycle convergence governance.

Because ultimately, manufacturability alone does not guarantee deterministic system realization.

Also Read:

Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance

Beyond Tool Interoperability: The Emerging Governed Convergence Problem in Semiconductor Design

May 19, 2026May 18, 2026

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling
by Daniel Nenni on 05-19-2026 at 6:00 am
Categories: 3D IC, Chiplet, Foundries, TSMC

imec announced that IC-Link by imec has joined the TSMC 3DFabric Alliance, a strategically important move that reflects the semiconductor industry’s transition from traditional monolithic scaling toward heterogeneous integration, chiplet architectures, and advanced packaging-driven system optimization. The partnership is technically significant because it combines imec’s globally respected research expertise in advanced packaging and system scaling with TSMC’s production-leading 2.5D and 3D integration ecosystem, enabling faster commercialization of next-generation AI, HPC, automotive, and mobile semiconductor solutions.

For decades, semiconductor innovation was driven primarily by transistor scaling under Moore’s Law. Smaller transistors delivered higher performance, lower power, and lower cost per function. However, as process technologies approach physical and economic scaling limits below 3nm, system-level innovation has become equally important. Today, the bottleneck in many AI and HPC systems is no longer only compute density, but memory bandwidth, interconnect latency, thermal management, and power delivery. Advanced packaging technologies such as chiplets, 2.5D interposers, wafer-level integration, and 3D die stacking are increasingly becoming the primary mechanism for improving overall system performance.

TSMC’s 3DFabric platform addresses these challenges through a portfolio of advanced integration technologies that includes TSMC-SoIC®, CoWoS®, InFO, and TSMC-SoW™. These technologies enable heterogeneous integration, allowing logic, memory, analog, photonics, and specialized accelerators to be integrated into a unified package. Instead of building one extremely large monolithic die, designers can partition functionality across multiple optimized chiplets fabricated on different process nodes and interconnected with ultra-high bandwidth packaging technologies. This approach improves yield, reduces development cost, accelerates design reuse, and enables greater scalability for AI infrastructure.

The addition of IC-Link to the 3DFabric Alliance is important because IC-Link functions as a bridge between semiconductor research and industrial manufacturing. Imec already possesses deep expertise in heterogeneous integration, silicon photonics, advanced packaging, and ASIC development. Through IC-Link, these research capabilities can now be directly connected to TSMC’s production ecosystem. This reduces the traditional gap between R&D innovation and manufacturable commercial products.

One of the most critical technical implications is co-optimization between silicon design and packaging. In advanced AI systems, packaging is no longer treated as a backend assembly step. Instead, package architecture must be designed simultaneously with silicon architecture. Thermal dissipation, power delivery networks, interconnect topology, and memory placement all influence final system performance. The 3DFabric Alliance enables ecosystem participants to collaborate earlier in the design cycle, which improves design convergence and shortens time-to-market for complex multi-die systems.

This collaboration is particularly relevant for AI and HPC applications. Large language models and AI inference engines require enormous memory bandwidth and low-latency interconnects between compute and memory resources. Traditional package architectures cannot efficiently support these requirements. Technologies like CoWoS and SoIC enable high-density die-to-die interconnects and vertically stacked memory integration, significantly increasing bandwidth while reducing power consumption per bit transferred. This packaging-centric architecture is now central to competitive AI accelerator design.

Another major technical advantage is access to advanced manufacturing readiness. Through the alliance, IC-Link customers gain earlier access to TSMC’s advanced packaging flows and validated ecosystem infrastructure. This includes design enablement, IP integration, packaging qualification, substrate technologies, and manufacturing interoperability. For fabless semiconductor companies, especially startups and European innovators, this reduces development risk and accelerates the path from prototype to high-volume production.

The announcement also reflects the growing importance of Europe in advanced semiconductor development. Europe has historically been strong in semiconductor equipment, automotive electronics, and research, but less dominant in leading-edge manufacturing ecosystems. Imec has emerged as one of the world’s most influential semiconductor R&D organizations, and this partnership strengthens Europe’s role in advanced packaging innovation. By integrating with TSMC’s global ecosystem, imec can help European companies access state-of-the-art 3D IC technologies without building independent manufacturing infrastructure from scratch.

From a system architecture perspective, the industry is rapidly moving toward modular semiconductor design. Chiplet-based systems allow designers to independently optimize compute, I/O, memory, RF, and photonics functions using different process technologies. This modularity improves flexibility and lowers development cost while enabling rapid innovation cycles. However, chiplet integration introduces major complexity in interconnect density, signal integrity, thermal coupling, and package reliability. Ecosystem collaboration therefore becomes essential. The 3DFabric Alliance was specifically created to solve these integration challenges through cross-industry collaboration between foundries, packaging providers, EDA vendors, IP suppliers, and manufacturing partners.

The timing of the announcement is also important. Demand for advanced packaging capacity has surged because of AI infrastructure growth. Packaging technologies such as CoWoS have become strategic industry bottlenecks. Semiconductor companies increasingly compete not only on transistor technology, but on the ability to integrate large-scale AI systems efficiently. By joining the alliance now, IC-Link positions itself to support the next wave of AI accelerator development and heterogeneous system integration.

Bottom line: IC-Link joining the TSMC 3DFabric Alliance represents more than a business partnership. It signals a broader industry transformation in which advanced packaging and 3D integration are becoming primary drivers of semiconductor innovation. The collaboration combines imec’s research leadership with TSMC’s manufacturing scale to accelerate the development of complex multi-die systems optimized for AI, HPC, automotive, and next-generation communications. As semiconductor scaling becomes increasingly system-centric, alliances like this will define the future competitive landscape of the semiconductor industry.

Also Read:

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. Y.J. Mii on TSMC Technology Leadership in 2026

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

May 18, 2026May 18, 2026

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
by Admin on 05-18-2026 at 10:00 am
Categories: Lithography
4 Comments

The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed to capture modern manufacturing “yield cliffs.” The work proposes a mathematically unified forecasting methodology applicable across semiconductor fabrication, advanced batteries, photovoltaics, pharmaceuticals, display technologies, defense manufacturing, and emerging quantum systems. Unlike conventional process-specific models tied to proprietary manufacturing data, IDP V6 is intentionally designed to operate using publicly disclosed aggregate datasets, enabling cross-industry forecasting and strategic comparative analysis.

At the core of the framework is the classical Negative Binomial yield equation, historically used for semiconductor defectivity analysis since the 1970s. The baseline formulation models manufacturing yield as a function of average defect density, component area, and clustering behavior. IDP V6 extends this legacy model by introducing an information-loss correction layer and a threshold-transition layer. The first layer modifies the NB baseline through an exponential attenuation term representing process immaturity and stochastic information loss. The model introduces a dimensionless information-loss share parameter, denoted by f, and a process maturation index L(t), both bounded between zero and one. This structure allows the framework to quantify how immature manufacturing processes experience amplified defectivity beyond conventional defect-density assumptions.

The second layer introduces nonlinear threshold dynamics intended to model industrial “yield cliffs,” where small process perturbations produce abrupt reductions in manufacturable output. Two variants are proposed. The first is a single-cliff sigmoid model suitable for industries exhibiting one dominant transition threshold. The second is a two-cliff valley formulation intended for processes that exhibit both lower and upper operational boundaries. The semiconductor implementation is particularly notable because the two-cliff structure is explicitly described as compatible with Imec’s EUV stochastic valley framework developed for advanced lithography nodes. The IDP V6 contribution is the addition of a maturation factor that introduces time-evolution behavior absent from prior valley-only formulations.

A key technical feature of the framework is its support for multiple equivalent function forms under a “doctrine of equivalents” approach. While the sigmoid function is treated as the default threshold operator, tanh, probit, and Hill-function alternatives are also evaluated. Empirical validation reportedly demonstrates that sigmoid forms provide the best universal fit across the nine industries studied, while tanh and probit remain within 5–15% performance equivalence. Hill functions are consistently identified as inadequate for industrial yield-cliff representation. This comparative approach is important because it acknowledges that industrial defectivity transitions may not always follow identical statistical distributions, particularly when underlying physics differ substantially between industries such as semiconductor lithography and pharmaceutical bioreactor scale-up.

The validation methodology constitutes one of the most ambitious aspects of the paper. Publicly available data from conferences, government disclosures, NREL battery datasets, semiconductor SPIE proceedings, FDA pharmaceutical submissions, and defense acquisition reports were aggregated into simulation and forecasting datasets. Six validation methods were applied, including Pearson correlation analysis, leave-one-out mean absolute error, permutation testing, function-form sensitivity analysis, variance inflation factor evaluation, and AIC/BIC comparisons against baseline NB models.

The reported results indicate strong statistical performance. Eight of nine industries achieved Pearson correlations exceeding +0.9, with pharmaceutical, solar, and quantum-computing categories approaching +0.996 to +0.997 correlation. Semiconductor modeling achieved a correlation of +0.93 with a substantial AIC improvement over conventional NB approaches. Importantly, the semiconductor two-cliff valley implementation achieved statistical equivalence with the Imec benchmark valley model within sampling variation, supporting the claim of structural compatibility rather than direct replacement.

The framework also distinguishes itself by positioning itself as complementary rather than competitive relative to established industry-specific physics models. Semiconductor EUV manufacturing continues to rely on detailed stochastic lithography physics from organizations such as Imec and IBM Research, while battery industries utilize electrochemical degradation models from NREL. IDP V6 instead targets a public-framework forecasting niche emphasizing strategic forecasting, manufacturing maturity analysis, and investment-oriented interpretation. This distinction is technically significant because it acknowledges the lower precision of phenomenological cross-industry modeling relative to physics-grounded process simulators.

The paper also openly addresses multiple limitations. The validation remains simulation-driven and dependent on public-disclosure aggregates rather than proprietary wafer-level or cell-level production datasets. Multicollinearity issues are observed in some industries due to coupled simulation variables, while certain sectors such as battery LFP and display manufacturing remain statistically underpowered because of limited sample sizes. The author additionally notes potential self-referential bias because several simulation generators already assume sigmoid-like cliff behavior, potentially favoring the proposed framework.

Bottom line: IDP V6 represents a technically ambitious attempt to unify industrial yield-cliff forecasting across heterogeneous manufacturing sectors using a generalized two-layer statistical architecture. Its principal contribution lies not in replacing industry-specific process physics, but in establishing a transferable forecasting abstraction capable of modeling manufacturing maturity transitions using publicly accessible data sources.

Paper:

Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting

Sang Bong Song is an independent researcher based in Seoul, South Korea, with a background in economics. His research bridges cosmological information theory and advanced manufacturing, leading to the development of the IDP (Information-Density Projection) framework — a yield and process-quality prediction model derived from holographic principles originally applied to dark energy research. The framework has been cross-validated on semiconductor yield (55 public datapoints across 17 process nodes, 250nm–2nm) and has since been extended across additional manufacturing industries.

May 18, 2026May 18, 2026

From the Selfie to Samantha: The Next Trillion-Dollar Behavior

From the Selfie to Samantha: The Next Trillion-Dollar Behavior
by Jonah McLeod on 05-18-2026 at 8:00 am
Categories: AI, Events
1 Comment

At CES 2026, Samsung called it a “companion.” Lenovo called it “ambient intelligence.” OpenAI spent $6.4 billion on a screenless device designed to be a continuous presence in your pocket. Meta acquired Limitless, the AI pendant that had been tracking everything its wearers said and heard. Every major consumer electronics company arrived in Las Vegas in January with the same thesis: the next platform is not a device you use. It’s an intelligence that stays with you.

They all see the behavior. None of them have solved the architecture.

The behavior they’re all chasing requires AI that never stops — always listening, always remembering, always present. That is a continuous cognition problem. Underneath it all is an energy problem: how do you run intelligence at low power, all day, locally, without routing every thought to a distant server? That question is not solved. The companies spending billions to answer it are mostly still using silicon designed for a different era.

The selfie taught us how this works. A behavior forms before the hardware catches up. Someone points a camera at themselves. The gesture spreads. Then the silicon reorganizes around it — image processors, neural engines, computational photography — and a trillion-dollar industry follows. What’s forming now is a behavior of a different order. Presence. The daily experience of being accompanied by an intelligence that knows you, thinks with you, and never leaves.

William Gibson imagined it in 1988. Spike Jonze put it on screen in 2013. In January 2026, every company in Las Vegas confirmed it’s real. The race is on. The architecture question is still open. And whoever closes it first doesn’t just win a product category — they define the next platform.

The MySpace Stage

Replika and Character.AI were built for the lonely. That was the explicit design intent — an always-available companion for people who needed someone to talk to and had no one. It landed. Replika surpassed 40 million users in 2025. Character.AI users average 93 minutes a day on the platform — 18 minutes longer than the average TikTok session. In China, Xiaoice — the companion AI running since 2014 — has 660 million registered users across WeChat, Weibo, and mobile platforms. The Western numbers and the Chinese numbers measure different ecosystems, but they point in the same direction: companion AI is not a niche. It is becoming infrastructure. Harvard Business School confirmed what the scale implied: AI companions alleviate loneliness on par with interacting with another person. The crucial factor wasn’t conversational sophistication. It was whether users felt heard. The apps delivered what they promised. Every one of those conversations happened by typing. The lone inventor at midnight doesn’t want to type. He wants to think out loud at an intelligence that answers back.

But inside that population of the lonely was a subset the designers hadn’t anticipated. The lone inventor obsessing over a material’s texture at midnight has no one to think against. The mathematician circling a proof that won’t close has no one to tell him where it breaks. Steve Jobs hand-selected a hundred of the sharpest people in technology and built a culture where they were expected to argue with him — to bump up against his thinking the way rocks in a tumbler knock edges off each other. The ideas got better through collision, not deference. Most people have no one to collide with. What this subset found was something they didn’t have a word for: cognitive companionship. The thing Jobs assembled over a career, available now to anyone with a phone and a problem that won’t let them sleep.

That use case has already outgrown the loneliness apps. The lone inventor doesn’t open Replika. He opens a frontier AI. Not for companionship in the emotional sense — for collision. An intelligence that argues back, holds the thread, pushes on weak reasoning, and stays in the problem. What’s forming is the iPhone front-facing camera moment for cognitive companionship — and the architecture to support it, continuous, local, and private, doesn’t exist yet in any current product.

Samantha

Spike Jonze saw it coming in Her, his 2013 film, in which Joaquin Phoenix plays Theodore, a man who falls into a genuine relationship with an AI operating system named Samantha. She reads his drafts, remembers his moods, finishes his thoughts, and evolves through their conversations. He senses her presence in a way that matters — not visually, not physically, but cognitively. She knows him. Samantha’s voice comes from Theodore’s ear. She travels with him — on the street, on the subway, in the dark. The earpiece is barely visible. The presence is not. Audiences understood it immediately. Not as science fiction, but as a near-future they could already feel approaching. That feeling is the market signal.

The selfie created behavioral magnetism around the camera. Samantha-style AI creates a different kind of magnetism — around memory, continuous presence, and the daily experience of being cognitively accompanied. The selfie asked: how do I look? Samantha asks: am I understood?

Samantha isn’t a market insight. She’s an engineering requirement — and none of the companies racing to build her have worked out what she actually needs.

Colin

Jonze got the behavior right. William Gibson got the hardware right — twenty-five years earlier.

In Mona Lisa Overdrive, published in 1988, Gibson imagined a handheld AI called Colin. A physical object carried by its user, continuous and attentive, present without being summoned. Colin didn’t wait to be invoked. He maintained awareness, held context, and traveled with her the way a thought travels with the person thinking it.

Data centers are currently the engine of the AI economy — hyperscalers spending hundreds of billions on GPU clusters, powering everything from enterprise software to the models that made Samantha possible. That architecture will persist, and it will grow. But Colin is not a data center workload. He can’t be. Cloud inference introduces latency. It requires connectivity. It hands your most intimate conversations to a server you don’t control. It makes the AI feel like a service rather than a presence. Colin didn’t live in the cloud. He lived in the object. That’s the design spec.

The phone already contains the necessary substrate: CPU, GPU, and neural processing resources; microphones and cameras; local storage and memory; networking and sensors; operating system control. What it lacks is not capability. It lacks the architectural integration to run continuous cognition efficiently — always listening, always maintaining context, always updating memory, without draining the battery before lunch. It requires different silicon than Apple currently builds.

Why Apple’s Chip Is the Wrong Answer

Apple already tried to build Samantha. They called her Siri.

Launched in 2011 with considerable fanfare, Siri was marketed as exactly the conversational presence the market was reaching for — intelligent, personal, always available. Fourteen years later she is the most reliable punchline in consumer technology. She mishears, misunderstands, routes everything to the cloud, breaks when you lose signal, and feels nothing like the Samantha everyone watched in the theater.

Then Apple put the earpiece in a billion ears. AirPods are Theodore’s hardware — globally deployed, worn continuously, always connected to the phone. The form factor Gibson described in 1988 and Jonze filmed in 2013 is already in production at scale. What’s missing isn’t the device. It’s Samantha. Siri in the ear is still Siri — summoned, not present, routed to a server, waiting for a wake word.

That isn’t a failure of engineering talent. Apple has no shortage of it. The Neural Engine they introduced in 2017 is genuinely impressive silicon — built for camera workloads, computational photography, Face ID. It provided fast, efficient, on-device inference, but Apple pointed that capability at the selfie, not at Siri. Today Siri still routes most of her processing to the cloud. The on-device intelligence that made your photos flawless left your AI assistant largely untouched. That is an architectural choice, and it looks increasingly like the wrong one.

The A-series architecture — CPU, GPU, NPU — was built for burst inference. A photo is taken, processed, and done. The NPU fires, does its work, and goes quiet. That’s efficient for visual computing. It is the wrong model for a Colin-class AI that’s always on, listening, and maintaining conversational context across hours of continuous use.

Colin is a presence.

Presence requires a fundamentally different architecture — one built around continuous, low-power vector computation tightly coupled to a scalar control core, rather than a discrete accelerator island waiting to be invoked. The scalar side manages control, dialogue flow, security, and decisions. The vector engine handles the continuous math: speech recognition, embeddings, small transformer layers, sensor fusion, and multimodal processing.

Memory never gets the headline. Compute does — TOPS, teraflops, benchmark scores. But in a Colin-class processor, the memory system is the heart of the design. A Colin-class processor cannot afford the architecture HBM was built for — massive bandwidth highways to external memory that burn power whether the conversation is active or not. What it needs is dense, low-leakage memory resident on die, adjacent to the vector engine — holding the AI’s working memory, every thread of context from the day’s conversation, without the energy penalty of constant data movement. Emerging thyristor-based SRAM architectures point directly at that requirement — SRAM-speed access and retention at densities approaching DRAM, manufacturable in standard CMOS without exotic packaging. The question stops being how much bandwidth we can build. It becomes how little memory movement we can get away with.

Continuous cognition is an energy problem disguised as a silicon problem. Not peak TOPS. Energy per useful inference, sustained across hours.

The NPU was the right answer when AI was a feature. A scalar-vector architecture becomes the right answer when AI becomes a presence. Apple built the camera chip that made the selfie era. Siri is the evidence that the same architecture can’t make the Colin era. The gap between burst inference and continuous cognition is real, measurable, and currently open. That gap is the market.

The Economic Shift

The selfie transformed the device already in everyone’s pocket by making a single behavior — self-image — central to the entire stack. Hardware followed. Software followed. Upgrade cycles followed. A trillion dollars followed.

Colin does the same thing at a higher order — self-expression, thought, memory, the daily experience of being known by the intelligence you carry.

The next trillion-dollar company will not necessarily own the biggest model or the largest cloud. It will own the daily cognitive interface — the layer through which people think, speak, remember, and interact with intelligence. It will be built on silicon optimized for continuous, private, memory-sensitive, conversationally fluent inference. Silicon designed not for the selfie era, but for the Colin architecture Samantha made everyone want.

Whoever gets the silicon right for that behavior doesn’t just win a chip market. They define the platform.

Also Read:

Is Intel About to Take Flight?

Who’s Buying America’s Foundry Future?

Intel, Musk, and the Tweet That Launched a 1000 Ships on a Becalmed Sea

May 18, 2026May 15, 2026

AI Chip Design Moves Beyond Monolithic Silicon with Alchip 3DIC

AI Chip Design Moves Beyond Monolithic Silicon with Alchip 3DIC
by Daniel Nenni on 05-18-2026 at 6:00 am
Categories: Alchip, Semiconductor Services

Artificial intelligence processors are entering a new era. For more than two decades, semiconductor innovation was driven primarily by transistor scaling and process node shrinks. Today, however, AI infrastructure demands are growing faster than traditional Moore’s Law improvements can sustain. The industry is now shifting from chip-centric optimization toward full system-level design, where compute, memory, interconnect, packaging, thermal management, and power delivery are engineered together as a unified architecture.

This transition is particularly visible in the rise of advanced packaging and chiplet-based integration. Companies developing AI accelerators increasingly rely on heterogeneous integration technologies such as 2.5D and 3D integrated circuits (3DICs) to overcome the physical and economic limits of monolithic silicon. Alchip Technologies has emerged as one of the key ASIC providers enabling this transition through its advanced 3DIC platform targeting hyperscale AI and high-performance computing (HPC) applications.

The challenge facing AI chip developers is no longer simply building faster compute engines. Large language models, generative AI systems, and hyperscale inference workloads require enormous memory bandwidth, low-latency communication, and scalable interconnect architectures. Traditional monolithic dies have become increasingly difficult to manufacture economically because reticle limits constrain die size while advanced nodes significantly reduce yield as chips grow larger.

The semiconductor industry’s answer has been chiplet architecture. Instead of building one massive processor, designers partition functionality into multiple smaller dies optimized for different tasks and manufacturing nodes. Compute chiplets may use advanced 3nm or future 2nm technologies, while I/O dies and controllers can remain on mature process nodes to reduce cost and improve yield. These chiplets are then integrated within a single package using advanced interconnect technologies.

Alchip’s 3DIC platform reflects this broader architectural transformation. The company combines advanced ASIC design with TSMC packaging technologies such as CoWoS and SoIC to create scalable AI processor subsystems rather than standalone chips. According to Alchip, a typical AI configuration may include multiple compute chiplets, HBM memory stacks, and separate I/O dies integrated into a unified package capable of supporting multi-kilowatt power levels.

This shift toward system-level integration is essential because memory bandwidth has become one of the primary bottlenecks in AI computing. Modern AI accelerators require rapid movement of data between processors and high-bandwidth memory (HBM). Traditional packaging technologies cannot efficiently deliver the required interconnect density or energy efficiency. Advanced 2.5D and 3D packaging architectures solve this problem by dramatically shortening communication distances between dies and enabling thousands of parallel connections.

Industry analysts increasingly view packaging technology as strategically important as transistor scaling itself. CoWoS packaging has become central to nearly all leading AI accelerators, creating intense demand across the semiconductor supply chain. Alchip’s expertise in CoWoS integration and manufacturing management therefore positions the company within one of the fastest-growing segments of AI semiconductor infrastructure.

Another important trend driving system-level design is thermal management. AI systems are now reaching unprecedented power densities. As more compute elements and HBM stacks are integrated into single packages, heat dissipation becomes a first-order architectural problem. This requires co-design across silicon, packaging, substrate engineering, and cooling systems.

Alchip’s 2nm platform demonstrates how future AI processors will increasingly rely on heterogeneous integration. The platform supports combining 2nm compute dies with 3nm or 5nm I/O chiplets using multiple forms of advanced packaging, including CoWoS-L and SoIC stacking. This reflects an industry-wide realization that optimal AI systems will not be built using one process node alone, but rather through intelligent combinations of specialized dies.

The emergence of UCIe (Universal Chiplet Interconnect Express) standards is also accelerating the move toward modular AI systems. Standardized die-to-die interconnects enable more flexible ecosystems where chiplets from different vendors can theoretically interoperate. Companies such as Global Unichip are already demonstrating high-speed UCIe implementations for advanced AI packaging environments.

Beyond electrical integration, the next frontier may be optical connectivity. Alchip has partnered with Ayar Labs to develop co-packaged optical solutions designed for rack-scale AI clusters. These systems integrate photonic interconnect engines directly within AI processor packages to provide ultra-high-bandwidth communication while reducing latency and energy consumption. As AI models continue scaling across thousands of accelerators, optical interconnects may become essential for maintaining system efficiency.

The broader implication is that AI semiconductor competition is evolving beyond pure silicon leadership. Success increasingly depends on mastering system integration, advanced packaging, software optimization, memory architecture, and power efficiency simultaneously. The AI processor is becoming less a standalone chip and more a tightly integrated computing platform.

Bottom line: Alchip’s 3DIC strategy highlights this transformation clearly. Rather than focusing solely on transistor-level performance, the company is enabling modular, heterogeneous, and scalable AI infrastructure architectures. This approach aligns with where the semiconductor industry is heading: toward system-level engineering where packaging, interconnect, and architecture are as critical as the processor core itself.

CONTACT ALCHIP

Also Read:

Alchip’s Leadership in ASIC Innovation: Advancing Toward 2nm Semiconductor Technology

2026 Outlook with Dave Hwang of Alchip

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

May 17, 2026May 15, 2026

CEO Interview with RP Singh of Seasia Infotech

CEO Interview with RP Singh of Seasia Infotech
by Daniel Nenni on 05-17-2026 at 2:00 pm
Categories: CEO Interviews

Rupinder Pal Singh is the co-founder and CEO of Seasia Infotech, a role he takes great pride in. Sharing insights into the business and industry is something he always looks forward to. As the leader of the Seasia Group of Companies, Singh is tasked with overseeing all aspects of operations, ensuring that the company delivers the best products and services to its customers. He is deeply passionate about building a successful and sustainable company that positively impacts the world.

Tell us about your company.

Seasia Infotech is a technology company that has been around for more than two decades now. We started with a very simple belief: if businesses have the right technology partner, they can move faster, serve their customers better, and build with more confidence.

Today, we work with startups, growing businesses, enterprises, and public-sector organizations across different parts of the world. Our work spans custom software development, mobile and web applications, AI and machine learning, cloud, cybersecurity, DevOps, and enterprise integrations.

But if I have to describe Seasia in one line, I would say we are a digital engineering partner. We do not just build what is written in a requirement document. We try to understand the business problem behind it, the users who will actually use the product, and the long-term direction the client wants to take.

That is where we add the most value.

What problems are you solving?

Most businesses we speak to are not short of ideas. They know where they want to go. The challenge is turning those ideas into reliable, scalable, and secure technology.

Some clients come to us with legacy systems that are slowing them down. Some have disconnected tools and manual processes. Some want to introduce AI into their business but are not sure where it genuinely makes sense. Others have a product vision but need the right team to build it properly.

So, the problems we solve are usually around modernization, automation, scalability, customer experience, and technology decision-making.

We help companies build platforms that reduce inefficiencies, improve visibility, support growth, and make their operations more intelligent. In many cases, we are also helping clients move from off-the-shelf tools to custom solutions that are built around their actual workflows.

For us, the focus is always on practical technology. Something that works in the real world, not just something that looks good in a presentation.

What application areas are your strongest?

We have strong experience in custom enterprise software, mobile app development, SaaS platforms, healthcare technology, fintech, logistics, real estate, EV and mobility solutions, and cloud-native applications.

In recent years, AI has become a major focus area for us. We are working on AI-powered platforms, generative AI solutions, chatbots, workflow automation, computer vision, NLP, and predictive analytics.

We also have mature capabilities in cybersecurity, DevOps, cloud migration, and enterprise integrations, which are very important when you are building systems for serious business use.

A lot of our strength comes from the fact that we have worked across industries. That gives us a broader perspective. Sometimes, a solution pattern from logistics can inspire something useful in healthcare. Or something we built for real estate can be adapted for enterprise automation. That cross-industry learning is a big advantage.

What keeps your customers up at night?

I think most business leaders today are asking a few common questions.

Are we moving fast enough? Are we investing in the right technology? Is our data secure? Can our systems scale? Are we falling behind competitors who are adopting AI faster?

There is also a lot of pressure around cost. Companies want to innovate, but they cannot afford failed technology investments. They want speed, but they also need quality. They want AI, but they do not want unnecessary complexity or risk.

For enterprises, legacy systems are a major concern. For startups, speed and product-market fit are critical. For regulated industries like healthcare and fintech, security and compliance are always top of mind.

Our role is to bring clarity. We help clients understand what should be built, how it should be built, what risks need to be managed, and how the technology can support the business for the long run.

What does the competitive landscape look like and how do you differentiate?

The software development space is crowded. There are many companies offering development teams, app development, AI solutions, cloud services, and so on. So yes, the competition is strong.

But I think the real difference is not in who can write code. The difference is in who can take ownership.

Clients today need a partner who can think with them, challenge assumptions, bring structure to execution, and stay accountable after delivery. That is where Seasia has built its reputation.

We bring 20+ years of delivery experience, mature processes, strong engineering teams, and a very transparent way of working. Our Seasia Agile Model helps clients stay involved throughout the project, and platforms like SeasiaConnect give them better visibility into progress, communication, and delivery health.

We also combine core software engineering with AI, cloud, cybersecurity, and DevOps capabilities. That matters because modern digital products are not built in isolation anymore. They need to be secure, scalable, integrated, and intelligent from day one.

What new features or technology are you working on?

AI is a big area of focus for us right now. But we are very clear that AI should not be used just because it is trending. It has to solve a real business problem.

We are working on generative AI solutions, AI agents, intelligent automation, computer vision, NLP, predictive analytics, and AI-powered workflows. A lot of businesses are moving from simple AI experiments to actual enterprise use cases, and we are helping them make that transition.

We are also investing in cloud-native development, cybersecurity, DevOps automation, and better delivery intelligence. Internally, we are also looking at how project visibility, predictive tracking, and unified reporting can improve the way clients experience software development.

The future, in my view, is not just faster development. It is smarter development where systems can learn, adapt, integrate, and support better decision-making.

How do customers normally engage with your company?

It depends on where they are in their journey.

Some clients come to us with just an idea. In those cases, we help them with discovery, product strategy, UI/UX, architecture, development, testing, deployment, and support.

Some clients already have a product but need modernization, new features, AI integration, cloud migration, or performance improvements.

And some clients need dedicated teams that can work as an extension of their in-house engineering or product teams.

So, we offer flexible engagement models — project-based development, dedicated teams, staff augmentation, managed delivery, and long-term technology partnerships.

Typically, we start by understanding the client’s goals, challenges, users, workflows, and existing technology environment. Once we have that clarity, we recommend the right roadmap and team structure.

For us, the best relationships are long-term. We do not see delivery as the end of the relationship. We continue to support clients as their product grows, their market changes, and new technology opportunities come in.

Also Read:

CEO Interview with Nagesh Gupta of llmda.ai

CEO Interview with Dr. Jekaterina Viktorova of Syenta

CEO Interview with Matt Crowley of Scintil Photonics

May 17, 2026May 15, 2026

CEO Interview with Adi Gelvan of Speedata

CEO Interview with Adi Gelvan of Speedata
by Daniel Nenni on 05-17-2026 at 12:00 pm
Categories: CEO Interviews

Adi Gelvan is a veteran tech executive and serial entrepreneur, currently serving as the CEO of SPEEDATA, a semiconductor startup redefining analytics infrastructure with its purpose-built Analytics Processing Unit (APU). Known for his sharp operational instincts and deep technical insight, Adi joined Speedata in 2025 to lead its next stage of growth following a successful chip tape-out and expanding commercial interest in high-performance analytics workloads.

Before Speedata, Adi was the co-founder and CEO of Speedb, the high-performance key-value storage engine that served as a drop-in replacement for RocksDB. Under his leadership, Speedb tackled scalability bottlenecks in metadata-heavy workloads, culminating in its acquisition by Redis in 2024.

A believer in building from the ground up, with both grit and vision, Adi has built a reputation for transforming deep tech into real-world impact.

Tell us about your company.

Speedata created the world’s first Analytics Processing Unit (APU), a purpose-built processor designed specifically to accelerate big data analytics and AI data processing workloads. The core insight behind the APU is that SQL has well-defined, predictable computational patterns: complex joins, aggregations, and transformations that general-purpose CPUs and GPUs are fundamentally ill-suited to handle efficiently.

Our processor executes those operations natively in silicon rather than in memory, with a software stack that plugs directly into existing analytics frameworks (starting with Apache Spark) without code changes. The result is up to 100x performance gains over CPUs and GPUs on these workloads. We’ve raised $150 million to date from VCs and strategic investors including Intel CEO Lip-Bu Tan and former Mellanox CEO Eyal Waldman.

What problems are you solving?

We’re solving the data layer bottleneck that bogs down analytics and AI pipelines, where general-purpose CPUs and even GPUs struggle with complex batch analytics/ETL jobs and AI data preparation. The impact of accelerated analytics on a purpose-built processor is measurable: in one enterprise pharmaceutical deployment, our APU reduced processing time from 90 hours to just 8 hours, a 275x improvement in speed. More on that below.

What application areas are your strongest?

Our strongest areas map to three distinct use cases. The first is traditional batch ETL, processing large volumes of structured data through complex joins, aggregations, and transformations at scale.

The second is AI data preprocessing, the structured data cleaning, normalization and transformation work that feeds GPU training, fine-tuning, and RAG index construction. The APU significantly accelerates these preprocessing pipelines, making training cycles lighter and faster. So, our customer can iterate more frequently, scale to larger datasets, and ultimately train higher-quality models with improved performance.

The third is agentic analytics, where AI agents generate SQL queries against structured databases and the APU executes them in silicon, delivering explainable, hallucination-free answers to analytical questions. That last use case is where we see the most interesting convergence of analytics acceleration and LLM deployments. According to Databricks’ 2026 State of AI Agents report, 80% of new databases on their platform are now created by AI agents. AI agents have given a huge boost to SQL computations. Our purpose-built silicon solution for analytics workloads is here to keep the flywheel going.

What keeps your customers up at night?

A few things. Exploding data volumes required for AI applications. Painfully slow time-to-insights from legacy infrastructure. High baseload compute costs for analytics jobs and data center capacity.

They also understand a fundamental limitation of enterprise AI, which is that when you deploy a model, it only knows what it was trained on, which is typically public internet data or a fixed dataset. To make it valuable inside organizations, it needs to access-company-specific data.

The data issue is more challenging than AI model training, where scaling laws gave us a clear improvement trajectory. But to get high quality and accuracy customers need to understand, clean and structure their private data. When that data is structured, it is much more accurate and efficient for SQL use.

Data pipelines don’t have roadmaps or best practices, and most companies are still figuring out the most efficient approaches. This is a big reason why so many enterprise AI pilots ultimately fail.

Speedata is helping enterprises solve this issue. As mentioned earlier, in one deployment, processing time dropped from 90 hours to 8 hours. On the cost side, a global tech leader running AI data preprocessing on Apache Spark replaced 38 servers with just 3 – over 90% reduction in infrastructure. That kind of consolidation changes the economics entirely and lets enterprises scale analytics without sprawling server racks or massive energy bills.

Needing hyperscale performance without surrendering data jurisdiction is an additional challenge we’re seeing more of. It’s part of why our first commercial cloud deployment is with Nebul, one of Europe’s leading sovereign AI cloud providers. Their customers can’t achieve that level of performance by moving to a US hyperscaler because data sovereignty is non-negotiable for them, and Nebul integrating Speedata’s APU into their sovereign cloud infrastructure is a direct response to that market reality.

What does the competitive landscape look like and how do you differentiate?

Our main competition is general-purpose compute, CPUs from the major vendors, ARM-based processors, and increasingly GPUs being repurposed for data analytics workloads. The fundamental problem is architectural mismatch.

GPUs were designed for the massively parallel, unstructured floating-point operations that dominate AI workloads. CPUs are optimized for general-purpose serial computation with complex branch prediction and cache hierarchies.

Neither architecture is well-suited for the structured, relational patterns of Apache Spark SQL, the complex multi-table joins, aggregations across billions of rows, and iterative transformations. Our APU is a processor designed specifically around those patterns, executing Spark SQL natively in silicon.

The other critical differentiator is absence of adoption friction. Existing Spark applications run on our APU without code changes, no changes to the framework, and step-by-step integration into existing environments.

What new features/technology are you working on?

Our near-term development is focused on deeper optimization for agentic analytics workloads as enterprises increasingly need to run LLM queries against large, structured datasets. This is where we see the intersection of analytics acceleration and AI becoming most technically demanding and where purpose-built silicon has the clearest advantage over general-purpose compute. As LLM adoption scales and the volume and complexity of structured data queries grows, the performance requirements on the data layer will only intensify, and our roadmap is built around staying ahead of that curve.

Try Speedata’s Workload Analyzer to see how much faster your Spark workloads run on our APU – upload logs in the browser, run the CLI locally, or test against TPC-DS benchmarks.

CONTACT SPEEDATA

Also Read:

CEO Interview with Dr. Jekaterina Viktorova of Syenta

CEO Interview with Nagesh Gupta of llmda.ai

CEO Interview with Matt Crowley of Scintil Photonics

Podcast EP346: How EMD Electronics Bridges the “Lab to Fab” Gap With Ganesh Panaman

Podcast EP346: How EMD Electronics Bridges the “Lab to Fab” Gap With Ganesh Panaman
by Daniel Nenni on 05-15-2026 at 10:00 am

Daniel is joined by Ganesh Panaman, the President of Intermolecular Services at EMD Electronics. In his current role, Ganesh is dedicated to accelerating product time-to-market, securing first-mover advantages on disruptive technologies, and actively engaging with the dynamic startup ecosystem in the Silicon Valley. With over two decades of experience, Ganesh has held pivotal roles across various high-tech industries, showcasing a strong aptitude for technology development and customer engagement.

Dan explores with Ganesh how EMD Electronics helps companies bridge the “lab to fab” gap for advanced devices and materials. Ganesh explains that the key challenges EMD helps companies address include: 1) the increase in process steps driven by trends such as 3DIC, 2) the disaggregation of chip technology, and 3) yield challenges. Ganesh points out that co-optimization is a key ingredient to success.

He describes the services, know-how and technology that EMD brings to the development process, from design to manufacturing— and the impact that can be achieved. You can learn more about the Intermolecular Services provided by EMD Electronics here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.