SemiWiki – Page 6 – The Open Forum for Semiconductor Professionals

May 15, 2026May 15, 2026

TSMC’s Record Tool Orders Hint at Another CapEx Shockwave

TSMC’s Record Tool Orders Hint at Another CapEx Shockwave
by Daniel Nenni on 05-15-2026 at 8:00 am
Categories: Foundries, TSMC

TSMC’s latest Board of Directors capital appropriation announcement may appear mixed on the surface, but a closer look reveals one important conclusion: The company is quietly setting the stage for another potential upward revision to its already aggressive 2026 capital expenditure outlook. The headline figure of $31.3B in newly approved capital appropriations was below the massive $45.0B approved in the prior quarter, yet the composition of this spending tells a much more constructive story for the semiconductor equipment ecosystem.

The most notable development is the continued acceleration in Advanced Node equipment investment. TSMC approved approximately $21.0B of Advanced Node-related equipment spending this quarter, representing the highest quarterly authorization level since we began tracking the company’s BoD capital approvals in 4Q19. Even though total approved spending declined sequentially, the shift toward leading-edge wafer fabrication equipment indicates that TSMC’s strategic focus remains firmly centered on expanding advanced logic capacity.

This distinction matters. Infrastructure spending and specialty technology investments can fluctuate depending on timing, construction schedules, or packaging initiatives. Advanced Node equipment approvals, however, are a far cleaner signal of future semiconductor manufacturing activity. They directly correlate with purchases of lithography, process control, deposition, etch, and metrology systems required for ramping leading-edge nodes such as N2 and A16.

At the same time, there was a notable absence of new approvals for Specialty Devices and Advanced Packaging. Last quarter’s record approval in this category was later understood to be tied to silicon photonics, CoWoS, and SoIC-related investments. The lack of follow-on approvals this quarter should not necessarily be interpreted as weakening demand. Rather, it likely reflects the exceptionally large allocation already approved previously. Given the long lead times and substantial scale of advanced packaging infrastructure deployment, TSMC may simply be digesting prior commitments before authorizing another major tranche of spending.

Infrastructure spending also normalized this quarter. The $10.3B approval level was meaningfully lower than the record $21.4B authorized in the prior quarter. However, this moderation appears more cyclical than structural. Infrastructure allocations often fluctuate depending on the timing of fab shell construction, utility expansion, overseas manufacturing projects, and regional government incentives. The key takeaway is that infrastructure moderation did not come alongside any slowdown in Advanced Node investment intensity.

Perhaps the most important data point from this quarter is the emerging disconnect between approved future spending and TSMC’s current annual CapEx guidance. Assuming BoD capital appropriations generally represent roughly the next 12 months of spending activity, the trailing twelve-month Advanced Node equipment authorization level has now climbed to approximately $55.0B. That figure alone nearly matches TSMC’s entire current 2026 capital expenditure guidance of roughly $56B.

This creates an increasingly difficult mathematical setup. If Advanced Node equipment alone already represents nearly the full-year CapEx plan, then either spending cadence must slow materially in coming quarters or total CapEx guidance will need to move higher. Given current AI infrastructure demand trends, slowing investment appears unlikely.

The broader industry backdrop strongly supports the latter scenario. AI-driven compute demand continues to accelerate across hyperscale data centers, sovereign AI projects, enterprise deployments, and edge inference applications. Leading-edge silicon demand remains supply constrained, particularly for advanced GPUs, AI accelerators, networking ASICs, and high-bandwidth memory integration. TSMC remains the dominant manufacturing partner for virtually all major AI chip developers, placing extraordinary pressure on its advanced manufacturing capacity roadmap.

As a result, TSMC’s quarterly CapEx run rate likely needs to increase further over the next twelve months. The company’s N2 ramp, advanced packaging expansion, overseas fab deployment, and ongoing EUV intensity growth all point toward sustained elevated investment levels. This is why the probability of a 2026 CapEx raise at TSMC’s 2Q26 earnings conference call in July appears to be increasing.

Bottom line: The latest TSMC approval data reinforces a critical industry theme: despite periodic fluctuations in quarterly headline numbers, leading-edge semiconductor investment remains in a structural expansion phase. AI demand is fundamentally altering semiconductor infrastructure requirements, and TSMC’s capital allocation patterns continue to reflect that reality. In fact, the latest BoD approvals may ultimately be remembered less for the sequential decline in total authorizations and more as an early signal that TSMC’s current 2026 CapEx framework is already becoming too conservative.

Also Read:

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. Y.J. Mii on TSMC Technology Leadership in 2026

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

Dr. Cliff Hou and the TSMC N2 Process Technology

May 15, 2026May 19, 2026

CEO Interview with Nagesh Gupta of llmda.ai

CEO Interview with Nagesh Gupta of llmda.ai
by Daniel Nenni on 05-15-2026 at 6:00 am
Categories: AI, CEO Interviews, EDA, llmda.ai

Nagesh has built a career spanning multiple aspects of system design and development at companies including Hewlett-Packard, Cadence, Xilinx, and Lattice Semiconductor.

He is also a serial entrepreneur. Nagesh founded Taray, Inc., which developed memory interface generators for Xilinx designs and was later acquired by Cadence Design Systems. He also founded Auviz Systems, to accelerate Vision/ML algorithms for data center and embedded applications; Auviz was acquired by Xilinx.

About two years ago, Nagesh founded llmda.ai and became its CEO. His expertise spans startup development, product management, product development, and chip and hardware system design.

Tell us about your company

llmda is ushering in a new era for embedded systems development: chip dev, hardware/board dev and embedded software dev. Each of these domains is complex – and putting them all together is an order of magnitude higher in complexity. The gap between product requirements and product development artifacts has been a key reason for schedule slips. Data often turns out to be locally consistent but globally inconsistent. Schedule slips result in increasing the operating expenses and reducing the revenues generated. In fact, there’s a 33% revenue loss when a project is delayed by 6 months.

Why is this important to address? More than a third of Embedded Systems Designs is late to market by more than 50%. 75% of chip projects fall behind the original schedule. Only 14% of all chips in 2024 achieved first time success! The industry has tried to figure out the reason behind this. There have been several surveys conducted by research firms: Wilson Research/Siemens has consistently found that what is classified as “spec errors” due to the broken digital thread was a leading cause of logic and functional errors. 84% of ASIC projects now have an embedded processor and here Hardware/Software interface is a massive vector for failure. Changing specs and siloed teams are the leading cause.

Even with all the well-intended work by engineering teams, there’s a high percentage of data that drifts. The primary cause is the complexity involved. Just take chip design for example – even a simple digital chip has a team of at least 50 people distributed across geographies. And teams are generally separated into groups to address different domains – architecture, logic design, verification, physical design, and so on. Next, there’s the hardware (PCB) design teams and the embedded software teams.

Take a simple example of register space definition: a chip may contain tens of thousands of registers. Software is used to program these registers – you can see millions of possible combinations, hundreds to thousands of configuration spaces. A small difference in the definition is all it takes for the teams to drift apart. The amount of schedule slip depends on when the difference is found. With the current process, the question is not if there will ever be a drift. The question is when the drift will be detected.

Having worked in the industry for the past 30 years and seeing this firsthand, the advent of GenAI was a golden opportunity to solve this issue forever and eliminate this latent flaw. To me, the question was not only about building faster but building the right product faster.

llmda is backed by experts from EDA, Chip Design and GenAI and well-known valley investors: Emergent Ventures and Up Partners in the journey.

What problems are you solving?

Our goal is to eliminate schedule slips and thus reduce the operating expense and the time to market. Embedded systems development needs a highly specialized development requiring skilled engineers. The teams are often distributed among geographies and time zones. Even within a time zone, the teams are separated by several layers purely due to the size of the teams and the scope of problems teams are solving. The industry is expected to grow significantly. However, there’s also a significant shortage of talent to enable the industry to grow.

There is an industry, composed of incumbents as well as new startups that are innovating to shorten the chip design cycle through RTL generation, debug and verification help. To us the question is about “creating the product consistent with the intent”: not just about shortening the design cycle. Ensuring the product you are building is the right product is our goal.

What application areas are your strongest?

We focus on simple to complex semiconductor and embedded system development teams across all application domains – because the problem we are solving is universal. The question is only about the scale of the problem.

What keeps your customers up at night?

Three concerns dominate.

Design data to definition drift. In chip design/embedded system design, ensuring that the design is verified against the requirement before tape-out is critical. Fixing defects after tape-out can cost anywhere from several million dollars to more than $100 million.
Schedule slip. In silicon design and embedded system design, schedules generally don’t slip by weeks. Slips are measured in quarters and the visibility is generally poor. For example, everything continues as planned, but validation of the chip takes a very long time due to a simple issue like an incorrect register definition. Anyone who’s worked in this domain knows how hard it is to debug in real silicon!
Resource constraints – global design teams and a critical shortage of specialized resources.

What does the competitive landscape look like and how do you differentiate?

Many AI-assisted chip design efforts focus on generating RTL, verification code or providing co-pilot like features to debug faster. Several startups, along with all major EDA suppliers, are developing solutions in this area. These are all very useful and will impact the time taken to design and develop silicon.

llmda’s focus is to ensure what is designed is true to the intent. llmda is not only for teams that have adopted GenAI development tools, but also for teams that are still using the legacy toolset. llmda is about formally ensuring development data and artifact correctness and consistency.

What new features/technologies are you working on?

llmda will release a suite of products to address this space comprehensively. Immediately, llmda is addressing a very fundamental aspect with our llmda Spectra product: to automate generation of all technical documents consistent with design artifacts. This problem is universal and it touches every stage of development and product release. Lead engineers and architects spend up to 40% of time creating and maintaining documents & still teams get out of sync.

llmda has developed a documentation platform that is agentic, and with the user in the loop slashes document generation, maintenance and update times by up to 90%! llmda thus gives back time to the development team to do real Engineering and reduces time-to-market!

How do customers normally engage with your company?

llmda will be attending a growing number of industry events in the coming months. You can visit our website at https://www.llmda.ai to see where we will be exhibiting.

If you cannot attend one of these events, you can reach us directly at sales@llmda.ai to arrange a meeting where we can discuss our capabilities and explore how we can help address your system design challenges.

You can also follow our LinkedIn page to stay updated as we expand our product offerings.

llmda Emerges From Stealth with llmda Spectra™, bringing Agentic AI to Embedded Systems Development

May 14, 2026May 15, 2026

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox

The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox
by Daniel Nenni on 05-14-2026 at 10:00 am
Categories: EDA, Emulation, IP, Prototyping, RISC-V, S2C EDA

In the EDA world, “Shift-Left” has traditionally been a mantra for early software development—booting the OS before the silicon even leaves the fab. But as the RISC-V revolution accelerates, the goalposts have moved. We are seeing the emergence of a “New Shift-Left”, one that focuses on critical architectural decisions long before the first line of production RTL is frozen.

The logic is simple: Flawless execution doesn’t matter if you’re building the wrong product. Building the chip “right” is a technical requirement; building the “right” chip is a strategic one.

Strategy Over Execution: Designing the “Right” Chip

The industry has spent decades perfecting the art of “designing the chip right” —optimizing synthesis, closing timing, and ensuring verification coverage. While these are critical, they are execution-level tasks.

Today’s winners are decided at the specification phase. Choosing the wrong IP or miscalculating the performance requirements of a specific workload can lead to a “perfectly designed” chip that is dead on arrival in the market. In this “New Shift-Left,” the most important work happens at the IP selection stage. Just as a project’s success depends on setting the right goal rather than just the efficiency of the journey, a SoC’s success depends on the architectural choices made on day one.

Navigating the RISC-V “Paradox of Choice”

RISC-V has fundamentally changed the IP landscape. We are no longer limited to a few rigid, proprietary cores. Instead, we have a vibrant ecosystem of vendors offering everything from tiny, MCU-grade controllers to massive, high-performance computing (HPC) clusters with complex vector extensions.

This flexibility creates a paradox: When you can choose anything, how do you choose the right thing?

One size does not fit all. A core that looks great on a spreadsheet might struggle with your proprietary AI algorithm or fail to meet the latency requirements of your real-time data path. You need more than a datasheet to make a multi-million-dollar decision.

The “Test-Drive”: Prototyping as a Strategic Tool

This is where FPGA prototyping has evolved from a back-end verification tool into a front-end decision engine. It provides the high-performance sandbox needed to “test drive” various RISC-V variants with your actual software stack.

Real-World Benchmarking: Unlike simulation, which is too slow for meaningful software execution, FPGA prototyping runs at the speeds needed (often 20MHz to 100MHz+) to see how a core actually behaves.
Mixing in the “Secret Sauce”: RISC-V’s extensibility allows you to integrate a vendor’s IP with your own custom instructions or proprietary accelerators. You can validate the entire system-level operation before committing to a final architecture.
Data-Driven Selection: Instead of guessing which core variant fits your power and performance envelope, you can prove it. This “test drive” ensures that the core you select is exactly what your application needs.

The Economics of the Test-Drive: A Budgetary Shift

Interestingly, using FPGA prototyping for IP evaluation often shifts the budgetary conversation. Because these systems are being used as “test-drive” tools to validate product-market fit and IP viability, the cost often aligns better with “Sales & Marketing or Strategic Planning budgets” rather than strictly ASIC development budgets.

When a tool is used to “sell” a concept internally or to “verify” an IP purchase externally, finding a prototyping system that offers “exceptional value” is paramount. You need a platform that is robust enough for high-end engineering but cost-effective enough to be deployed as a versatile evaluation vehicle across different teams. High-end emulation is often too expensive and “stationary” for this role; a high-performance, modular FPGA prototyping system is the ideal middle ground.

S2C: Two Decades of Prototyping Excellence

When it comes to providing the “test-drive” platform for the RISC-V era, S2C stands as the industry veteran. With over 20 years of experience in the FPGA prototyping space, S2C has been a pioneer in helping designers bridge the gap between ASIC RTL and physical hardware.

Their latest flagship, the Prodigy S8-100, is built on the AMD Virtex™ UltraScale+™ VP1902 FPGA. It features a staggering 100 million equivalent ASIC gates per FPGA, providing the massive capacity required for today’s most complex SoC designs.

It is no coincidence that the Prodigy S8-100 has been widely adopted by leading RISC-V IP vendors, such as Andes, Xuantie, BOSC, Starfive, Nuclei. These vendors use S2C’s systems to showcase their latest features and performance to their own customers. If the IP creators trust S2C to demonstrate their “secret sauce,” you can trust it to validate yours.

Conclusion: The New Competitive Edge

The New Shift-Left is about de-risking the most expensive decision in chip design: IP selection. By leveraging the speed and flexibility of FPGA prototyping early in the cycle, architects can move past theoretical models and gain hard data on system performance.

In the RISC-V era, the competitive edge goes to those who don’t just move fast but move in the right direction. Use prototyping to ensure you aren’t just designing a chip well—you’re designing the right chip for the job.

CONTACT S2C

Also Read:

2026 Outlook with Ying J Chen of S2C

Accelerating Advanced FPGA-Based SoC Prototyping With S2C

There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?

May 14, 2026May 15, 2026

The Semiconductor Growth Numbers are Insane but the Real World Doesn’t Tally!

The Semiconductor Growth Numbers are Insane but the Real World Doesn’t Tally!
by Malcolm Penn on 05-14-2026 at 8:00 am
Categories: Future Horizons, Semiconductor Services
6 Comments

May’s WSTS Report saw March’s total monthly semiconductor sales up 88.1 percent vs. March 2025, albeit down 8.5 percent from February 2026. This month-on-month decline needs to put in the context of February’s record-breaking 25.7 percent monthly growth.

This growth, however, was solely attributable to ICs, up 99.5 percent year-on-year, more specifically to Memory, up 269.1 percent, and Logic, up 38.9 percent, each in turn driven by the still white-hot AI-datacenter explosion.

In sharp contrast, IC growth excluding Memory was just 28.3 percent, Analog 13.8 percent, and Micro 8.8 percent, with Opto up 12.3 percent, and Discretes up just 10.1 percent.

Annualised IC unit growth was relatively strong in March, up 20.3 percent vs. February’s 9.9 percent, but this does not detract from the fact the current stratospheric IC growth is being driven by ASPs, not real market demand. This, plus the fact it is severely AI Datacentre dependent, makes the current recovery untenable in the longer term. IC ASPs will drop like a rock when the datacentre boom slows, and the memory market will crash once new capacity comes on stream.

IC unit growth was also single digit, at just 9.9 percent, re-enforcing the fact the current stratospheric IC growth is being driven by ASPs, not real market demand. This, plus the fact it is severely AI Datacentre dependent, makes the current recovery untenable longer term.

ASPs will drop like a rock when the datacentre boom slows, and the memory market will crash once new capacity comes on stream.

At our recent IFS2026 industry webinar, we updated our outlook for the rest of this year. Given the current growth rates are wild, the numbers insane, with no clear baseline to underpin a consistent set of assumptions, we elected to provide a series of forecast guidance scenarios in lieu of our traditional forecast with bull and bear boundaries.

The likelihood of which scenario materialised depending on three factors, namely, the global economy, the AI boom and memory ASPs.

These in turn depend on how long the Middle East war hostilities and associated disruptions continue; if (when?) investor and AI market data centre exuberance wanes; and how soon new DRAM capacity comes onstream.

The net result was a potential market growth of anywhere from 13 to 101 percent.

The key difference between our view on the market and the overwhelming industry consensus is the impact of AI.

We do not accept that today’s AI boom represents a brave new world of AI-driven semiconductor reality, given AI chips account for between 25-50 percent of the total revenue, depending on how you count it, but significantly less than 1 percent of the total unit shipments.

The current boon may well be the second longest on record, with dollar growth rates to die for, but unit growth is abysmal and the non-AI markets struggling.

Whilst we absolutely believe AI will eventually transform the world as we currently know it, just as the car, air and rail travel, telecommunications, radio, TV, calculators, computers, the Internet and numerous other breathtaking inventions changed the way we live, work and play, we believe these all take time to materialise and the durable path of the associated technological evolution has yet to emerge.

We are the only analyst currently forecasting an industry downturn “maybe this year, if not, next” but we believe the risks are clear given the current market anomalies.

Unit growth is below the industry trend-line and market growth is being driven by ASPs not unit demand, which is unusual. It’s usually the other way round.

The industry’s recent dollar growth is alarmingly unprecedented with Q1-2026, normally the weakest quarter of the year, seeing quarter-on-quarter sales grow 25 percent. That is not only the strongest growth for Q1 over Q4 growth in the 70 plus year industry history, the first quarter growth average is minus 3 percent, it is the highest quarterly growth rate ever.

If datacenter investment weakens, AI chip sales will inevitably follow.

The more optimistic chip forecast current grabbing the headlines would see the chip market increase its share of the US$126 trillion world GDP market from 0.6 percent to 1.5 percent by 2035, growing three times as fast as the historical GDP growth rate, twice as fast as the pre-AI industry average, and with no slowdown in growth.

With all due respects, this is not going to happen. There will be a correction. Either AI demand will tank, or the infrastructure will not be able to keep pace with the demand.

Enjoy the current party but proceed with extreme caution. Do not be misled by current headline dollar growth numbers, they reflect ASP expansion, not underlying demand.

Malcolm Penn
Future Horizons
May 2026

Also Read:

Future Horizons Industry Update Webinar IFS 2025

Semiconductor Industry Update: Fair Winds and Following Seas!

The Recovery has Started and it’s off to a Great Start!

May 14, 2026May 13, 2026

SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era

SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era
by Kalar Rajendiran on 05-14-2026 at 6:00 am
Categories: AI, IP, SiFive

With the launch of its new P570 Gen 3 processor family, SiFive is making a broader statement about the future of edge computing and the growing role of RISC-V in mainstream application processors. Rather than simply unveiling another CPU core, the company is positioning the P570 as a balanced-performance processor built specifically for AI-era workloads.

The launch includes two processors: the P570 Gen 3 with vector support and the P550 Gen 3 without vector support. Both belong to SiFive’s “Performance” family and target Linux-class systems, Android-capable devices, edge AI platforms, consumer electronics, and embedded computing applications.

What makes the announcement significant is not just the performance uplift, but the architectural direction behind the design. SiFive is targeting a segment between low-power embedded processors and large server CPUs. This is a space where devices increasingly need AI acceleration, vector processing, and modern software support while still operating within tight power and silicon-area limits.

A New Kind of Edge Processor to Address a Market Gap

SiFive repeatedly described the P570 as a “balanced performance” processor, meaning it is optimized for performance-per-watt and performance-per-sqmm rather than peak benchmark scores alone.

That focus reflects how edge devices are evolving. Smart cameras, industrial systems, AI-enabled consumer electronics, and intelligent IoT devices increasingly run mixed workloads combining traditional CPU tasks with AI inference, media processing, and vectorized compute. These systems need far more capability than legacy embedded CPUs were designed to deliver, but they still cannot absorb the power and thermal costs of server-class processors.

SiFive argues that existing mid-range CPU architectures, particularly older Arm Cortex-A designs, have not evolved aggressively enough for these modern workloads. The P570 is intended to address that gap.

Fully Out-of-Order Scalar and Vector Execution

One of the most important aspects of the P570 is its execution architecture. According to SiFive, both the scalar and vector engines operate fully out-of-order.

That is unusual. Most processors execute scalar instructions out-of-order while vector operations remain in-order or only partially decoupled. Fully out-of-order vector execution is significantly more difficult to implement efficiently and is typically reserved for much larger server-class CPUs.

SiFive claims it has brought these capabilities into a smaller, more power-efficient design suitable for edge devices. The benefit is particularly important for modern heterogeneous workloads where scalar and vector operations are heavily interleaved. By allowing both execution engines to run out-of-order, the P570 can improve utilization and reduce bottlenecks in mixed AI-oriented workloads.

AI-Oriented Vector Enhancements

The P570 also introduces new vector dot-product extensions designed to accelerate AI and signal-processing workloads. Dot-product operations are fundamental to machine learning inference because neural networks rely heavily on multiply-accumulate operations.

By combining multiplication and accumulation into optimized vector instructions, the processor can improve throughput while lowering instruction overhead and power consumption. SiFive said some vectorized workloads achieved performance gains of up to 21× compared with earlier-generation designs.

The company emphasized that these improvements come from architectural efficiency rather than brute-force scaling. Just as important, these dot-product extensions reportedly add very little silicon-area overhead.

RVA23 and Software Readiness

One of the most commercially important aspects of the launch is full support for the RVA23 application profile.

Historically, software fragmentation has been one of RISC-V’s biggest challenges, with vendors implementing different combinations of ISA extensions. RVA23 aims to establish a standardized baseline for modern application processors, including support for vectors, hypervisors, security features, and modern Linux requirements.

SiFive emphasized that Linux distributions and Android ecosystem efforts are increasingly aligning around RVA23. The P570 positions itself as a software-ready platform for mainstream operating systems by fully supporting the RVA23 profile, including several optional extensions.

The company also pointed to growing ecosystem momentum. Previous SiFive-based development platforms have reportedly been used by NVIDIA for CUDA-related RISC-V work, by Red Hat for enterprise Linux development, and by Samsung for Tizen demonstrations.

Part of a Broader AI Strategy

The P570 also fits into SiFive’s broader processor portfolio, which includes AI-focused Intelligence processors, embedded cores, and automotive products.

Importantly, SiFive does not position the P570 as a replacement for dedicated NPUs or AI accelerators. Instead, it is designed to work alongside them in heterogeneous AI systems. In many deployments, the P570 would run Linux or Android while dedicated AI engines handle inference workloads.

That approach reflects a larger industry trend toward heterogeneous SoC architectures where CPUs, vector engines, and accelerators work together rather than relying on a single monolithic processor.

Summary

The P570 Gen 3 is more than an incremental CPU refresh. It reflects a broader shift in edge computing itself. Modern edge devices increasingly require a combination of scalar compute, vector acceleration, AI processing, and software flexibility within strict power and area constraints.

By combining fully out-of-order scalar and vector execution, AI-oriented vector acceleration, RVA23 software compatibility, and efficient edge-focused design, SiFive believes the P570 represents one of the most advanced balanced-performance RISC-V processors introduced so far.

Whether the market embraces that vision at scale remains to be seen. But the launch makes one thing increasingly clear: RISC-V is moving well beyond its experimental roots and becoming a serious contender for mainstream application processing.

Learn more at SiFive.com

Also Read:

Architecting Intelligence: The Rise of RISC-V CPUs in Agentic AI Infrastructure

SiFive’s AI’s Next Chapter: RISC-V and Custom Silicon

SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion

May 13, 2026May 15, 2026

Configurable xSPI memory controller IP core is FuSa-ready

Configurable xSPI memory controller IP core is FuSa-ready
by Don Dingee on 05-13-2026 at 10:00 am
Categories: CAST, IP

SPI, invented some four decades ago, is so successful as a low-pin-count interface for microcontrollers and processor cores that it spurred memory makers to incorporate both the physical signaling interface and advanced memory command protocols into serial flash and serial pseudo-SRAM (PSRAM) devices. Those protocols, however, fractured into manufacturer-specific versions. A few years ago, JEDEC expanded SPI into xSPI, aiming to gather the most popular proprietary over-SPI serial memory protocol variants into a single superset standard. Now that xSPI adoption is widespread across the industry, CAST’s xSPI-MC IP core is an attractive offering that blends a protocol engine and a serial memory controller in functional safety-ready configurations that are fully synthesizable and suitable for practically any serial flash or serial PSRAM application.

From four wires to plug & play auto-configuration

The power of SPI lies in its ability to communicate with a wide range of attached peripherals, including sensors, displays, control devices, and, of course, serial memory. A basic SPI implementation has four lines: a serial clock, a slave select, master-out-slave-in (MOSI, serial data output by a master), and master-in-slave-out (MISO, serial data output by a slave).

Early implementations simply connected the pins and relied on software to manage transfers on a per-device basis. Eventually, to speed up software development, manufacturers created over-SPI protocols with device command sets that offered some consistency as long as designers were loyal to that manufacturer.

Without firm guidelines, for instance, bit widths and clock rates (which are theoretically not limited, but in practice, signal integrity starts having an effect around 20 MHz), the over-SPI protocols diverged at the whim of manufacturers. While specifics differ, the general form of an over-SPI protocol resembles this:

One command structure is standardized: obtaining the device ID. A master sends a 9Fh to request a device ID, and a device responds with its unique JEDEC-registered ID. That implies a master can maintain a table of supported device IDs and their corresponding protocols, query the attached device, and initiate transfers using the correct commands and parameters.

xSPI defines just such an auto-configuration method for serial memory devices by tabulating support for various over-SPI protocols, selectable by device ID. The same scheme allows adding other over-SPI protocols to a controller, as long as the device IDs are unique.

A quick look at the CAST xSPI-MC IP core

It’s also possible to configure wider interfaces to speed up transfers while still keeping pin counts relatively low using the same scheme. CAST leverages this capability in the xSPI-MC IP core, supporting xSPI, HyperBus (a 12-pin interface originally designed by Cypress), and Xccela (a 12-pin interface created by Micron). Both specifications fall into the octal SPI category with eight data lines tuned for higher-frequency operation. The xSPI-MC SPI controller and PHY scale across single-, dual-, quad-, octal-, and 16x SPI buses.

Run-time configurability enables users to detect a variety of devices. The configuration can be done with zero software overhead to initialize the controller and a memory device, or it can be modified in software. The device ID table is stored off-core, for instance, in ROM or OTP memory so that it can be updated easily. This configurability can be a project-saver – it’s not uncommon to get near the end of a design and discover, for supply chain or pricing reasons, the memory device has to switch to a different part.

The PHY is of particular interest – it’s a soft PHY specifically designed for SPI, implementing only the logic required for the interface with no excess, so it takes considerably less area. Unlike hard PHYs, which typically require qualification in a specific process node, CAST implemented the xSPI-MC soft PHY in fully synthesizable RTL, ready for any foundry, process node, or standard-cell library. This soft PHY also integrates into a standard ASIC or FPGA flow with no analog bring-up procedures, and it can drop directly into FPGA-based prototyping platforms for a smooth design workflow. These soft PHY attributes open up more implementation options, eliminate foundry dependencies, and make designs highly portable, reducing schedule risk.

Use cases include firmware, data, parameter, and log storage

xSPI-MC use cases span a range of application segments for serial flash and serial PSRAM:

With automotive applications, a popular use case, the xSPI-MC supports nine ISO 26262-ready core configurations, ranging from ASIL-B to ASIL-D levels. Enhancements such as spatial redundancy and CRC protection enable swifter functional safety (FuSa) certification. Engine control units with firmware storage and XIP boot, displays that store navigation, audio, or user interface data, and EV battery management systems with calibration tables and fault log storage are a few use-case examples.
In IoT and edge devices, sensor nodes with firmware and configuration parameters are a common use case. The onset of AI also requires storage of model weights, and wireless communication nodes can store upgradable protocols.
Industrial automation controllers often have firmware storage. Robotics platforms also need real-time parameter tables and event logging, while smart meters require non-volatile event and usage logging.
Consumer electronics often feature OTA (over-the-air) firmware updating. Small displays may use serial PSRAM for framebuffers and rendering. Earbuds and hearing aids present an ultra-small form factor, and the space saved by the soft PHY can make a difference. Gaming controllers and handheld consoles also need configuration and save-state storage.

xSPI-MC IP core flexibility also includes Verilog parameters that enable feature selection, reset value definition, AHB bus configuration, and SPI controller configuration. More info on the xSPI-MC IP core and its applications is available on the CAST website:

xSPI-MC: xSPI, HyperBus™, & Xccela™ Serial Memory Controller

Also Read:

CAST’s Breakthrough in Automotive IP: The MSC-CTRL Microsecond Channel Controller

CAST Simplifies RISC-V Embedded Processor IP Adoption with New Catalyst Program

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May 13, 2026May 12, 2026

CEO Interview with Dr. Jekaterina Viktorova of Syenta

CEO Interview with Dr. Jekaterina Viktorova of Syenta
by Daniel Nenni on 05-13-2026 at 8:00 am
Categories: AI, CEO Interviews, Chiplet

Dr. Jekaterina (Jeka) Viktorova is the CEO and Co-Founder of Syenta, an Australian deep-tech company developing breakthrough additive manufacturing technology for the semiconductor industry. With a background in chemistry, electrochemistry, and advanced manufacturing, she is the inventor of the core Syenta technology and leads its mission to solve the AI era’s memory bandwidth bottleneck by enabling high-resolution copper interconnects for next-generation advanced packaging.

Tell us about your company

Syenta is a next-generation semiconductor company focused on solving one of the most pressing challenges in AI infrastructure: how chips connect and communicate at scale. As systems move toward chiplet-based architectures, performance is increasingly limited not by compute, but by interconnect density and packaging constraints.

We’ve developed a proprietary manufacturing approach, Localized Electrochemical Manufacturing (LEM), that enables finer-pitch, high-density chip-to-chip connections using existing fabrication infrastructure. Our goal is to unlock higher performance and scalability for AI and high-performance computing systems while making advanced packaging more accessible and manufacturable at scale.

What problems are you solving?

The industry is hitting a fundamental bottleneck in advanced packaging. As AI systems scale, they rely on more chips working together, but current interconnect technologies can’t keep up with the bandwidth and density requirements.

At the same time, advanced packaging capacity is constrained and concentrated in a small number of facilities, making it difficult to scale production globally.

Syenta addresses both challenges. We enable higher-density interconnects to improve system performance, while also reducing manufacturing complexity by eliminating steps and leveraging existing infrastructure. This helps customers scale faster without needing entirely new fabrication approaches.

What application areas are your strongest?

Our strongest applications are in AI and high-performance computing, where system-level performance depends heavily on how efficiently chips are connected.

This includes hyperscale data centers, AI training and inference systems, and emerging architectures built around chiplets and heterogeneous integration. These environments require extremely high bandwidth, low latency, and scalable manufacturing approaches, all of which align directly with what our technology enables.

What keeps your customers up at night?

Customers are increasingly concerned about how to scale AI systems efficiently. They’re running into limits on interconnect density, which directly impacts bandwidth, performance, and power efficiency.

There’s also growing concern around supply chain constraints in advanced packaging. With capacity concentrated in a few regions and facilities, customers face risk when trying to scale production or bring new systems to market quickly.

Ultimately, they’re looking for solutions that improve performance without adding complexity or requiring entirely new manufacturing ecosystems.

What does the competitive landscape look like and how do you differentiate?

The advanced packaging ecosystem includes large foundries, OSATs, and equipment providers, all working to push the limits of interconnect density and system integration.

Where Syenta differentiates is in our approach. Instead of requiring new infrastructure or entirely new process flows, our LEM technology integrates into existing manufacturing environments.

We’re able to achieve micron-scale interconnects with fewer process steps, improving both performance and manufacturability. This combination of higher density and lower complexity is what sets us apart and makes our approach scalable in a way that many alternatives are not.

What new features or technology are you working on?

We’re focused on advancing LEM toward high-volume manufacturing and continuing to push the limits of interconnect density and performance.

At the same time, we’re working closely with partners across the semiconductor ecosystem to ensure our technology aligns with next-generation packaging roadmaps and evolving AI system requirements.

How do customers normally engage with your company?

Customers typically engage with us through early technical collaboration. We work closely with them to understand their system requirements and evaluate how our technology can be integrated into their packaging and manufacturing flows.

As we scale commercialization, we’re building deeper relationships with customers and partners globally, including through our expansion into the U.S., where we can collaborate more closely with leading semiconductor and AI companies.

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May 13, 2026May 12, 2026

Sensing. A Quantum Tech Ready for Market?

Sensing. A Quantum Tech Ready for Market?
by Bernard Murphy on 05-13-2026 at 6:00 am
Categories: 3D IC, Quantum Computing, Semiconductor Services

While the quantum world revolves around quantum computing, (QC) there are a couple of other quantum technologies of note. I covered one of these, quantum communication, in a recent blog. Here I’ll introduce the other, quantum sensing. The goal is to use the high sensitivity of an individual quantum state to external factors such as magnetic fields, able to sense very small variations outside the range of traditional sensors. There are indications that at least some of these applications may be much closer to production-ready than QC.

Origins

Deep research methods aren’t particularly helpful here. Instead, I’ll reference the first implementation example in Building Quantum Computers, based on Nuclear Magnetic Resonance. In or around 1997 attempts were made to build QC’s using NMR to monitor precession frequencies in molecules such as chloroform in liquid suspension. These methods provided proof of concept but were completely unscalable. Nevertheless, NMR and similar techniques such as electron spin resonance are now proving effective in quantum sensing, as illustrated in this paper and this paper.

I certainly can’t claim an exhaustive review of quantum sensing techniques, however examples I have found cluster around nitrogen vacancy centers in synthetic diamond. This name confused me at first. What it means is a nitrogen atom replacing a carbon atom in the diamond lattice plus a vacancy in the lattice adjacent to the nitrogen atom. Valence electrons for a negatively charged state of this structure form a spin-triplet state in both ground and excited primary states (sorry, bit of physics) with 3 possible magnetic quantum states: 0 and ±1. The 0 state is (energetically) lower than the ±1 states and the ±1 states split further under influence of a magnetic field, the difference being proportional to the field strength.

Detecting spin states is accomplished through fluorescence from excited states. The 0 state on relaxing back to the ground state fluoresces brightly, the ±1 states fluoresce less brightly since they often relax through an intermediate state. Frequency sweeping microwave radiation pulses across the diamond changes populations between 0 and ±1, detectable as a dip in fluorescence at a frequency related to the magnetic field strength. Which proves very useful in semiconductor defect detection.

An application for failure analysis

Quantum Diamonds has just installed a production system at Eurofins EAG Labs in Sunnyvale, aimed to support failure analysis for <5nm tech and 3D packaging. This system was first unveiled at Semicon Taiwan in 2025 and is especially valuable for non-destructively testing for semiconductor shorts, leakage and opens in die and in 3DIC. The Quantum Diamonds Microscopy platform images magnetic fields generated by current flow in a chip and can achieve remarkable localization resolution: <1μm in xy and down to 1 μm in depth, with a 3mm x 3mm field of view (which can be stitched to larger areas).

There are several interesting aspects to this technology. The usual constraints on QC don’t apply here. While additional defect centers may be used to amplify light signal, there is no need for superposition or entanglement. This is a simple atomic physics application: pump electrons up to an excited state, observe fluorescence when they relax back to the ground state. Also the technology works at room temperature, no need for special cooling. Diamond is especially stiff, minimizing impact of heat noise, it has a wide bandgap minimizing electrical noise, and if diamonds are grown using isotopically pure C₁₂, there is no nuclear “noise” from C₁₃. This room-temperature capability makes quantum sensing interesting in other areas, such as a hack-proof alternative to GPS, based on detecting variations in the earth’s magnetic field.

You can read the Quantum Diamonds press release HERE and a more detailed paper for a different application HERE.

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Beyond Tool Interoperability: The Emerging Governed Convergence Problem in Semiconductor Design

Beyond Tool Interoperability: The Emerging Governed Convergence Problem in Semiconductor Design
by Moh Kolb on 05-12-2026 at 10:00 am
Categories: AI, Chiplet, EDA

The semiconductor industry has spent decades optimizing tools. Today, however, the central challenge is no longer whether individual tools are powerful enough. The real question is whether increasingly specialized tools, domains, models, and organizations can still converge coherently into a manufacturable, reliable, high-performance system.

That distinction matters.

Recent discussions around interoperability frameworks such as Siemens’ Calibre Connectivity Interface (CCI) highlight an important and necessary evolution in the industry. By transforming LVS verification output into a structured, queryable data foundation for downstream tools, the industry is moving beyond isolated verification flows toward connected engineering ecosystems. This is a major step forward. But interoperability alone does not guarantee system-level convergence. That distinction is becoming increasingly important as semiconductor systems move from tool-limited complexity to convergence-limited complexity, as illustrated in Figure 1.

Figure 1.

At advanced nodes, particularly below 5nm and within heterogeneous integration architectures, fragmentation is no longer limited to tools alone. It now spans abstraction layers, physics domains, organizations, manufacturing flows, packaging ecosystems, and even decision authority itself. Modern system realization extends across architecture, silicon, package, interposer, PCB, thermal, mechanical, SI/PI, electromagnetic behavior, reliability, validation, and manufacturing integration. Each of these domains is represented by highly specialized tools that are often locally optimized but globally disconnected.

This creates a dangerous illusion: every domain can appear “correct” while the overall system still fails to converge.

The industry is beginning to encounter what can be described as a convergence scaling crisis.

As systems become more tightly coupled, the number of interactions between engineering domains grows nonlinearly. At some point, organizations encounter an “Entropy Wall,” where the complexity of cross-domain coordination grows faster than the organization’s ability to reason about it coherently. Historically, engineering scale was constrained by transistor count, lithography, frequency, or power density. Increasingly, the limiting factor is becoming convergence capacity itself. In other words, the industry may not be running out of compute capability nearly as quickly as it is running out of governed decision-making capability.

Many organizations assume that AI will naturally resolve this fragmentation. In practice, however, uncontrolled AI risks amplifying fragmentation rather than reducing it. Most engineering environments already operate with conflicting models, inconsistent assumptions, disconnected evidence chains, isolated optimization loops, tool-specific abstractions, and incomplete causality tracking. AI systems trained across such fragmented ecosystems can accelerate local optimization while simultaneously increasing global instability.

This highlights a critical distinction: intelligence is not convergence. Prediction is not governance. Automation is not authority.

The next architectural transition therefore extends beyond interoperability toward what can be described as governed convergence. Interoperability ensures that tools can exchange information, but governed convergence ensures that fragmented engineering evidence can be normalized, causally bounded, and used to drive deterministic system-level decisions.

This distinction becomes especially important in chiplet ecosystems, advanced packaging, 2.5D and 3D integration, AI accelerator platforms, high-speed interconnect architectures, and multi-vendor manufacturing environments. In these systems, the challenge is no longer simply moving data between tools. The challenge is orchestrating convergence across the entire engineering stack.

Historically, packaging has been treated primarily as a physical integration layer. That assumption is rapidly changing. At multi-terabit bandwidths and in highly coupled heterogeneous systems, packaging increasingly functions as an active control plane through which power integrity, thermal behavior, signal integrity, manufacturability, and system stability must converge simultaneously. The package is no longer merely carrying the system; it is increasingly governing the system.

One of the least discussed realities in advanced semiconductor development is that governed convergence capacity itself is becoming scarce. The industry already possesses exceptional domain expertise, powerful simulation environments, advanced AI techniques, and enormous compute capability. What remains limited is the ability to coordinate these domains coherently, preserve authoritative evidence, bound uncertainty, and make deterministic cross-domain decisions at scale.

This is fundamentally an orchestration challenge.

Not merely a compute challenge. Not merely a tool challenge. And not merely an AI challenge.

The work being done around interoperable verification ecosystems is therefore extremely important because it establishes the foundation for this next stage. The ability to create trusted, queryable, authoritative engineering evidence layers is a prerequisite for any future convergence architecture.

However, as systems continue to scale in complexity, the industry may increasingly require governance architectures, orchestration frameworks, evidence-driven gate systems, and bounded AI-assisted convergence engines capable of operating across fragmented engineering ecosystems without losing determinism, traceability, or accountability.

The semiconductor industry has solved scaling through abstraction many times before.

The next scaling problem may be convergence itself.

By Dr. Moh Kolbehdari

Dr. Moh Kolbehdari is a Senior Lead Architect at Socionext, where he specializes in the industrialization of high-performance AI chiplets and 1.8-Tb/s interconnects. With over two decades of experience in SI/PI, electromagnetic field theory, and system-level architecture, he has been a pivotal force in bridging the gap between cutting-edge silicon design and high-volume manufacturing (HVM).

Dr. Moh is the creator of the SEGA™ (Systematic Engineering Governance Architecture) framework, a methodology designed to solve the “Crisis of Complexity” in heterogeneous integration. His work focuses on transforming the package into an Active Control Plane, utilizing field-confined EM Corridors and state-aware causality to ensure deterministic yield at 2nm and beyond. He is a frequent contributor to industry-standard committees and is recognized for his “Physics-First” approach to solving the semiconductor industry’s most challenging entropy walls.

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Thermal Reliability and Robustness of CMOS-Compatible GaN-on-Si MIS-HEMTs Under High-Temperature Stress

Thermal Reliability and Robustness of CMOS-Compatible GaN-on-Si MIS-HEMTs Under High-Temperature Stress
by Daniel Nenni on 05-12-2026 at 10:00 am
Categories: Events

The continued evolution of semiconductor technologies has created a growing demand for devices capable of operating reliably under extreme conditions, particularly high temperatures. Among the most promising candidates for such applications are gallium nitride (GaN)-based high electron mobility transistors (HEMTs). These devices offer significant advantages over traditional silicon-based technologies, including higher breakdown voltage, faster electron transport, and greater power efficiency. As a result, GaN HEMTs are increasingly being explored for use in high-frequency communication systems, power electronics, and harsh-environment applications. However, ensuring their long-term reliability under elevated temperatures remains a critical challenge.

A key area of research focuses on the thermal robustness of GaN-on-silicon (GaN-on-Si) MIS-HEMTs fabricated using CMOS-compatible processes. This approach is particularly important because it allows integration with existing silicon manufacturing infrastructure, enabling cost-effective large-scale production. The use of gold-free processes and refractory metal gate materials further enhances compatibility with standard semiconductor fabrication while also improving device stability at high temperatures. These design choices reflect a broader industry trend toward scalable, reliable, and manufacturable advanced semiconductor technologies.

To evaluate thermal reliability, devices are subjected to long-duration storage tests at temperatures as high as 375°C. These tests are conducted without electrical bias to isolate the effects of temperature alone. Over extended periods—on the order of thousands of hours—researchers monitor key electrical parameters such as threshold voltage, drain current, transconductance, and on-resistance. These measurements provide insight into how the device performance evolves under sustained thermal stress.

The results of such studies demonstrate that GaN-on-Si MIS-HEMTs exhibit strong resistance to thermal degradation. Although some changes in electrical characteristics are observed, they are relatively modest given the severity of the test conditions. One of the most noticeable effects is a slight negative shift in the threshold voltage. This shift indicates changes in the charge distribution within the device, which may be linked to variations in carrier density or subtle modifications in the material interfaces. Despite this shift, the overall device operation remains stable.

In addition to threshold voltage changes, small reductions in drain current and transconductance are observed. These variations suggest that carrier mobility within the channel may be affected by thermal stress. At the same time, an increase in contact resistance contributes to overall performance degradation. This increase can be attributed to changes at the metal-semiconductor interface, which may experience minor structural or chemical alterations under prolonged exposure to high temperatures. However, these effects remain limited in magnitude, indicating that the device retains a high level of functionality.

A deeper analysis reveals that the observed electrical degradations are likely the result of a combination of factors. Slight increases in carrier density and decreases in mobility work together to influence device behavior. These changes are consistent with the interplay between material properties and thermal effects in semiconductor systems. Importantly, the degradations tend to stabilize over time, suggesting that the devices reach a new equilibrium state rather than continuing to deteriorate indefinitely.

Reliability modeling plays a crucial role in understanding long-term performance. By analyzing degradation trends and applying statistical models, researchers can estimate the time to failure under typical operating conditions. These models often incorporate temperature-dependent acceleration factors, allowing extrapolation from high-temperature test data to more moderate real-world environments. The results indicate that GaN-on-Si MIS-HEMTs can achieve extremely long lifetimes, even when operating at elevated temperatures. This level of reliability makes them strong candidates for applications where durability and stability are essential.

Another important aspect of thermal reliability is the behavior of defects and trapping phenomena. In many semiconductor devices, high temperatures can lead to the formation of new defects or the activation of existing ones, which can degrade performance. However, studies show that trapping effects in these GaN devices remain largely unchanged after thermal stress. This suggests that the material system is inherently stable and resistant to defect generation under the tested conditions. Such stability is critical for maintaining consistent performance, especially in high-frequency applications where signal integrity is paramount.

Structural analyses further support the conclusion of strong thermal robustness. Advanced characterization techniques reveal that the internal structure of the devices remains largely intact after prolonged exposure to high temperatures. Interfaces between different layers retain their integrity, and there is no significant evidence of common failure mechanisms such as cracking or interdiffusion. This resilience is largely attributed to the use of thermally stable materials, including the InAlN/GaN heterostructure and refractory metal gate electrodes.

Despite these positive results, some aspects of degradation are not yet fully understood. The exact mechanisms responsible for threshold voltage shifts and resistance increases require further investigation. Potential contributors include changes in material properties, diffusion of light elements, or variations in mechanical strain due to differences in thermal expansion. Addressing these questions will require more detailed studies using advanced analytical techniques.

Bottom line: CMOS-compatible GaN-on-Si MIS-HEMT technology demonstrates excellent thermal stability and reliability under extreme conditions. While minor performance degradations occur, they are well within acceptable limits for most applications. The combination of robust materials, optimized device architecture, and scalable manufacturing processes positions these devices as a key enabler for future high-performance electronics. As research continues to refine our understanding of degradation mechanisms, GaN-based technologies are expected to play an increasingly important role in next-generation semiconductor systems.

11B.5 – Thermal Robustness of a CMOS-compatible GaN-on-Si MIS-HEMT Technology

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