Sensors are inherently analog in nature, and they get digitized for processing by using an Analog to Digital Converter (ADC) block. At the recent IP SoC event I had the chance to see the presentation by Ken Potts, COO of Alphacore on their semiconductor IP for ADCs. I learned that Alphacore started out in 2012, now offering both standard and custom IP for AMS, RF, imaging and radiation hardened electronics through a global organization, based in Arizona.
Data converters can be designed in any IC process node, however the FD-SOI technology provides the lowest power while being tolerant to radiation effects. A 28nm FD-SOI chip will consume 70% lower power when compared to a bulk CMOS process.
RF data converters need to have both high bandwidth and low power to fit applications like phase array architectures, direct to RF sampling, beamforming and 5G radios.
Alphacore designed a hybrid ADC named the A11B5G with a sampling rate of 5GS/s, resolution of 11 bits, with a 800mV supply, and a power of just 50mW by using a 22nm FD-SOI process from GlobalFoundries. One useful feature of this ADC is an integrated auto-calibration, as it eliminates interleaving spurs.
Another Analog to Digital Converter with even lower power is the A10B3G with a sampling rate of 3GS/s, 8.6 Effective Number Of Bits (ENOB) at 100MS/s, consuming just 13mW, fabricated on the 22nm FD-SOI process from GlobalFoundries.
The first low-power Digital to Analog Converter (DAC) that Ken showed was the D6B5G, and it consumed only 16mW, with 5.4 ENOB, 6-bit input and running at 5GS/s.
Phase Locked Loop (PLL) circuits can be used when demodulating a signal, to distribute clock signals inside an SoC, create a new clock frequency multiple, or recover a signal from a communication channel. The PLL5G is a very low jitter <150fs design, taping out in January 2023 in the 22FDx node.
For serial communications a SerDes circuit is used, and Alphacore has a 22FDx-based design taping out in January 2023, dubbed the SD16G, supporting a data rate from 1Gb/s to 16Gb/s, using either 8 or 16 bit for serialization/de-serialization width. All the popular protocols are supported: PCIe, JESD204, SATA, SRIO, SG-MII, USR/XSR.
All IP from Alphacore comes with a design kit that includes everything that you’ll need for customization:
- DRC/LVS logs
- Extracted View
- Extracted simulation model
- Verilog-AMS models
- Integration guide: DFT, I/O
Roadmaps for ADC, DAC, PLL and SerDes were shared for four foundry nodes: TSMC 28HPC+, TSMC 12FFCP, Intel16, GF 22FDx. So 2023 is a very busy year for silicon proven IP.
At Alphacore they are experts at designing radiation hardened circuits, taking special care for effects like Total Ionizing Dose (TID) and Single Event Effects (SEE). They have rad-hard ADC and DAC in GF 22FDx now, then plans for Intel16 in Q2’23, GF 22FDx in Q3’23, and SkyWater RH90 in Q4’23.
Three more rad-hard design examples were for Power Management ICs (PMIC), a 2-color in-pixel ADC, and an imager/camera with high frame rate of 120 FPS.
Low-power and radiation-hardened applications are a niche market, requiring specialized expertise. At Alphacore there’s a strong track record of delivering a growing family of ADC, DAC, PLL, SerDes, PMIC and imagers. The tapeout schedule for 2023 looks quite full, meaning that you get even more IP that is silicon proven for your designs in 5G, space communications, automotive, even in quantum computing.