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The Siemens Digital Industries Software View of AI and its Impact on System Design

The Siemens Digital Industries Software View of AI and its Impact on System Design
by Mike Gianfagna on 07-13-2023 at 6:00 am
Categories: AI, EDA, Siemens EDA

The Siemens Digital Industries Software View of AI and its Impact on System Design

The impact of AI seems to be everywhere. Products are smarter, doing more of what used to be done by the humans. Complex tasks can be completed quicker and with greater accuracy and failures can now be predicted more reliably and repaired before they even occur. The AI technologies used to make all this happen and how those technologies are applied to tasks familiar to SemiWiki readers is the subject of a new white paper from Siemens Digital Industries Software. The white paper presents a comprehensive view of our changing world; this is required reading for those doing electronic system design. A link is coming, but first let’s examine the Siemens Digital Industries view of AI and its impact on system design.

The AI Tools of the Trade

The term AI, or artificial intelligence has a very broad meaning. It represents a collection of algorithms and information processing strategies. Many of these concepts have been around for quite a while, some dating back to the 1940’s. A combination of new application strategies enabled by vast processing power has created the revolution we are witnessing now. According to the white paper:

During the last ten years, artificial intelligence (AI) has progressed from a visionary concept to a mainstream reality in many large companies.

The white paper provides a very useful overview of the technologies at play in this revolution and how they fit together to address real-world problems. I recommend you get the first-hand view of all this from the white paper. These technologies are woven together using mathematics, computer science, statistics, and psychology. They include machine learning and deep learning. The goals of AI application discussed are broad and include:

  • Make informed decisions, increasing efficiency
  • Complete routine tasks with minimal effort, improving productivity
  • Improve expertise by recommending next tasks

AI Applied to PCB Design

PCB design is used as an example in the white paper to illustrate the impact of AI. PCB design challenges engineers to generate designs that have adequate power and cooling for complex and fast ICs while maintaining signal and thermal integrity for every high-speed signal between the various ICs on a board. The complexity of the problem can explode quickly. This application provides a great backdrop to see the various ways AI can revolutionize design. 

Many aspects of AI’s impact on the design process are discussed in the white paper. Here is a brief summary to whet your appetite:

Learning curve: Experienced engineers develop an intuition about how to optimally apply tools and set options. This is the main reason the productivity of a senior engineer is so much higher than that of a junior engineer. What if AI could capture this intuition, allowing junior engineers to perform like senior engineers?

Component selection: Engineers spend a lot of time researching the selection of components to optimally address system requirements. What if a model could be developed based on historical information to cut this problem down substantially?

Component model creation: Generating models to represent the components (e.g., symbols, 2D/3D physical geometries, and simulation models) takes a lot of time and demands many different skillsets. What if natural language processing, image recognition, and ML could be applied here?

Schematic connectivity: Optimal component placement and connection requires a broad perspective of the design. Here is another opportunity for AI assistance.

Dynamic reuse: The knowledge applied to one design is often lost once the design is completed. What if institutional knowledge could be saved and curated?

Constraints: Again, prior knowledge can make this task much easier with higher quality results.

Layout: These tasks use heuristics to optimally automate the process. What if AI can target those heuristics to be more specific and more accurate?

Analysis and verification: Design sensitivity to factors such as material properties, physical layout and temperature/voltage all conspire to make this process challenging. What if AI can refine the interdependencies to a more predictable model?

Design synthesis: Pulling it all together, generative AI approaches can have a big impact.

The Big Picture

Siemens Digital Industries Software has a very broad footprint. Its customers span many markets, industries and applications. The white paper discusses some of the investments being made to deploy AI across this broad footprint.

Examples discussed include:

  • AI/ ML-based accelerators for edge applications get to market faster
  • Genetic algorithm-based optimization to build an efficient decoupling capacitor set for a power delivery network
  • An adaptive UI to improve user productivity by predicting the commands that users will most likely want to use
  • Delivery of 90 percent accuracy on next-step suggestions in microflows
Siemens Xcelerator portfolio

This is an incredibly broad set of AI applications across design, manufacturing, and production. As part of the Siemens Xcelerator portfolio, these tools help electronic systems design companies leverage AI technologies to deliver futuristic products to market today.

To Learn More

Here is a link to the new white paper, Reducing Electronic Systems Design Complexity with AI. AI will change the face of design and manufacturing. I highly recommend you download this white paper to learn more. It will help you to understand the Siemens Digital Industries view of AI and its impact on system design.

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Transforming RF design with curated EDA experiences

Transforming RF design with curated EDA experiences
by Don Dingee on 07-12-2023 at 10:00 am
Categories: EDA, Keysight EDA

How to Design an RF Power Amplifier course screenshot

Access to sophisticated RF EDA tools is one thing. Effectively harnessing their capability in real-world use is another. Digital EDA and test & measurement providers have long recognized ongoing customer education needs for their solutions. Keysight is embarking on an initiative to develop curated EDA experiences with a wide range of free learning for RF EDA solutions.

Curation brings users better information

Keysight teams already produce a massive quantity of information online, most of which lives a very long life somewhere tied to an asset. “If you go and search Keysight.com for ‘oscilloscopes’ today, you’re going to come up with thousands of documents, videos, applications, notes, and white papers,” says Linas Dauksa, Senior Digital Marketing Manager for Keysight. “Much of this material we’ve developed as vendor-neutral for learning to do something with any oscilloscope – we’re teaching users, not selling gear.”

Still, an unaided search can produce many results – some new, some old, some on target, some not maintained. Curation can pull better results to the top, but it takes skilled resources. For the last four years, Keysight has quietly assembled an experienced digital learning team to begin the process, creating a portal called Keysight University as a first step and collecting RF EDA content in pages like this one focused on RF circuit designers.

 

 

 

 

 

 

 

 

 

 

 

 

 

“We originally thought of Keysight University as a pre-sales tool,” says Julie Pildner, Digital Learning Marketing Manager. “Soon, we discovered people were using the information in many different ways at all points in their journey – and the journey didn’t necessarily take them through the portal for everything they found useful.”

Formatting for smoother consumption in short or long form

A funny thing happens when asking people to pay for anything: expectations jump. There’s always a freemium model, where introductory information is openly available, and higher-value content is behind a paid subscription wall. The hope is free material demonstrates enough value to convince a user to subscribe and get more access for a fee. That approach can leave a lot of users behind, however.

“If I’ve paid for a subscription, and I launch into a 45-minute webinar without well-designed sections, there’s a risk I lose interest before I get the information I was looking for,” says Richard Duvall, RF EDA Portfolio Marketing Manager. “To solve that, we’re converting many of our longer content hits into easier-to-find, easier-to-navigate lessons.”

Rather than locking the entire content behind a paywall, a user journey might take them directly to a lesson section and deliver the curated EDA experiences with minimal time and no fees invested. Duvall and others have been busy converting webinars on various topics into lesson modules that look more like this one on How to Design an RF Power Amplifier. Note how users can go hands-on with downloadable workspaces reinforcing lessons.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pildner quickly points out that learners sometimes look for full-length, deep-dive webinar content on a complex topic – or maybe long-form insight, like a boot camp, from a particular expert. She sees free Keysight content in both formats moving forward, saying, “We want to be the trusted source, the first place people think of for test and measurement and RF EDA ideas.”

Learning via curated EDA experiences sets a new tone

Starting in August, Keysight learning teams plan on moving away from the hierarchical portal and toward a smoother experience integrated with search, where users can guide their journey faster from more places in Keysight.com and other environments.

These curated EDA experiences with user access to Keysight experts are a big part of the digital transformation in enterprise RF EDA solutions. Users can see how Keysight approaches real-world RF design challenges with broader access to experts and their ideas.

To support your continuous learning effort, visit the extensive EDA course library covering RF Circuit Design, RF System Design, High-Speed Digital Circuit Design, and Device Modeling and Characterization on Keysight University.

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Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US

Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US
by Bernard Murphy on 07-12-2023 at 6:00 am
Categories: Aion Silicon, Automotive, Semiconductor Services

Sondrel scaling

It’s no secret that system companies are driving a lot of new silicon. Google, AWS, Tesla and others have well-established design teams delivering differentiated servers, AI engines and other technologies. I’m sure NVIDIA suspects sub rosa projects are already underway in many of these hyperscalers to design out their GPUs.

Below those dizzy heights, there is plenty of demand among midlevel system suppliers to build the essential brick-and-mortar silicon underlying modern electronic systems. Advances in edge AI, automotive networking and support for zonal architectures, and fixed wireless access devices for industrial and building automation are all very active domains. System builders here must also differentiate in their silicon platform to meet affordability and low-power objectives but span a spectrum from zero chip expertise, to logic design only, to an in-principle full design team not yet proven on a high-risk project.

Sondrel, a UK ASIC design services company, has provided an answer for many years to such clients, growing to be the biggest digital Design and Supply and ASIC design services organization in Europe.

About Sondrel

The company was established in the UK in 2002. Starting in back-end design services where demand is commonly highest, they have grown steadily, acquiring the ST Morocco design center and the Imagination Technologies IMG Works team, the latter adding architectural and front-end design expertise. Sondrel now has design centers in the UK, India and Morocco, with sales offices in Europe, the US and Israel (Redtree Solutions).

These are not simple designs. Even in the midrange, systems builders want video interfaces, machine learning, automotive compliance, networking, AR/VR, low-power IoT and even blockchain expertise. Design sizes are significant, one recently reported at 500 sq mils with over 30 billion transistors. They are also regularly pushing leading-edge technologies with large chip designs on 7nm and 5nm. Markets served include AI at the edge, automotive, 8K video, smart homes and cities, wearables and consumer devices.

Even more interesting, Sondrel offers a full turnkey service, from concept to delivered packaged and tested parts. They have established relationships with the principal EDA and IP suppliers, foundry relationships with TSMC, Samsung and GlobalFoundries and with leading Test and OSAT companies. Naturally, they provide supply chain management throughout this cycle. Ian Walsh (VP of Biz Dev and VP of North America Operations) makes the point that TSMC and others will only work directly with extremely high-volume customers. The only way anyone but the giants can get access to their technologies is through accredited ASIC services like Sondrel. Sondrel calls their full-service solution Design and Supply, which starts at the design concept and extends to supply chain management and delivery, distinguishing them from other lesser ASIC offerings.

Ian also adds that another key strength is their design team which has worked on over 100 designs over the last 20 years and is tightly integrated. They operate not so differently from established teams in a big semiconductor house, working on platforms they already understand (more on that next). There is plenty of opportunity to keep pushing frontiers, yet with lots of accumulated experience in managing risk. An intriguing option for a wide range of design and supply needs.

The Sondrel SFA platform

Sondrel starts with well-proven reference designs. The SFA 200 reference is architected for single-channel video and data processing, targeted at fixed and mobile (battery-powered) applications, such as Smart Home, Smart Metering, Sensor Fusion and other applications where a compact chip can provide local intelligence for end-point data processing. The SFA 250A variant adds ISO 26262 compliance, including an independent functional safety island as a basis for ASIL D compliance if requested.

The SFA 300 reference has four CPU clusters enabling powerful, scalable signal and data processing SoCs to be created faster at lower costs. This is targeted at signal and data processing applications such as 8K video, facial recognition for surveillance, smart factories, blockchain servers and medical data analysis. In a similar way, the SFA 350A reference is extended to support automotive applications.

The SFA 100 platform is designed for small-footprint IoT applications supporting features such as voice activation, image classification, gesture recognition, filtering, inference and tracking.

I think this is interesting. Turnkey ASIC Design and Supply service, load-balancing the business across the mid-tier of system companies with options to serve monster projects without overbalancing the revenue mix. You can learn more HERE.

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WEBINAR: Leap Ahead of the Competition with AI-Driven EDA Technology

WEBINAR: Leap Ahead of the Competition with AI-Driven EDA Technology
by Rob vanBlommestein on 07-11-2023 at 10:00 am
Categories: AI, EDA, Events, Synopsys

Synopsys.ai

The demands on today’s designs are relentless. Each generation of devices needs to be faster, smaller, more functional, more connected and more secure than the previous generation. In the face of all this, the time required for next-generation devices to hit the market is dramatically shrinking. That means the competitive landscape is fierce.

Complexities are making it impossible for companies and engineers to keep pace and deliver high-quality results. Too much time is spent optimizing, verifying, and testing the design without any guarantee that desired targets are being met. In the wake of all this increased complexity, the semiconductor industry is encountering a shortage of talent making it difficult to innovate.

The picture being painted seems very bleak, but we are at an inflection point. The demands are outpacing the resources to deliver, and that means the technology and tools to help must change. This is where artificial intelligence plays a critical role. AI is like the industrial revolution of our generation. It is essential to make what is imagined possible.

For the semiconductor industry, AI-driven electronic design automation solutions will not only help in this highly competitive market but also will allow companies to spend time innovating.

Synopsys is hosting a seminar series that explores how companies can leverage AI-driven EDA technology to deliver significant quality of results and productivity improvements across the development flow. The series will discuss how Synopsys.ai™, the industry’s first full-stack, AI-driven EDA suite, can help tackle the PPA (power, performance, and area), verification, and test challenges associated with today’s complex designs.

The first presentation of this three-part series targets design engineers looking to optimize PPA targets using Synopsys Design Space Optimization solution, DSO.ai™. The second webcast focuses on the verification engineer and how to achieve higher quality verification coverage faster with Synopsys Verification Space Optimization solution, VSO.ai™. The third webcast addresses the challenges faced by test engineers to reduce the number of test patterns while optimizing defect coverage with Synopsys Test Space Optimization solution, TSO.ai™. All three presentations will illustrate how to eliminate redundant and repetitive tasks using the respective sophisticated Synopsys.ai technology.

The future of innovation rests on the adoption of critical AI technologies. We can no longer burden ourselves with traditional manual tasks if we are to beat the competition. AI-driven EDA technology will allow companies to focus on chip quality and differentiation and empowers engineers to get the right chip with the right specs to market faster.

Register for the Synopsys.ai webinar series today!

Also Read:

Computational Imaging Craves System-Level Design and Simulation Tools to Leverage AI in Embedded Vision

Is Your RTL and Netlist Ready for DFT?

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Requirements for Multi-Die System Success

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Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform

Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform
by Kalar Rajendiran on 07-11-2023 at 6:00 am
Categories: EDA, Siemens EDA

siemens xpedition supplyframe opengraph 1200x630

 

Next generation electronic systems require an engineering approach incorporating a digital twin methodology for early verification with digital prototypes. Over the course of a design project, the digital twin model evolves to allow more complex interactions including analysis, simulations and validations earlier in the design cycle. This enables teams to detect problems much earlier when they are easier and cheaper to fix with very little product launch schedule impact.

Siemens Xcelerator is a powerful digital platform that offers a comprehensive suite of software and services built for the digital twin methodology. The platform encompasses various domains, including product lifecycle management, computer-aided design, simulation, and manufacturing operations management. It enables organizations to optimize their entire product development process, from ideation to production, by providing a unified environment for collaboration, data management, and analysis. With its advanced capabilities, Siemens Xcelerator empowers businesses to accelerate time-to-market, enhance product quality, and drive digital transformation.

Xpedition software is a specific component of the Siemens Xcelerator platform and focuses on PCB (printed circuit board) and electronic systems design. It offers a range of advanced tools and features for system design definition, electronics design, electro-mechanical co-design, analysis, verification, and PCB manufacturing. This software provides engineers with the capabilities to create complex, high-performance PCB designs and streamline the design process. The software is widely recognized in the industry as one of the most innovative and comprehensive solutions for electronic systems design.

Recently, Siemens announced a significant enhancement to its Xcelerator platform with the integration of the Supplyframe™ Design-to-Source Intelligence (DSI) capability. By incorporating this capability into Siemens Xcelerator, the company aims to offer comprehensive component technical data and real-time supply chain intelligence to its customers. This integration is a significant addition and brings high-value to Siemens EDA’s customer base.

What is Supplyframe DSI?

Siemens Supplyframe DSI platform is an advanced solution that provides comprehensive intelligence and insights throughout the design and sourcing stages of product development. It offers real-time data and analytics related to global component availability, demand, cost, compliance, and parametric information. The solution aggregates and analyzes vast amounts of data signals from the global electronics value chain, capturing information on part supply, demand, risk, and commercial intent.

Benefits of Supplyframe DSI Integration

With the Supplyframe DSI capability integrated into Siemens’ Xcelerator, the platform empowers businesses to make informed decisions during the design phase. The solution enables seamless collaboration and data sharing, leading to better coordination, improved resource management, and increased efficiency in the digital enterprise.

Cost Reduction

The real-time supply chain intelligence provided by the integrated solution enables engineers to make better component decisions during the design phase, resulting in cost savings and improved agility. With access to detailed component intelligence on over 600 million manufacturer part numbers, engineers can make informed tradeoffs when the cost of change is lowest, optimizing the design and sourcing strategies.

Streamlined Workflows and Risk Assessments

The integration eliminates manual data entry and library maintenance tasks, streamlining the design process. Engineers can benefit from detailed part comparison views, “what-if” part selection analysis, and digitally managed workflows. Real-time part-level audits facilitate streamlined risk assessments during design capture, enabling businesses to mitigate potential supply chain risks early in the process.

Supply Chain Resilience

In today’s dynamic business landscape, supply chain resilience is crucial for organizations. The integrated solution extends Siemens’ supply chain resilience leadership by providing comprehensive real-time data and decision support to engineering, new production introduction (NPI) management, and sourcing teams. It empowers businesses to adapt their design and sourcing strategies quickly, keeping pace with industry evolution.

Summary

Siemens’ integration of the Supplyframe DSI platform with Siemens Xcelerator represents a significant advancement in real-time supply chain intelligence. By providing access to global component availability, demand, cost, and compliance data during the design phase, Siemens empowers businesses to optimize their supply chain management, reduce costs, and improve agility. The integrated solution streamlines workflows, facilitates risk assessments, and enhances collaboration among teams, enabling organizations to thrive in the face of dynamic supply chain changes.

Also Read:

Transforming the electronics ecosystem with the component digital thread

DDR5 Design Approach with Clocked Receivers

Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform

Podcast EP170: An Overview of the New Calibre Shift-Left Methodology with Jeff Wilson

Podcast EP170: An Overview of the New Calibre Shift-Left Methodology with Jeff Wilson
by Daniel Nenni on 07-10-2023 at 10:00 am

Dan is joined by Jeff Wilson, the DFM director of product management for Calibre Design Solutions at Siemens EDA. Jeff is responsible for the development of products and design flows that address the challenges of DFM and increasing the robustness of designs.

Dan explores the capabilities of the new Calibre Design Enhancer product from Siemens EDA with Jeff. This product delivers a shift-left methodology for design implementation using proven Calibre layout modification technology. Jeff explains the use model and impact of Design Enhancer VIA, PGE and PVR.

Jeff discusses in detail how these three capabilities are deployed during design to enhance the resulting layout and reduce design time. The broad foundry and technology support of Calibre are also discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Podcast EP171: A Discussion of an EDA Revenue Milestone and the Upcoming DAC with Wally Rhines

Podcast EP171: A Discussion of an EDA Revenue Milestone and the Upcoming DAC with Wally Rhines
by Daniel Nenni on 07-10-2023 at 8:00 am

Dan is joined by Dr. Walden Rhines to discuss the Q1 2023 Electronic Design Market Data report that was just released. SEMI and the Electronic System Design Alliance collect data from almost all of the electronic design automation companies in the world and compile it by product category and region of the world where the sales occurred. It’s the most reliable data for the EDA industry and provides insight into what design tools and IP are in highest demand around the world.

In this spirited and far-reaching discussion, Dan explores the anatomy of the Electronic Design Market Data report with Wally. An all-time quarterly revenue record of $4B was posted for Q1 2023. Almost all product categories saw a healthy 15 – 25 percent increase, with PCB leading the pack. Oddly, there is one category that posted flat revenue for the quarter. In terms of regional performance, Europe led the way. Asia Pac showed very mixed results. All these points are discussed by Wally.

The upcoming DAC was also touched on. Wally will be on a panel with Joe Costello – all questions fair game. Wally will also deliver the main keynote on Wednesday to discuss taking AI to the next level. These are must-see events.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Are you Aware about Risks Related to Soft Errors?

Are you Aware about Risks Related to Soft Errors?
by Admin on 07-10-2023 at 6:00 am
Categories: EDA, IROC Technologies

Image1

Soft errors change stored data and cause temporal malfunctions in electronic systems. This mainly occurs when radiation particles collide with semiconductor devices. Soft errors are a concern in all environments, whether in the atmosphere, in space, or on the ground.

Soft errors are critical in high-reliability applications such as automotive, aerospace, medical, and high-performance computing. A Single-Event Upset (SEU) or Multi Bit Upset (MBU) can cause data corruption or software crashes that can have severe consequences for these applications.

For example, in 2003, soft errors in voting machines used in Belgium’s elections counted 4,096 more votes than voters (Ref1). Soft Error problems have been manifesting themselves for decades (Ref2) and the problems will continue to increase as chips become larger, increasing in density and functionality.

IROC solutions for Soft Error assessment in your design:

IROC Technologies is specialized in providing best-in-class EDA solutions and test/consulting services for soft error analysis and mitigation. With our expertise and know-how, we help our customer to get more confidence in their chips against radiation effects.

  • TFIT®: predicts FIT rate at the cell level and provides help for optimal hardening solutions
  • SoCFIT®: analyzes propagation of the soft errors at SoC level and provides mitigation strategies
  • SERTEST: provides radiation particle test in international world-class laboratories
  • SERPRO: provides consulting for SER management and mitigation for complex systems

IROC helps customers throughout all phases of chip design and development. Using IROC EDA solutions in a standard EDA flow early in the design cycle reduces costs and saves time while enhancing the reliability of your chip. IROC design consulting and radiation testing can help to optimize and verify your designs for optimal SER.

Customers & Partners:

More than 130 companies, including over 50% of the top semiconductor companies have benefited from IROC’s deep experience in radiation effects. Over a 23 year history, IROC has nurtured partnerships and long-term relationships with major foundries such as TSMC, Samsung, Global Foundries, the European Union, and CEA. Foundries, in particular, have used IROC EDA products to enhance PDKs to help reduce soft error problems in their customers’ designs.

Who benefits from IROC solutions?
  • TFIT®
    • cell developers such as foundries, IP vendors, and custom cell designers
    • reliability engineers looking for raw soft error rates of basic cells in their chip design
  • SoCFIT®
    • reliability engineers targeting chip reliability problems caused by radiation
    • designers who wish to analyze and mitigate propagation of soft errors and reduce the Soft Error Rate (SER) at SoC-level
  • SERTEST/SERPRO:
    • chip and system providers who want to verify the reliability of their chip
    • chip and system providers who seek expert advice to optimize the radiation related reliability of their designs

Example of IROC customers’ use cases:

Automotive: TFIT was used to harden Flip-Flops. TFIT provided analysis and suggestions for schematic and layout changes. The customer was able to achieve clean triple modular redundancy implementation and discovered a potential weakness related to angular impacts.

Aerospace: SERPRO team is working actively with the European Space Agency (ESA), recently completing a project in 16nm FinFET. Additional projects with even more advanced nodes are in the pipeline.

Medical: SERTEST team successfully analyzed and identified the root cause of a critical issue in a pacemaker application, resulting in the implementation of improved qualification and testing procedures for the customer.

HPC: Customer was able to lower their Failure in Time (FIT) Rate 7X by using SoCFIT on several, complex digital circuits including 40Mbit SRAM, 1.7M FF, 13M-Combo Gates.

Shi-Jie WEN, Distinguished Engineer, Advanced Silicon Technologist at CISCO Systems said: “Cisco benchmarked TFIT with results of tests on silicon for several designs and other tools. The correlation between the simulation results and test is impressive for this particular process node – TSMC 40nm. Cisco is committed to continue our correlation work with TFIT on the other Si technology nodes. TFIT stands as one of the best commercially available simulation tool offered to the industry for soft error simulation.”

If you would like to know more about IROC Technologies and our offerings, please do not hesitate to contact info@iroctech.com or visit www.iroctech.com.

Ref 1: https://en.wikipedia.org/wiki/Electronic_voting_in_Belgium

Ref 2: https://www.computerworld.com/article/2584471/q-a–mcnealy-defends-sun-reliability–personal-privacy-views.html

Also Read:

CEO Interview: Issam Nofal of IROC Technologies

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Mirabilis Invites System Architects at DAC 2023 in San Francisco

Mirabilis Invites System Architects at DAC 2023 in San Francisco
by Daniel Payne on 07-07-2023 at 10:00 am
Categories: IP, Mirabilis Design

visualsim architect min

System architects have a difficult task of choosing the most efficient architecture by exploring alternative approaches, while tracking and testing requirements. Using a Model-Based Systems Engineering (MBSE) approach is recommended to achieve these goals,  before getting mired in low-level implementation details like RTL code. Mirabilis is an EDA vendor at DAC this year that aims at using an MBSE methodology through their VisualSim tool. I spoke with Deepak Shankar, founder of Mirabilis Design by phone this week to get a preview of what they’re doing at DAC.

The three big messages from Mirabilis this year for DAC that will interest system architects are:

1. Integration with Model Based Systems Engineering

Architects can import their existing SysML models into the VisualSim tool. The adoption of SysML started out in the Defense community and now even system-level semiconductor companies are using it. SysML can manage your code, but it cannot predict what the performance and power will be when mapping to HW like an SoC. SysML cannot tell cache contention, because there is no latency understanding. Using VisualSim with MBSE supplies the requirements data, allowing you to measure latency, see the buffer occupancy, and even track radiation requirements.

VisualSim Architect

2. Addition of RISC-V modeling environment

RISC-V is a very popular Instruction Set Architecture (ISA) that can be extended for specific domains, but how would you do power and performance comparisons between using SiFive or an ARM architecture? How about system-level benchmarks?

With Mirabilis there are pre-built models of RISC-V IP, plus you can even create your own special RISC-V architecture. For Network On Chip (NoC) you can choose from models for Arteris NoC or ARM NoC. In VisualSim Architect you can run benchmarks for RISC-V, and see what would happen if your data is stored in cache or you have to use external RAM. You can also see the performance and identify your architectural bottlenecks. This analysis allows you to evaluate RISC-V cores for use inside an SoC, or model an SoC to give to customers so they can start planning the architecture of their end products. VisualSim allows an engineer to understand pipelines and the entire system all in one platform.

3. Created a new packaging mechanism

A RISC-V core vendor could package their high-level model before product development even starts, to use it inside an SoC, then hand it off to their end customer to see how the full system works. A semiconductor vendor, tier 1 supplier and customer can all be sharing the same executable models. Denso is an example customer sharing models of their auto ECUs as a tier 1 supplier for automotive companies, and they saved 40% of development time by using VisualSim.

DAC Paper

Mirabilis has a DAC paper on system modeling and failure analysis in avionics, in conjunction with a US Defense application.

Attend this presentation on Tuesday, July 11th, from 2:24pm – 2:42pm PDT, room 2008 on Level 2, as part of the Embedded Systems and Software track.

DAC Booth

You will find Mirabilis in booth #2217, that’s on the 2nd floor at Moscone West, and in their booth will be three technical people to speak with. While other vendors tend to only show PowerPoint slides, you will instead see a live demo of the VisualSim Architect tool in action, now that’s confidence.

You may also sign up for a private discussion in their suites by requesting online here.

Summary

System design and system modeling has become much easier, is accurate, and by using system-level IP your system architects will analyze quickly and explore more thoroughly than with other methods. At this level of abstraction your team can analyze and uncover architectural bottlenecks before detailed RTL implementation starts.

Enjoy some chocolate at the booth, I’ve heard that it’s quite tasty.

Related Blogs

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CEO Interview: Ashraf Takla of Mixel

CEO Interview: Ashraf Takla of Mixel
by Daniel Nenni on 07-07-2023 at 6:00 am
Categories: CEO Interviews, IP, Mixel

Ashraf Takla Mixel

Ashraf Takla is Founder and CEO of Mixel Inc., which he founded in 1998 and is headquartered in San Jose, CA. Mixel is a leading provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHY, MIPI M-PHY, MIPI C-PHY, LVDS, and many dual mode PHY supporting multiple standards. Before founding Mixel, Mr. Takla was Director of Mixed-Signal Design at Hitachi Micro Systems. He has over 40 years of experience in analog and mixed signal design, and holds 8 patents.

Tell us a bit about Mixel history and what lies ahead?

Mixel was founded in 1998, with one focus, to develop best of class Mixed-Signal IP. That is where our name comes from: Mixel; Mixed-Signal Excellence, so this year, we are celebrating our 25th Anniversary. Originally, we created a very wide portfolio of mixed-signal IP; PLL, SerDes, PHY’s, ADC, DAC, and Transceivers. As we grew, we focused more and more on PHYs and SerDes. In 2000, we had one of the first multi-standard SerDes in the industry, running at 4.25Gbps. When MIPI came along, we were ready to jump in since we already had an IP that supported a MDDI a standard, a predecessor to MIPI. Since then, we have had great success with our MIPI portfolio and plan to duplicate that success in adjacent segments.

There are a lot of competitors in the IP space. How is Mixel different?

We have a 25-year track record of delivering differentiated IP while consistently achieving first-time silicon success. We have a saying in Mixel; first-time success is the rule, no exceptions. For every generation and port of our IP, this has been the case.

We work closely with our customers, listen to their challenges, and address them by coming up with unique and differentiated solutions that set their products and our IPs above our competition.

Based on that, we develop proprietary implementations to address unique challenges for certain market segments. As an example, when we started addressing automotive applications over 10 years ago it became clear that testability is a key challenge. We developed and patented an implementation that uniquely addresses this challenge, which is now very widely adopted by our customers. This is a differentiated solution that only Mixel provides.

Over the last 25 years, we have developed robust design methodology that encompasses all our engineering activities. This approach enables us to create different configurations of our IP’s quickly with a high level of success. We call that methodology LegorithmicTM

Constant improvement in all we do. This is not only limited to our products, but also our engineering methodology and business practices. Our methodology and quality standards are always evolving and improving. What we consider excellent today might not be good enough tomorrow.

We have an outstanding culture that we call Mixel PRIDE: Partnership, Responsibility Integrity, Diversity and Excellence. This culture is one of the cornerstones of Mixel success.

Most importantly we treat our customers as partners, because at the end of the day it’s all about our customers’ and their customers’ success.

Who are your customers? How are your customers using your IP, what applications?

We are in the wired communication space. Most of our customers use our PHY IPs to transport data at high data rates at the lowest possible power.

We have a very wide loyal customer base, many of them are repeat customers, and have become true partners. They are all over the globe and span the whole spectrum from the largest tier-one semiconductor giants to the small innovative startups, and a whole lot between. Our IPs are widely deployed wherever the system incorporates sensors/cameras or displays, such as mobile, automotive, VR, MR, XR headsets, IoT, industrial and medical devices and platforms. You can see some of our customers on our website as well as several customer demos on Mixel’s YouTube page.

What is next for Mixel?

While we have been developing IP for automotive for 10 years, we continue to see increasing adoption in automotive. We were ISO 9001 certified in 2019 and in 2021, we achieved ISO 26262 certification with our process certified up to ASIL-D and multiple configurations of our IP certified up to ASIL-B. Automotive is a focus area for us.

While we continue to grow our MIPI portfolio, our market share, and expand our customer base, we are looking to replicate our success with MIPI in complementary standards. Many of our loyal customers are encouraging us to address more of their other PHY/SerDes requirements.

We have been selling our test chips at low volume for a while now and looking into growing that business and leveraging it as an entry to the chiplet business.

We are continually expanding the team and our global presence to address the ever-growing opportunities available to us.

What are you excited about?

Despite the recent high-tech industry challenges, the future of the semiconductor industry and the IP business is bright, particularly in the segments that Mixel is focused on.

I’m very excited about our plans to expand beyond our MIPI focus, and about growing our engineering team globally beyond our current footprint.

In 2021, we announced Mixel’s commitment to our environment, community, and employees as a part of our CSR initiatives. We want to do our part to give back. We are offsetting 100% of the carbon footprint of our global operations and have partnered with several organizations to give back to the local community. It will be exciting to build on those first steps and see that effort come to fruition.

Our customers continue to amaze us with their creativity and innovation. There are many examples. Just this year, we announced that our D-PHY IP is in Teledyne e2v’s award-winning Topaz CMOS image sensors. Our MIPI IP is in Hercules Microelectronics HME-H3 FPGA, the industry’s first FPGA to support MIPI C-PHY v2.0.

So, I’m excited about future collaboration with our customers and partners and that together, as part of the ecosystem, we are changing the world in positive ways.

Mixel will be exhibiting their latest customer demos at Design Automation Conference (booth #1414) on July 10-12, 2023, in San Francisco. Learn more here.

 Also Read:

MIPI D-PHY IP brings images on-chip for AI inference

MIPI bridging DSI-2 and CSI-2 Interfaces with an FPGA

MIPI in the Car – Transport From Sensors to Compute