SILVACO 073125 Webinar 800x100
Semiconductor Expert Forum

Posted on

TSMC Clarified CAPEX and Revenue for 2023!

TSMC Clarified CAPEX and Revenue for 2023!
by Daniel Nenni on 06-06-2023 at 2:00 pm
Categories: Events, Foundries, TSMC
4 Comments

TSMC HQ Taiwan

TSMC clarified CAPEX and revenue for 2023 last night at the Annual Shareholders Meeting. Last year TSMC guided up during this meeting but this year they guided down. CAPEX was guided down to the lower end of $36B-$32B.  Revenue was guided down from low-single to mid-single digit so maybe down another percent or two. The TSMC Jan – May 2023 revenue report indicates a decrease of 1.9 percent compared to the same period in 2022 so I think TSMC is being very conservative here.

Other foundries may not be as fortunate. Globalfoundries is already -5% in Q1 and UMC is -17% Jan-May 2023. In contrast TSMC started the year strong with +16% in January and +11% in February. Things turned bad in March with -15% and April -14%. At the TSMC Symposium CC Wei joked about his horrible forecasting but coming off the strongest year in the history of TSMC it was not a surprise.

“The year 2022 was a landmark year for TSMC. Supported by our strong technology leadership and differentiation, we delivered a thirteenth-consecutive year of record revenue, with strong profitable growth. Our 2022 annual revenue increased 33.5% year-over-year in U.S. dollar terms, while our EPS rose to NT$39.20, nearly tripling over the past three years.”

A landmark year indeed. TSMC manufactured 12,698 products for 532 customers in 2022. Hopefully we can all recognize this incredible achievement. Unfortunately, 2023 will also be a landmark year for a YoY decline and the pandemic is still to blame.

TSMC predicts that the second half of 2023 will improve so we may be at the bottom. 2024 also looks very promising but of course it is too soon to tell. According to the  World Semiconductor Trade Statistics, the global semiconductor industry is forecasted to grow 11.8% to $576B in 2024 with a major rebound expected in the memory segment, a surge of about 40% from last year.

The other news from the meeting echoed the Symposium which is good news:

 “In Taiwan, our N3 has just entered volume production in Tainan Science Park. We are also preparing for N2 volume production starting in 2025, which will be located in Hsinchu and Taichung Science Parks. In the U.S., we are in the process of building two advanced semiconductor fabs in Arizona, with N4 and N3 process technology, respectively. We are also building a 12-inch specialty technology fab in Kumamoto, Japan.”

TSMC was crystal clear in the reasoning for building fabs around the world. TSMC’s business model has always been customer centric and customers want fabs near their customers. This customer demand is not just for semiconductor manufacturing, other manufacturing is localizing as well, and again it is a direct result of the pandemic which broke supply chains around the world.

“N2 technology development is on track, with risk production scheduled in 2024 and volume production in 2025. Our 2-nanometer technology will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced.”

Interesting wording here and I do agree N2 will be denser and more power efficient than Intel 20A or Samsung 3nm. I would also add more cost effective as no one in the foundry business has the economies of scale to match TSMC.

One thing you have to remember is that when TSMC says volume N2 production in 2025 that means Apple which is a multi-billion transistor SoC shipped by the millions. TSMC is not talking about internal product, engineering samples or chiplets. The mainstream media misses this point every time. Either they are ignorant or they are intentionally besmirching TSMC to get clicks. Either way it is unethical, my opinion.

“To help customers unleash their product innovations with fast time-to-market, TSMC provides customers with comprehensive infrastructure needed to optimize design productivity and cycle times. TSMC continues to expand our Open Innovation Platform® (OIP), providing over 55,000 items of libraries and silicon IP portfolio, more than 43,000 technology files, and over 2,900 process design kits, from 0.5-micron to 3-nanometer in 2022.”

As most people know I have been part of this ecosystem since it started so I know it better than most. The one thing that I would add here is that with the overwhelming success of TSMC N3, the ecosystem has never been stronger for TSMC so there is significant momentum for the N2 transition, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

Posted on

Arm 2023 Mobile Solutions Continue Gaming Focus

Arm 2023 Mobile Solutions Continue Gaming Focus
by Bernard Murphy on 06-06-2023 at 6:00 am
Categories: Arm, IP, Security

TCS23

Arm recently announced an update for mobile under the Arm Total Compute Solutions (TCS) label, led by Chris Bergey (Sr. VP/GM for the Client line of business). You’ll remember that Chris headed the infrastructure line of business impressively through the Neoverse brand, as demonstrated by Arm-based servers appearing in multiple hyperscalars and penetration in multiple wireless infrastructure platforms. Now we get to see what he can do with mobile.

How do you grow in a saturated market?

That’s the challenge for Arm. The engine that boosted them to fame and fortune, the smartphone business, now sees declining unit shipments and projections for revenue growth anywhere between 2.5% and 7% CAGR depending on who you believe. The spread reflecting, I’m sure, uncertainty in what might stick among future product features.

Arm sees mobile gaming as an important TAM growth driver, consistent with their view last year. They commissioned a report a couple of years ago showing that mobile gaming is by far the most popular platform for gaming worldwide. Given that gaming is even now a significant contributor to NVIDIA revenue, I can believe mobile gaming presents an opportunity for Arm.

Arguably today the mobile gaming trend is strongest in China where consumers are very active in online multi-player games. Chris sees folding phones accelerating the trend as these offer a larger screen size. I also remember that at least last year the majority of phones in China were still on 3G. I expect need to upgrade to 4G/5G would also push growth, especially for Chinese phone suppliers (Xioami, Oppo, Vivo, etc). RISC-V could in theory compete for CPU slots, but without a top-of-the-line GPU offering and NVIDIA blocking RISC-V support for their GPUs that threat seems limited for now.

Gaming is also popular outside China mostly in puzzle-oriented games rather than hard-core player-competition titles. Arm sees this changing already in Korea and expects growth in the West as content adapts and as larger screen options (especially foldables) become more popular. Seems reasonable – we’re already starting to see Galaxy-S23 commercials in the US for competitive gaming; the seed is being planted 😊. Arm’s point here is that mobile competitive gaming demands a high level of performance in a smartphone, in CPUs and GPUs, features that will only be possible in premium models.

What’s new in TCS23?

There are 4 new cores covered under the announcement. Given the gaming focus of this release, Chris led with the new Immortalis G720 GPU, developed in partnership with MediaTek. Arm have upgraded the graphics pipeline to support the more complex real-time 3D imaging already standard on console and PC applications. This comes with a 15% uplift in performance and efficiency and a boost in system-level efficiency. They also introduced Mali-G720 and Mali-G620, presumably targeted to entry-level gaming handsets.

Next up is the Armv9 Cortex CPU compute cluster, starting with the Cortex-X4, delivering 15% more performance than Cortex-X3 at 40% less power and expected to serve AI/ML applications. There are new big and LITTLE cores – Cortex-A720 for “big” and Cortex-A520 for “LITTLE”, both delivering 20% power efficiency improvements over earlier generations. There is also a DSU update. Chris notes that there is now a tighter coupling between process nodes and these performance metrics, enabled by close collaboration with TSMC. That may account for these cores being 20% more area efficient than the nearest competitor, per Chris.

All of these cores are now 64-bit and complemented by Arm Memory Tagging Extension (MTE) to eliminate memory safety bugs. 70% of security issues detected in Microsoft products and 75% of vulnerabilities detected by Google in Android have been attributed to memory safety problems, leading Google to adopt MTE for Android. Nice – I’m impressed by the work Arm is putting into security, here and in the Cheri collaboration.

Deployment

The platform is built into the MediaTek Dimensity 9200, which in turn is inside top of the line phones from Oppo and Vivo and is already delivering results in games from Genshin Impact to Fortnite. Chris didn’t want to share more details but seems optimistic that more deployments will be announced.

In summary, growing in a saturated market will be an uphill climb, but Arm seems to know how it wants to get there and continues to work on ensuring it will stay on top of the game through continued technology advances. You can read the press release HERE.

Posted on

Automotive IP Certification

Automotive IP Certification
by Daniel Payne on 06-05-2023 at 10:00 am
Categories: Automotive, EDA, IP, Synopsys

SLM min

The electrification of cars and the growth of EVs means that more semiconductor content is being added with every new vehicle model from suppliers around the globe. There are unique concerns for automotive IP in terms of reliability, security and safety over the lifetime of the vehicle. I had the pleasure to speak with Pawini Mahajan, Head of Product for Silicon Automotive Solutions at Synopsys over a Zoom call this month to hear what they see happening in the industry.

Automotive OEM Challenges

I was surprised to learn that it can take 8 years to go from concept to showroom floor for a new model of car, while remodels are completed in a much shorter time span. New entrants like Tesla are certainly challenging the status quo for the speed of development and adding features. Chip shortages have plagued new car delivers over the past 2 years, as supply chains became disrupted. Zonal architectures are being used to place electronics in clusters, and ADAS features automate more of the driving for us as Level 3+ emerges. Our phones have frequent Over The Air (OTA) updates, and that trend continues in automotive as the idea of a Software Defined Vehicle (SDV) grows more popular. Hackers are active in efforts to break into auto systems, making security a new burden.

With added automotive IP there are concerns about the lifespan of semiconductor components as issues like electromigration can cause early failures. Increased temperatures actual speed up the aging process in chips. Even the constant vibration present in automotive vehicles adds to mechanically induced failures in wire bonding or even die fracturing. The current flow across transistor channels degrades the Vt and mobility values over time, another aging effect.

Larger chips fabricated at smaller nodes used in automotive IP are prone to analog circuit failures, per the bi-annual Wilson Research Group survey. It’s projected that by 2030 the percentage of total car cost will be 50% attributed to electronics, while in 2010 it was 33%.

Silicon Health Monitoring

The idea to meet these challenges of safety, security and reliability is to have monitoring inside of each chip to measure what’s going on and be able to predict a failure before it occurs. At Synopsys they use the phrase Silicon Lifecycle Management (SLM) to encompass the sequence of monitoring, gathering data, analyzing then acting on the analysis.

Silicon Lifecycle Management

The functional safety for hardware is defined in ISO 26262-5, and there’s a classic “Bathtub Curve” showing the failure rate of electronics as a function of time.

Bathtub Curve

Automotive grade requirements to reduce risks and quicken qualification for automotive SoCs are to follow the ISO 26262 functional safety assessments, meet the reliability standards of AEC-Q100, and pass the quality checks from ISO9001 and ITAF 16949.

PVT IP

Synopsys acquired Moortec back in 2020, adding on-chip IP for Process, Voltage and Temperature (PVT) monitoring. The processor detector measures speed of the silicon, the voltage monitor detects IR drop, and the thermal sensors reveal the precise temperature across multiple locations on the die. Synopsys has included these PVT IP blocks on several popular process nodes, including the N7A node from TSMC for silicon validation, and they are qualified to AECQ-100 Grade 2.

Automotive-specific documents are delivered with this PVT IP from Design FMEA to an ISO 26262 assessment report.

Systematic failures are caused during the design, development and manufacturing while specifying or implementing, and random hardware failures show up from random defects or aging effects. ISOS 26262 covers both systematic and random hardware faults. There are four Automotive Safety Integrity Levels (ASIL):

ASIL

The strictest ASIL-D requires that components have <1% single points of failure, and <10% latent faults.

For reliability standards of SoCs the AEC-Q100 specifies stress testing of automotive ICs across various temperature ranges, and this corresponds to a number of hours testing at a high temperature for electromigration reliability.

AEC-Q100 Grades

IP at Synopsys is characterized under three product classes:

  • Automotive Grade (AG), used for hard-IP only, automotive reliability but no functional safety work products
  • ASIL Random (AP), ISO 26262 Random Hardware Fault Metrics only
  • ASIL Compliant (AC), ISO 26262 full compliancy Systematic + Random

Summary

As an automotive driver and passenger I really want my trips to be safe, secure and reliable. The automotive industry has the same goals and has established working groups and standards over many years now. EDA and IP vendors like Synopsys have served the automotive segment well by creating the SLM applied to automotive IP certification.

Related Blogs

Posted on

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
by Daniel Nenni on 06-05-2023 at 6:00 am
Categories: Chiplet, EDA, Events, Scientific Analog
3 Comments

UCIe image2

Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog, using Scientific Analog’s XMODEL.

WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
DATE: June 29, 2023
TIME: 14:00-15:30 Pacific Time

Registration Link 

Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog, using Scientific Analog’s XMODEL.

This webinar is organized in two parts. The first part gives a brief overview of the UCIe standard and explains why XMODEL is the best way to model and verify UCIe PHY, especially considering the close interactions between its electrical layer and logical layer. It will show how to model various analog circuits in the electrical layer, including the phase-locked loop (PLL), delay-locked loop (DLL), duty-cycle corrector, phase interpolator, and transmitter / receiver circuits. Each circuit block is modeled using XMODEL primitives, which enable fast and accurate simulation of their analog behaviors in SystemVerilog.

The second part shows how you can design the finite-state machines (FSMs) in the logical layer, performing digital training and calibrations on the reference voltage levels, clock-to-data timing, lane-to-lane skews, and link data rate via a series of data transmission tests with pseudo-random bit sequences. All the FSMs are described in SystemVerilog, and with XMODEL, you can simulate this logical layer model interacting with the electrical layer model entirely in SystemVerilog. It implies that you can also use various features of SystemVerilog to check the thoroughness of your simulation, such as checking the FSM state coverage.

This webinar will be beneficial to everyone who is interested in the design and verification of UCIe PHY. For analog circuit designers, the presented models will help understand the requirements posed on each circuit block, such as the scaling of bandwidth to support a wide range of data rates from 4GT/s to 32GT/s. For digital verification engineers, the presented testbenches will show how to perform SystemVerilog-based verification on the systems containing analog circuits. And most importantly, by running the simulations with the provided models, you can gain a hands-on understanding on how the various components of a UCIe PHY work to realize a high-bandwidth interconnect between chiplets.

Registration Link 

Speaker’s Bio:

Jaeha Kim is CEO and founder of Scientific Analog, Inc., Palo Alto, CA and Professor at Seoul National University (SNU), Seoul, Korea. With a flagship product called XMODEL, he is pursuing ways to make analog design and verification as efficient as digital. Dr. Kim received the B.S. degree from SNU in 1997, and the M.S. and Ph.D. degrees from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Dr. Kim was with Stanford University as Acting Assistant Professor and with Rambus, Inc. as Principal Engineer. Prof. Kim is a recipient of the Takuo Sugano award for Outstanding Far-East Paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea by the National Academy of Engineering of Korea in 2020.

Also Read:

Chiplet Interconnect Challenges and Standards

Chiplet Q&A with John Lee of Ansys

eFPGA Enabled Chiplets!

Chiplet Modeling and Workflow Standardization Through CDX

 

Podcast EP165: The Impact of Mobiveil Across the Industry with Ravi Thummarukudy

Podcast EP165: The Impact of Mobiveil Across the Industry with Ravi Thummarukudy
by Daniel Nenni on 06-02-2023 at 10:00 am

Dan is joined by Ravi Thummarukudy. Ravi is CEO of Mobiveil, a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services with designs deployed in millions of units of silicon embedded in communications and consumer products worldwide.

Dan explores the silicon IP products, platforms and design services offered by Mobiveil with Ravi. It turns out the company is involved in a broad range of product development services and its IP unlocks many markets for its customers. Ravi explores the trends in the industry and the impact Mobiveil is having across a wide range of markets and applications.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

A Primer on EUV Lithography

A Primer on EUV Lithography
by Fred Chen on 06-02-2023 at 6:00 am
Categories: Lithography

Litho historical trend Fig 1

Extreme ultraviolet (EUV) lithography systems are the most advanced lithography systems in use today. This article is a basic primer on this important yet complex technology.

The Goal: A Smaller Wavelength

The introduction of 13.5 nm wavelength continues a trend the semiconductor industry had been following a wavelength reduction since the use of blue light (436 nm “g-line” wavelength) for feature sizes >1 micron. The light is projected through a mask (or “reticle”) which has the circuit pattern printed on it. The transmitted image is then demagnified when finally projected onto the wafer. The minimum pitch is half the wavelength divided by the numerical aperture (NA) of the system. The NA of an optical system is a dimensionless number that indicates the range of angles over which the final lens can focus light. Wavelength reduction is not trivial, as it means the energy of the photons is increased in inverse proportion. Consequently, there is high absorption in all materials. Thus, all-reflective off-axis optical systems are needed. This has led to the development of so-called “ring-field” projection systems, which lead to rotating the illumination across the exposure field [1]. Pre-EUV optical systems could rely on on-axis transmissive optics, which simplified the illumination setup by having no rotation.

A Different Mask

The use of the EUV wavelength also led to an overhaul of the mask structure. The mask is also a reflecting element. The reflection is achieved with a multilayer consisting of at least 40 molybdenum/silicon bilayers. The mask pattern uses an absorbing layer, currently based on tantalum, which is several wavelengths thick. With the off-axis illumination scattering through the absorber pattern and propagating and reflecting through the multilayer, 3D effects are inevitable in affecting the final image on the wafer [2].

The mask is also protected by a thin membrane called the pellicle, which stands off a certain distance from the mask surface. Developing a pellicle for EUV was a big deal, as light has to pass through it twice as a non-reflecting transmitting element.

Changing the Numerical Aperture

The numerical aperture in current EUV systems is 0.33. In a future generation of EUV systems, the numerical aperture will be increased to 0.55. This is expected to enable 0.6x smaller feature sizes, from the wavelength/NA proportionality. However, the depth of focus is expected to suffer by being reduced faster than the resolution, as it is roughly proportional to wavelength/(NA)^2 (Figure 1) [3]. For 0.55 NA EUV, this has led to concerns with the use of resist (the absorbing image layer on the wafer) as thin as 20 nm [4].

Figure 1. Historical trend of depth of focus vs minimum pitch [3].
A 0.55 NA system has additional complications. First, it is a half-field system, which means two mask scans are needed to fill the same area as a single mask scan in an earlier system [5]. Secondly, there is a central obscuration projected by the last two optical elements. This constrains the illumination as well as certain combinations of pitches [6]. Finally, polarization becomes important for pitches which may make use of 0.55 NA [7].

The obscuration is the fundamental systematic difference that affects projected scaling from the current 0.33 NA systems. There will be light loss just before reaching the final focusing element. In addition, the image quality will be fundamentally changed. Key components of the image diffraction spectrum. Figure 2 shows a 68 nm pitch bright line under illumination tailored for 28 nm pitch. The appearance is normal without obscuration, but with the obscuration in place, the central peak is diminished and the sidelobes beside it are enhanced, since the first diffraction order is removed. These sidelobes can print stochastically [8].

Figure 2. (Left) 68 nm pitch line under 28 nm pitch illumination, with vs. without obscuration. (Right) Stochastic sidelobe printing (top view) for the obscured case (40 mJ/cm2 absorbed) [8].
It’s Not Only the EUV Light…

EUV lithography is unfortunately plagued by a number of factors which are not obvious from the classical optical treatment so far considered. The EUV light is a form of ionizing radiation, meaning it releases electrons in the resist upon absorption. The photoelectrons (~80 eV) are from the direct ionization, and the secondary electrons are from the ionization caused by these and subsequently released electrons. The energy deposited by the electron scattering will obviously heat the resist, leading to outgassing, which will contaminate the optical elements in the EUV system. For this reason, EUV systems now contain a minimally absorbing hydrogen ambient that will keep the surfaces of the optical elements clean without oxidizing them. However, hydrogen has been known to also cause blistering [9].

Figure 3. Electron release processes following EUV photon absorption in the resist.

The electrons also spread out from the original photon absorption site, leading to the originally defined image being blurred. The effects of this blur are easily felt several nanometers away. Aggravating the spreading effect further is the inherent randomness of the entire chain of events.

EUV Reveals the Stochastic Nature of Lithography

Photon absorption and electron scattering are all inherently random events. These lead to CD non-uniformity and edge roughness, and even placement errors and serious defects. Stochastic effects are more serious with lower absorbed photon density. Thinner resists reduce absorption, enhancing this effect. However, increased photon density leads to increased electron number density and increased electron blur, whose randomness leads to stochastic defects [10]. DUV lithography had not dealt with stochastic issues mainly because the feature sizes were large enough to secure enough photons, but EUV could not exploit this benefit.

References
  1. Antoni et al., Proc. SPIE 4146, 25 (2000).
  2. Tanabe, Proc. SPIE 11854, 1185416 (2021).
  3. J. Lin, J. Micro/Nanolith., MEMS, and MOEMS 1, (2002).
  4. https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography
  5. Davydova et al., Proc. SPIE 12494, 124940Q (2023).
  6. https://www.youtube.com/watch?v=1HV2UYABh4E
  7. https://www.youtube.com/watch?v=agMx-nuL_Qg
  8. https://www.youtube.com/watch?v=sb46abCx5ZY
  9. https://www.youtube.com/watch?v=FZxzwhBR5Bk&t=3s
  10. https://www.linkedin.com/pulse/secondary-electron-blur-randomness-origin-euv-stochastic-chen

Also Read:

SPIE 2023 – imec Preparing for High-NA EUV

Curvilinear Mask Patterning for Maximizing Lithography Capability

Reality Checks for High-NA EUV for 1.x nm Nodes

Posted on

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks
by Kalar Rajendiran on 06-01-2023 at 10:00 am
Categories: EDA, IP, Siemens EDA

PCIe TLP Encryption

In the fast moving world of data communications, the appetite for high speed data transfers is accompanied by a growing need for data confidentiality and integrity. The wildly popular PCIe interface standard for connectivity has not only been increasing data transfer rates but has also introduced an Integrity and Data Encryption (IDE) security option. The introduction of IDE features in PCIe enables the processing of higher data bandwidths while encrypting the data to maintain its integrity.

Siemens EDA has a published a whitepaper that discusses the encryption flow used in IDE Transaction Layer Packets (TLPs) in PCIe and the underlying software stack. The paper explains how IDE ensures security against digital attacks on TLPs transferred from the transmitter to the receiver, including link-to-link connections and devices connected through switches. The TLPs are encrypted using keys exchanged during IDE key management. Furthermore, the whitepaper explains the underlying protocols used in IDE, including data object exchange (DOE), component measurement and authentication (CMA), and security protocol and data model (SPDM).

Data Object Exchange (DOE)

Data Object Exchange (DOE) in PCIe is an extended capability introduced to transfer various types of data objects between devices. Each vendor can define specific data objects, which are identified by a vendor ID assigned by PCI-SIG. Data are transferred as data objects, one double word (32-bits) at a time, forming packets through configuration write transactions in PCIe. The transmitting device sets the DOE go bit after sending the entire length of the data object. The receiving device consumes the data and begins forming a response. Once the response is ready, the receiving device sets the DOE data object ready bit in its configuration space. The transmitter reads the response one double word at a time until the data object ready bit is high. This process enables the transfer of data from one device to another.

Component Measurement and Authentication (CMA)

The Component Measurement and Authentication (CMA) feature in PCIe relies on the underlying Security Protocol and Data Model (SPDM) protocol. CMA utilizes the DOE feature to transfer packets for secure connection establishment. Within the CMA/SPDM framework, the authenticity of connected devices is verified using digital signatures and public key cryptography. This process ensures that the devices involved in the connection are genuine and trusted. Once the authenticity of the connected devices is established, a secure connection is formed between the requester and responder. The secure CMA/SPDM protocol is then utilized to transfer data objects securely. The data objects are transmitted using the negotiated algorithm that was employed during the establishment of the secure connection.

IDE Key Management

IDE key management is used to exchange keys that will be utilized to encrypt IDE TLPs. The process involves exchanging keys on a per sub-stream basis for both transmitting and receiving TLPs. There can be two sets of keys identified by the K bit in the IDE prefix, with each set containing different keys for the Tx and Rx directions. There are seven different types of packets involved in the IDE key management process, each identified by an object ID field. The full details are described in the whitepaper.

Integrity and Data Encryption (IDE)

The goal of securing data transfers is to not only prevent unauthorized access but also to prevent tampering. Even with encryption, it is possible that attackers may be able to modify the data without the receiver’s knowledge unless there is a check for data integrity. The Message Authentication Code (MAC) feature of the IDE mechanism makes data integrity check possible. A secure state is achieved through the establishment of a secure connection using CMA/SPDM, configuration of keys using IDE key management, and enabling IDE by setting the IDE enable bit. The whitepaper goes into details of the transmit-receive data flow and the Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) encryption/decryption process using keys and initialization vectors. Based on the MAC check, an IDE stream can be marked as being in secure state or insecure state. An IDE stream can transition from secure to insecure state if the security condition is compromised.

 

The IDE mechanism also provides flexibility in securing TLP transfers. The establishment of an IDE stream between two ports can be accomplished by connecting using Link IDE or Selective IDE. When a switch is present between the ports, selective IDE is used to encrypt the packets transferred between them. Link IDE and selective IDE can work independently or together for directly connected ports.

Verification of IDE Feature with Siemens EDA’s Questa VIP

Siemens QVIP serves as a comprehensive verification solution offering support for the entire IDE feature verification process. It includes stimulus generation, assertion checks, error injection capabilities, and extensive sequence libraries. The presence of debug and log features further enhances the efficiency and effectiveness of the verification process.

Summary

The whitepaper also goes into details of IDE TLP prefixes (M-bit, K-bit, T-bit and P-bit) and what purpose they serve. For example, the presence of the M bit in an IDE prefix indicates whether a MAC is present or not. The paper also covers TLP aggregation that allows multiple TLPs to be combined into a single unit for transmission for achieving increased throughput.

The whitepaper will be a valuable read for anyone involved in implementing data integrity and security for PCIe-based systems.

Also Read:

Emerging Stronger from the Downturn

Chiplet Modeling and Workflow Standardization Through CDX

Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Posted on

WEBINAR: Driving Forward with UWB Radar: Enhancing Child Safety in Automotive

WEBINAR: Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
by Daniel Nenni on 06-01-2023 at 6:00 am
Categories: Automotive, Ceva, Events, IP

CEVA UWB Radar Webinar Email Invitation 230521

 

The rapid advancement of UWB (Ultra-Wideband) wireless technology has garnered significant attention and interest, thanks to its adoption by leading smartphone brands and its versatile range of applications. Within the automotive industry, UWB has already emerged as the preferred choice for Digital Keys in the premium segment. Moreover, the integration of UWB anchor points in modern vehicles presents a cost-effective platform for implementing advanced in-cabin radar capabilities, particularly for Child Presence Detection (CPD). This webinar aims to provide valuable insights into UWB technology, its functionality, and the role it plays in improving child safety in automotive environments.

Register Here

UWB Technology and Ecosystem

To comprehend the potential of UWB radar in automotive applications, it is essential to understand the underlying technology and the ecosystem surrounding it. The UWB Alliance, CCC (Car Connectivity Consortium), and FiRa (Fine Ranging) are key players in promoting UWB technology. The UWB Alliance fosters collaboration and innovation among industry leaders, driving the development and adoption of UWB solutions across various sectors. CCC focuses on standardizing the implementation of UWB technology in vehicles, ensuring interoperability and seamless integration with other connected car technologies. FiRa, on the other hand, is dedicated to advancing UWB’s precise positioning capabilities, enabling enhanced location-based services.

How UWB Radar Works

UWB radar leverages the unique characteristics of ultra-wideband signals to enable accurate and reliable detection and ranging. UWB signals consist of extremely short pulses with a wide frequency spectrum, allowing for high-resolution sensing. By transmitting these pulses and analyzing the reflections, UWB radar can identify and locate objects with exceptional precision. This technology excels in differentiating between closely spaced objects and can operate effectively in challenging environments with high levels of interference.

CEVA’s UWB and Radar Solutions

CEVA, a leading provider of wireless connectivity and smart sensing technologies, offers cutting-edge UWB and radar solutions for automotive applications. During the webinar, participants will gain insights into CEVA’s UWB technology, which provides secure and accurate positioning for digital key solutions. CEVA’s radar solutions leverage UWB technology to enable advanced in-cabin features such as Child Presence Detection. By integrating UWB radar into vehicles, automakers can enhance child safety by detecting the presence of a child within the car. Additionally, UWB technology enables new features based on gesture recognition, such as opening the trunk with a simple hand gesture.

Target Audience

This webinar is designed to benefit system engineers, SoC (System-on-Chip) designers, and product managers who are involved in UWB device development and are interested in incorporating radar capabilities into their products. Professionals from diverse industries, including automotive, industrial, consumer electronics, and others, will find this webinar valuable for understanding the potential applications of UWB radar and its role in enhancing safety and convenience in their respective domains.

Conclusion

As UWB wireless technology gains traction across various industries, its implementation in the automotive sector holds immense potential, particularly in improving child safety. The integration of UWB anchor points in modern vehicles creates a cost-effective platform for deploying advanced in-cabin radar systems, enabling features like Child Presence Detection. This webinar offers a comprehensive overview of UWB technology and its ecosystem, provides insights into the working principles of UWB radar, and showcases CEVA’s UWB and radar solutions for automotive applications. By attending this webinar, participants will gain valuable knowledge and perspectives on leveraging UWB radar to enhance child safety and drive innovation in the automotive industry.

Register Here

Also Read:

DSP Innovation Promises to Boost Virtual RAN Efficiency

All-In-One Edge Surveillance Gains Traction

CEVA’s LE Audio/Auracast Solution

CEVA Accelerates 5G Infrastructure Rollout with Industry’s First Baseband Platform IP for 5G RAN ASICs

Posted on

Real-Time AI-driven Image Signal Processing with Reduced Memory Footprint and Processing Latency

Real-Time AI-driven Image Signal Processing with Reduced Memory Footprint and Processing Latency
by Kalar Rajendiran on 05-31-2023 at 10:00 am
Categories: AI, IP, Semiconductor Services, VeriSilicon

AI ISP for Automotive, Low Light Image Enhancement

In our day to day lives, we all benefit from image signal processing (ISP), whether everyone realizes it or not. ISP is the technique of processing image data captured by an imaging device. It involves a series of algorithms that transform raw image data into a usable image by correcting for distortions, removing noise, adjusting brightness and contrast, and enhancing features. So, ISP by itself is not something new.

What is new though is leveraging artificial intelligence (AI) to enhance ISP to yield better results than traditional ISP can. Firstly, in the field of digital photography, AI can significantly enhance ISP capabilities. Traditional ISPs are effective at processing images, but AI can take this to the next level. For instance, AI can help in noise reduction, improving the image’s clarity, especially under low-light conditions. Moreover, AI algorithms can recognize various scenes or objects in the image, enabling automatic adjustments to different parameters like brightness, contrast, and saturation for optimal results.

In the world of autonomous vehicles, AI-enhanced ISPs can process real-time images to understand the vehicle’s surroundings better, aiding in decision-making. Traditional ISPs can struggle with different lighting conditions or object detection at high speeds, but AI can improve upon these aspects, enhancing the vehicle’s ability to react to potential hazards and improve overall road safety.

Lastly, in the realm of surveillance and security, AI-enhanced ISPs can process images from CCTV footage more effectively. AI can help detect suspicious activities, recognize faces, or identify objects left unattended, providing real-time alerts and enhancing overall security measures.

But how to implement AI-based ISP? It is easier said than done. There are a lot of challenges to overcome.  AI algorithms are fast advancing, requiring an AI-ISP solution to be programmable. AI models require a lot of computational power. Conventional  techniques combining separately developed ISP and NPU often require a lot of memory to store entire frames of images for processing. Accessing DDR-SDRAMs consume a lot of power. And this loosely coupled frame-based solution will introduce latencies measured in frames, which is unacceptable for many applications.

What is needed for today’s applications is real-time processing at low latency and low power consumption. Making the solution DDR-less is even more attractive as it will reduce the system power requirements significantly. Of course, NPUs are key to an AI-based ISP solution. But there is a lot more to arriving at a DDR-less, low latency, low power AI-ISP solution. This was the topic of Mankit Lo’s presentation at the recent Embedded Vision Summit conference. Mankit, who is the Chief Architect, NPU IP Development at VeriSilicon walked the audience through the various aspects that need to be addressed.

Solution Requirements

ISP Requirements

In traditional hardware for ISP, there are many modules in the pipeline stages to correct the potential artifacts of the imaging system. To perform AI-ISP, the chosen ISP should be flexible enough to allow the customer to pick and choose the modules to replace or enhance.

NPU Requirements

As ISP tasks are computationally huge and intense, the task is usually partitioned to be executed on many NPU cores. There is a lot of image overlap on the input side going into the NPU cores. Even for a 3×3 convolution layer inside the neural network, the overlapping requirement for just a few pixels could result in a huge overlap at the whole network level. The overlap needs to be minimized for reducing the memory, power, and computing demand on the system. The way to do it is through layer-level overlap sharing.

What is needed is an NPU that can handle raster lines and become part of the ISP processing pipeline, making the solution DDR-less, low latency, and low power. The NPU needs to be programmable to handle a changing AI network model landscape and deliver very good performance. It also needs to be able to support Per Layer Overlap Sharing which results in not requiring any overlap on the image input side.

VeriSilicon Offers

Specific to the topic of AI-ISP, VeriSilicon provides ISP, NPU, and the FLEXA-PSI interface to seamlessly connect these IPs. Refer to the block diagram of a VeriSilicon AI-ISP solution.

The customers need to just add their custom AI algorithms to the mix to complete their unique solution. VeriSilicon can also provide algorithms relating to the ISP such as noise reduction, demosaicing, and different types of detection such as facial detection and scene detection, etc.

Click here to learn more about VeriSilicon’s NPU IP offering.

Click here to learn more about VeriSilicon’s ISP IP offering.

VeriSilicon offers custom silicon services and a very broad portfolio of IP for many different markets. Learn more at VeriSilicon.com

Also Read:

VeriSilicon’s VeriHealth Chip Design Platform for Smart Healthcare Applications

VeriSilicon’s AI-ISP Breaks the Limits of Traditional Computer Vision Technologies

Posted on

Investing in a sustainable semiconductor future: Materials Matter

Investing in a sustainable semiconductor future: Materials Matter
by Daniel Nenni on 05-31-2023 at 6:00 am
Categories: EMD Electronics, Foundries, Semiconductor Services, TSMC

EMD LinkedIn Twitter Materials Matter

In 2020 TSMC established its Net Zero Project with a goal of net zero emissions by 2050. I remember wondering how could this possibly be done before 2050 or at all for that matter. After working with TSMC for 20+ years I have learned never to bet against them on any topic and green manufacturing is one of them, absolutely.

TSMC presented on green manufacturing at the recent symposium in Silicon Valley. Clearly energy and water resources are critical parts of any net zero project but carbon emissions are also a of great importance and that means materials. In regards to semiconductor manufacturing materials we have experts here on SemiWiki.

EMD Electronics has a presence in 66 countries and over 100 years of invaluable experience in the electronic materials space delivering a broad portfolio of semiconductor and display materials for cutting-edge electronics.

EMD Electronics recently published a paper: INVESTING IN A SUSTAINABLE SEMICONDUCTOR FUTURE – MATERIALS MATTER.

It is a very interesting comprehensive look at innovative sustainable semiconductor materials techniques that decrease carbon emissions, improve resource efficiency and productivity, and highly contribute to achieving net zero semiconductor.

“It is amazing where collaboration can take us. Sustainability is no longer the result of individuals; only by working together can we get closer to our goals for a sustainable future! Brita Grundke, Head of Sustainability, EMD Electronics”

Here is the introduction. This paper is freely available and well worth the read for semiconductor professionals at all levels:

Emissions from semiconductor manufacturing are a growing segment of global greenhouse gas (GHG) emissions. There are two reasons behind this trend. First, the demand for semiconductor chips is growing. Our technology appears in everything from mobile phones to automobiles, where the number of chips per vehicle increases every year. Data storage, which relies on the semiconductor industry, is exploding. Second, today’s manufacturing processes have more deposition and etch steps than ever. Each step consumes water and electricity and creates GHG emissions.

Semiconductor companies large and small talk about achieving climate neutrality by 2030. That sounds like a great goal. But merely achieving that goal won’t solve the emissions problem. How we get there matters.

Buying carbon offsets is an easy way out. It isn’t the best long-term answer, because many offsets are not as effective as they claim to be. Some may even make the problem worse, defeating the purpose [1]. And relying on offsets can make internal actions seem less pressing. It is best to see offsets as a temporary or last-choice option.

Semiconductor industry leaders are, of course, doing more than buying offsets. They are investing in renewable energy, improving the energy efficiency of their processes, and finding ways to reduce waste. These actions are helpful, and we must do more. Despite modest success in reducing emissions per wafer or per revenue, demand for semiconductor chips is growing faster than the improvements can handle. We need more drastic reductions, and that starts by examining the sources.

Bottom Line: Climate change is real and semiconductor manufacturing is under a microscope now that it is being regionalized due to the shortages and supply chain issues we suffered during the pandemic. If you really want to know why semiconductor manufacturing left the US it was due to the Environmental protection Agency crack down on water, ground, and air pollution. I grew up in Silicon Valley so I had front row seat to the environmental issues of semiconductor manufacturing. Now that semiconductor manufacturing is coming back to the US and other parts of the world sustainability is front and center once again.

Also Read:

Step into the Future with New Area-Selective Processing Solutions for FSAV

Integrating Materials Solutions with Alex Yoon of Intermolecular

Ferroelectric Hafnia-based Materials for Neuromorphic ICs