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Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
by Kalar Rajendiran on 10-25-2023 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Siemens EDA

3D IC Cross Section Illustration

One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields an array of benefits, including reduced latency, high-bandwidth data transfer, lower manufacturing costs, increased wafer yields, minimized power consumption, and ultimately, lower overall costs. While not yet mainstream, the growing standardization of chiplets and the development of supporting tools are paving the way for the practical and profitable implementation of 3D ICs for both large and small players. These appealing benefits have driven significant growth and development in advanced heterogeneous packaging and 3D IC technology. However, this progress has also introduced challenges related to manufacturability and reliability and must be addressed for 3D ICs to become a mainstream reality.

Siemens EDA has published an eBook that addresses these challenges and offers up solutions to help deliver 3D IC semiconductor reliability. Anyone involved in the development of 3D ICs will find the eBook very informative. The following is an overview of the salient points from the book.

Challenges in Ensuring 3D IC Semiconductor Reliability

3D ICs have brought with them a host of challenges, spanning the selection of tools and methodologies, parasitic extraction, and the task of heterogeneous integration.

Sign-off strategies of 2D ICs heavily rely on design rule kits provided by foundries, typically designed for single-process System-on-Chip (SoC) designs. However, this conventional approach falls short in the realm of 3D IC advanced heterogeneous packaging, where multiple layers with varying processes are involved. Traditional LVS relies on recognizing electrical connections between pins, a feature that passive components lack by definition. To address this, a method is required to comprehend the impact of passive components and consider their interconnection role alongside active devices. This is critical as accurate post-assembly netlisting and simulation results hinge on detailed wire placements and material information. Unlike System-on-Chips (SoCs) that are coplanar, 3D ICs incorporate stacking with components at different vertical depths, rendering them non-coplanar. This non-coplanar nature introduces intricate challenges for semiconductor and IC packaging designers, particularly regarding the assessment of interactions between components with different process technologies and iterative evaluations. The issue also involves determining which interactions are essential to verify to avoid wasting resources on unnecessary checks, further complicating the design and manufacturing process of 3D ICs.

Solutions for 3D IC Semiconductor Reliability

Overcoming these challenges necessitates a blend of innovative strategies, tools, and methodologies.

Accurate Modeling: The initial step in addressing the challenges of 3D ICs is the creation of highly accurate models. Components like Through-Silicon Vias (TSVs) require precise modeling to account for their parasitic elements.

Parasitic Extraction: Accurate parasitic extraction is vital for understanding the effects of these new components on signal integrity, power efficiency, and overall performance. Utilizing advanced extraction tools enables engineers to capture intricate parasitic elements introduced by components like TSVs and micro bumps.

Data Representation: For organic-based (PCB-oriented) 3D ICs, intelligent data representation is paramount. This entails including information such as net names, via details, and structural elements natively in the design database, streamlining the setup time for parasitic extractions and reducing the likelihood of errors.

Early Planning and Floorplanning: The utilization of planning tools is critical to facilitate the integration of diverse components and the creation of a reliable floorplan. This planning step is indispensable for comprehending the interactions between different layers and components within a 3D IC.

Summary

The challenges in ensuring the reliability of 3D ICs are considerable. However, by embracing innovative tools, methodologies, and intelligent data representation, it’s feasible to overcome these hurdles. With accurate modeling, precise parasitic extraction, and innovative design strategies, engineers can unlock the full potential of 3D IC technology while adhering to the highest standards of reliability. As the semiconductor industry evolves, 3D ICs are set to play a pivotal role in shaping the future of electronic devices, promising more powerful, energy-efficient, and compact solutions for consumers.

You can download the “Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration” eBook here.

Also Read:

The Path to Chiplet Architecture

Placement and Clocks for HPC

AI for the design of Custom, Analog Mixed-Signal ICs

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Powering eMobility Through Silicon-Carbide Substrates

Powering eMobility Through Silicon-Carbide Substrates
by Bernard Murphy on 10-25-2023 at 6:00 am
Categories: Automotive, Foundries, Soitec
2 Comments

SOITEC SEPTEMBRE 2023

While writing on infotainment and ADAS I sometimes wonder about the devices that make an EV run. These have nothing to do with digital or software wizardry. While logic and software play a role, the real heart of EV power is in power electronics driving motors, regenerative braking and charger options at home and on the road. Technologies in support of power electronics are predominantly bipolar (e.g. IGBT) and silicon carbide (SiC). SiC is growing fast, driven particularly by Tesla (barring some recent hiccups). Which is good news for Soitec who build the SiC substrates/wafers on which many semis and Tier1s can manufacture their SiC power devices. Soitec just announced a new fab to create these substrates.

A very elementary primer on power electronics in EVs

Start with the drive train. Previously. if I thought about it at all I vaguely assumed DC batteries driving DC electric motors. Completely wrong it turns out. The motors are AC for a variety of reasons, not least because controlling speed for a DC motor through a variable resistor would waste significant energy and reduce range. Driving AC motors from a DC supply requires an inverter, the first place where you will find SiC transistors.

The standard method to control speed in these systems is through pulse width modulation (PWM), a more energy efficient approach I would assume. SiC adds further to this advantage in several respects. It can tolerate higher voltages than silicon-based devices and can operate at higher frequencies, resulting in more compact designs. These devices also generate less heat. All of which means that a typical implementation will be lighter weight and more energy efficient, reducing cost and increasing the range of the car.

These benefits apply equally and then some to charging stations, particularly for fast charging. Rapid chargers can deliver 500-600kW of DC power from an AC supply, needing a full-wave rectifier capable of outputting that level of power. Again an SiC implementation will be smaller, more energy efficient, and lower cost than a silicon-based implementation, all significant considerations when it comes to scaling charging stations nationally.

Given social and political pressures to move to EVs, there is very active growth in this sector. One survey shows 28% CAGR through 2030, with major semiconductor suppliers including Rohm, Infineon, ST, OnSemi, and Wolfspeed.

Soitec and their SmartSiC technology

Remember that Soitec builds SiC substrates on which their customers manufacture SiC-based circuits like inverters and rectifiers. This technology depends on a technique called SmartCut®, invented at nearby CEA-Leti in Grenoble (France). SmartCut is a method to transfer a thin crystalline layer onto the top of another material, rather like an atomic scalpel slicing a layer off an SiC ingot, which is then placed on top of a poly-SiC wafer, yielding what Soitec call Auto SmartSiC®. The SmartCut method has become an industry standard apparently. Soitec claims significant SiC manufacturing  cost and energy advantages in this approach over other methods, important in what is likely to be a hot and competitive market.

The plant they have commissioned is in Bernin, just a little south of the ST Crolles fab, also close to Grenoble and CEA-Leti. They expect the plant to have a final production capacity of 500k SiC wafers per year. You can learn more about Auto SmartSiC HERE.

Also Read:

FD-SOI, the technology shaping the future of automotive radars

Soitec is Engineering the Future of the Semiconductor Industry

Semiconductors and Mobile Communications: 5G and Beyond

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Electronics Production Trending Up

Electronics Production Trending Up
by Bill Jewell on 10-24-2023 at 1:08 pm
Categories: China, Semiconductor Intelligence, Semiconductor Services

Unit Change Electronics 2H 2023

Production of electronic devices is finally on the uptrend following a post-pandemic slump in late 2021. According to IDC, smartphone shipments versus a year ago turned negative in 3Q 2021 at -6%. The decline hit a low of -18% in 4Q 2022. Since then, smartphones have been recovering. IDC data is not yet available, but Canalys estimated 3Q 2023 smartphone shipments were down only 1% from a year earlier. 4Q 2022 shipments should follow the typical pattern of an increase from 3Q shipments, which would result in a mid-single-digit year-to-year increase. IDC’s August forecast called for a 4.7% decline in full year 2023 smartphone shipments.

PCs are also on an uptrend. IDC estimated global PC unit shipments in 3Q 2023 were down 7.6% from a year earlier, a substantial improvement from the low of the 29% year-over-year decline in 1Q 2023. Again, based on typical fourth quarter versus third quarter trends, PC shipments in 4Q 2023 should increase by mid to high single-digits versus 4Q 2022. IDC’s PC forecast in August was a 14% decline for the full year 2023. The IDC forecast will likely be revised upward based on the 3Q 2023 data.

As the largest producer of electronic devices, China is key to understanding trends. August 2023 data shows China’s three-month-average electronics production in local currency (yuan) was up 2.6% from a year ago, the highest rate in eight months. Limited data on smartphone production shows August 2023 three-month-average units were down a slight 0.6% from a year ago, a major improvement from an 11.6% decline in March 2023.

China PC production is still weak, with August 2023 three-month-average units down 17% from a year ago. August is the twelfth consecutive month of double-digit declines. However, several major PC makers are in the process of shifting some PC production out of China. Of the four largest global PC suppliers, number one Lenovo is based in China while numbers two through four (HP, Dell, and Apple) are based in the U.S. As reported by Nikkei Asia in July 2023, HP plans to shift much of their laptop production out of China to Mexico, Thailand and Vietnam. The production outside of China could be up 5 million units in 2023, close to 10% of HP’s total PCs. In January 2033, PCMag reported Dell may move up to 50% of its PC production out of China by 2025. Also in January, Forbes stated Apple plans to shift much of the production of its MacBook PCs from China to Vietnam. These moves are primarily due to the impact of the COVID-19 pandemic and increasing trade tensions between the U.S. and China. While these production shifts are ongoing, Chinese data on PC production will not be a reliable indicator of global PC trends.

Electronics production in local currency for major Asia countries is primarily on an uptrend. As mentioned, China’s three-month-average electronics production in August versus a year ago accelerated to 2.6%. Taiwan production was up 9% in August, the strongest growth in eight months. In September, Vietnam production increased 0.6%, an improvement from seven consecutive months of year-on-year declines. South Korea reported a 6% decline in August, but it was an improvement from double-digit declines the previous three months. Japan’s August production was up a healthy 6.8% but decelerating from double-digit growth in the prior three months.

Electronics production in the U.S. and Europe is generally on a trend of decelerating growth. U.S. three-month-average production in August grew 1.2% from a year ago. This marked the ninth consecutive month of decelerating growth since a peak of 8.1% in November 2022. The 27 countries of the European Union (EU 27) reported 2.2% production growth in July, continuing a trend of single-digit growth following seven months of double-digit growth in May through November of 2022. UK production growth slowed to 1.1% in August after growth in the 7% to 17% range in the previous thirteen months. Differences in the type of electronic devices manufactured in the U.S. and Europe compared to Asia account for some of the differences in production trends. Asian countries mostly produce smartphones, PCs, televisions, and other consumer electronic devices. Production in the U.S. and Europe is more heavily weighted toward electronic devices sold to business – such as enterprise computing, data centers, communications infrastructure, and industrial electronics.

Based on the above trends, the electronics and semiconductor markets are primed for solid growth in 2024.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Also Read:

Nvidia Number One in 2023

Turnaround in Semiconductor Market

Has Electronics Bottomed?

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Generative AI for Silicon Design – Article 1 (Code My FSM)

Generative AI for Silicon Design – Article 1 (Code My FSM)
by Anshul Jain on 10-24-2023 at 10:00 am
Categories: AI, EDA
1 Comment

Generative AI for Silicon Design

In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article series, we delve into exciting experiments that demonstrates how Generative AI is revolutionizing semiconductor design.

Experiment 1 – FSM Diagram to SV Code

This first experiment showcases the remarkable capabilities of Generative AI by converting a Finite State Machine (FSM) diagram into SystemVerilog (SV) code. In this case, Google’s Generative AI Model – BARD was used to generate a SystemVerilog implementation of a vending machine FSM shown in the cover picture (sourced from https://www.softwareideas.net/fsm-finite-state-machine-diagram)

FSM Diagram of a Vending Machine

Generated Code

// Vending machine FSM
// Disclaimer: This code is not tested for correctness

module vending_machine (
  input clk,
  input reset,
  input coin_inserted,
  input product_selected,
  input product_dispensed,

  output reg dispense_product,
  output reg return_coin
);

  // Define the states
  localparam [2:0] IDLE = 3'b000;
  localparam [2:0] COIN_INSERTED = 3'b001;
  localparam [2:0] PRODUCT_SELECTED = 3'b010;
  localparam [2:0] PRODUCT_DISPENSED = 3'b011;
  localparam [2:0] OUT_OF_STOCK = 3'b100;

  // Define the registers
  reg [2:0] current_state;

  // Transition logic
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      current_state <= IDLE;
    end else begin
      case (current_state)
        IDLE: begin
          if (coin_inserted) begin
            current_state <= COIN_INSERTED;
          end else begin
            current_state <= IDLE;
          end
        end
        COIN_INSERTED: begin
          if (product_selected) begin
            current_state <= PRODUCT_SELECTED;
          end else begin
            current_state <= COIN_INSERTED;
          end
        end
        PRODUCT_SELECTED: begin
          if (product_dispensed) begin
            current_state <= PRODUCT_DISPENSED;
          end else if (out_of_stock) begin
            current_state <= OUT_OF_STOCK;
          end else begin
            current_state <= PRODUCT_SELECTED;
          end
        end
        PRODUCT_DISPENSED: begin
          current_state <= IDLE;
        end
        OUT_OF_STOCK: begin
          current_state <= IDLE;
        end
      endcase
    end
  end

  // Output logic
  always @(posedge clk) begin
    case (current_state)
      PRODUCT_DISPENSED: begin
        dispense_product <= 1'b1;
      end
      default: begin
        dispense_product <= 1'b0;
      end
    endcase
  end

  always @(posedge clk) begin
    case (current_state)
      OUT_OF_STOCK: begin
        return_coin <= 1'b1;
      end
      default: begin
        return_coin <= 1'b0;
      end
    endcase
  end

endmodule

FSM diagrams are widely used in silicon design, and here’s how Generative AI can play a pivotal role:

  1. Increased Productivity: With Generative AI, creating and updating diagrams becomes a breeze. Designers can now focus on high-level concepts and let the AI do the groundwork. This not only accelerates the development process but also allows for swift iterations when design changes are required.
  2. Higher Accuracy: FSM diagrams have become standardized tools in hardware design. Generative AI models are trained on a vast dataset, making them proficient in converting these diagrams into accurate SV code. The result is reduced human error and higher code quality.
  3. Improved Innovation: Generative AI’s speed and accuracy open doors to rapid exploration of new design ideas. Designers can brainstorm and experiment with various FSM diagrams, pushing the boundaries of innovation. This agility allows for quicker integration of advanced features in each generation of semiconductor devices.

Caution – A Reality Check

While Generative AI holds enormous promise, it’s essential to exercise caution. The generated code may not always be perfect. Designers must review and rigorously test the AI-generated code before deploying it in a production environment. A thorough validation process is crucial to ensure the reliability and functionality of the final semiconductor design.

Conclusion

Generative AI is a game-changer in semiconductor design development. Experiment 1 clearly illustrates its potential by simplifying the conversion of FSM diagrams into SV code, offering increased productivity, higher accuracy, and a boost in innovation. However, it’s vital to remember that AI-generated solutions should be used as a tool to enhance the creative process, not replace it entirely. With the right checks and balances, the synergy between human ingenuity and Generative AI can lead to groundbreaking developments in the semiconductor industry.

Also Read:

Generative AI for Silicon Design – Article 2 (Debug My Waveform)

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SRAM design analysis and optimization

SRAM design analysis and optimization
by Daniel Payne on 10-24-2023 at 6:00 am
Categories: EDA, MunEDA

SRAM design cell min

Every year EDA vendor MunEDA hosts a user group meeting where engineers present how they used automation tools to improve their IC designs, and one presentation from Peter Huber of Infineon caught my attention, it was all about SRAM design optimization. Peter has authored papers at IEEE conferences and been issued patents related to SRAM design. The schematic for a six-transistor SRAM cell is shown below:

SRAM bit cell. Source: Wikipedia

During a SRAM read cycle the Word Line (WL) goes active, then the stored bit values get transferred to the Bit Lines (BL), and finally a sense amplifier goes active to read out the differential Bit Lines. The delay between WL and BL is part of the Read Programmable Self-Timing (RPST), and is tuned by the circuit designer.

SRAM memory designers have several challenges to meet while optimizing the circuit design and layout:

  • Minimum operating voltage, Vmin
  • Sensitivity to small transistor geometries
  • Process variation effects
  • Power consumption
  • Layout density
  • Soft error rate

As the power supply value of Vdd is lowered then the SRAM bit cell eventually fails to operate, and that failure can occur during a Read cycle, Write cycle, or just by noise induced from nearby circuits switching. Influences on the memory failures come from how the core and periphery layouts are done, process and local variations, temperature, memory array size, and the yield criteria.

Yield prediction by simulation is challenging because multiple blocks are involved: bit cell and periphery such as sense amplifiers, multiplexers, self-timing circuitry, and so on. The SRAM designer hence faces multiple issue with parametric yield simulation:

  • The interactions between the blocks are relevant: A bit cell whose read current is exceptionally weak due to local variation of Vth may or may not be read correctly depending on the offset of the connected sense amplifier and other periphery, which in turn depends on the local Vth variation in those blocks.
  • Various blocks’ quantities must be considered, for example in an array of 32 sense amplifiers, each of which is connected to 1024 bit cells.
  • High effort of transient simulation of a single bit cell read cycle, because the transient simulation has to include layout parasitic effects of a large part of the circuit with high accuracy.
  • The statistical analysis must be repeated many times to analyze the effect of array size, macro settings for the self-timing, assist and boost circuitry.

Brute force Monte Carlo SPICE simulation of every cell’s read cycle in an extracted post-layout full chip netlist allows to calculate the statistically correct yield estimate but at a prohibitively large simulation effort. In the past, ML surrogate models could be used to guide the sampling but that still has a too large simulation effort for extensive analysis of the effects of SRAM macro settings.

Infineon now introduced a new two-step approach to simulate their SRAM design by using Worst Case Distance (WCD).

The WCD analysis consists of creating a simulation set with the WiCkeD tool for one Vdd and one probability plus sigma combination.  During this process the worst-case value for Read current (Iread) is determined, and then determining the worst-case sense-amp detuning. Finally, one transient simulation is run for each Programmable Self Timing (PST) setting, with back-annotated worst-cases cells from WCD analysis.

Separating the analysis into two steps has the advantage that the detailed statistical analysis of the sub-blocks is done independently in small netlists with short simulation time, whereas only a handful of slow transient runs of the full circuit are necessary to determine whether the combined worst-case blocks pass or fail the read cycle depending on different high-level macro settings (RPST).

In the past, a single combination of worst-case blocks was used for full-chip transient simulation, for example a 6-sigma worst-case bit cell combined with a 4-sigma worst-case sense amplifier. That was fast and sufficient for verification but overly pessimistic. In the new approach, multiple combinations are tested, and each single met point on the equi-probability curve guarantees a minimal total yield, so that one met point is enough to guarantee the yield and accept the supply voltage as working. In this way, the pessimism is eliminated so that simulated failure rates match very well with silicon measurements.

SRAM equi-probability curves

Simulation results produced the following plot where the Vmin value is on the Y-axis, and the read PST setting is on the X-axis.

Silicon measurements correlated very well with simulations, where the values for Vmin on Read and Write cycles were less than two percent off, as expected due to effects such as IR drop.

Summary

This group at Infineon was able to simulate and optimize Vmin operation values for SRAM designs by using a two-step methodology with the MunEDA WiCkeD tools: WCD plus transient simulation.  Python scripting was used to automate these analysis methods, and that feature is called GangWay.  With scripting they are able to setup and transfer to new memory architectures, reproduce simulation results quickly and transfer the verification task to other engineers.

WEBINAR:  Fast and Accurate High-Sigma Analysis with Worst-Case Points

Related Blogs

 

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Managing IP, Chiplets, and Design Data

Managing IP, Chiplets, and Design Data
by Daniel Payne on 10-23-2023 at 10:00 am
Categories: Chiplet, EDA, Keysight EDA

Managing IP min

Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked by manual methods. Other big questions that need to be answered are where to find the right IP, or how to make others aware that you’ve created new IP that could be re-used on new projects.

Companies like Cliosoft, now part of Keysight EDA, have been automating features for IP reuse like finding IP, creating new IP, and safely reusing IP in systems for many years now. A webinar on November 1st at 10:00AM PT is planned, Mastering the Art of Managing IP, Chiplets and Design Data.

The basic SoC design flow will be reviewed in the webinar, along with the multiple engineering roles that form the design and verification team. Having a way for each of these team members to communicate and collaborate during the project ideation and implementation is crucial for success.

IC Design Flow and Team Members

Finding the right IP block either in-house or from third-party vendors is automated with the Keysight IP Management (HUB) tool. System architects typically partition a complex design into smaller pieces using hierarchy as an abstraction, then identify all of the IP blocks required. The members of the design and verification teams may be geographically dispersed, causing communication and documentation challenges. Proper data management tools help with these tasks of partitioning an electronic design, securing the needed IP blocks, and even geofencing IP to conform with license agreements.

Managing IP across geographies

In the webinar both the SoC flow and Chiplet design flows are addressed in terms of managing IP and design data. Common challenges for system design include managing the BOM, IP version conflict resolution, assembly of IP subsystems, safely connecting IP blocks to a NoC, reusing design knowledge of connecting to NoCs.

A team member may update the status of an IP block by attaching a tag to that block, like Verification Ready, then automatically informing other team members of the status change, so everyone knows the history and sequence of who has worked on each IP block, and what the next step is in the design flow. An engineer may tag an IP block as RTL Signoff, then a workflow triggers a snapshot or version made of that hierarchy used for future audits, and finally sends emails to all stake holders. Industries like the DOD and Aerospace have rigorous requirements on tracking specifications and requirements into implementation, so running audits is required for traceability.

Legal teams are also interested in knowing which IP is included in every design that is shipped, so that they can properly manage contract agreements for licensed IP blocks.

The Cliosoft tools are fully integrated in the Keysight EDA tool flow, along with IC tool flows from Cadence and Synopsys. EDA tool users stay within their favorite vendor tool to access all the Data Management (DM) features, making for a quick learning curve. Project management tools like Jira are also integrated, along with bug tracking tools like Bugzilla.

Summary

Attend the webinar on November 1 at 10:00AM PT to learn more about data and IP management, even managing the engineering lifecycle from chip specification all the way to tapeout. Both SoC and chiplet design approaches benefit from using automation beyond what a typical PLM system can provide.

Related Blogs

Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines

Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines
by Daniel Nenni on 10-23-2023 at 8:00 am

Dan is joined by Dr. Walden Rhines. Wally is a lot of things, CEO of Cornami, board member, advisor to many and friend to all. For this discussion he is the Executive Sponsor of the SEMI Electronic Design Market Data report.

Dan explores the Q2 results summarized in the report with Wally. Overall growth was around 5%, a much lower number than prior quarters. Digging into the data a bit Wally points out that the EDA segment of the market continues to show very strong growth. What is different this quarter is a lower growth for IP. Wally believes this is due to a re-classification of revenue that will normalize in subsequent quarters.

Dan explores more detailed analysis of the data from around the world with Wally, including some very interesting regional trends in this informative discussion.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers
by Kalar Rajendiran on 10-23-2023 at 6:00 am
Categories: EDA, IP, Synopsys
2 Comments

112G Ethernet PHY IP EOE InterOp Demo JR5 0179

Electrical copper interconnects, once the backbone of data center networks, are facing growing challenges. Rapid expansion of AI and ML applications is driving a significant increase in cluster sizes within data centers, resulting in substantial demands for faster I/O capabilities. While the surge in I/O requirements is being addressed by faster SerDes PHY technologies, interconnects are facing scaling challenges from power consumption perspective. This coupled with the imperative to flatten networks to minimize latency is driving the trend to optical interconnects. Another reason for this shift is the ability of optical interconnects to reduce channel loss, thereby improving data transmission efficiency. Optical interconnects also address the rigidity and space limitations associated with copper cables, providing greater flexibility in designing and expanding data center architectures.

The Rise of Optical Interconnects

Optical data transfer over optical fiber with minimal loss (compared to copper cable) over longer distances has been in use for a long time. Optical interconnects are nothing new to the industry, but the current implementation approach uses traditional optical modules which consumes a lot of power. Consequently, there is a significant push to integrate optical components into semiconductor electronics. The goal is to enable faster data transmission over longer distances, at low latencies and reduced power consumption.

Silicon Photonics

Silicon photonics is a field that leverages the semiconductor manufacturing process to create optical components on silicon substrates. Integrating photonics on silicon offers numerous advantages but comes with its set of challenges. One major challenge is achieving efficient light generation, modulation and amplification on a silicon platform. Silicon, being an indirect bandgap material, is not suitable for generation of light. As a result, integration of direct bandgap materials is required, which can be complex and costly.  Silicon photonics fabrication processes can vary from one foundry to another, some allowing monolithic integration of electronics and photonics on the same chip, while the others requiring co-packaging of electronic and photonic chips. Overcoming these challenges is crucial for realizing the full potential of silicon photonics in data centers.

OpenLight’s Integrated Photonic Integrated Circuits (PICs)

OpenLight has developed a technology to heterogeneously integrate indium phosphate (InP) on to a standard silicon process flow and create highly integrated devices. OpenLight’s PICs represent a significant advancement in the field of optical communication technology. These integrated circuits bring together a multitude of optical components, such as lasers, modulators, detectors, and waveguides, onto a single chip, offering a compact and highly efficient solution for data transmission and photonics applications. OpenLight’s Integrated PICs are engineered to meet the increasing demand for high-speed data transfer, lower power consumption, and enhanced performance. By consolidating these optical elements into a single package, OpenLight’s Integrated PICs facilitate seamless integration with electronic circuits, enabling more efficient and cost-effective solutions for data centers.

Synopsys and OpenLight Collaboration

Synopsys and OpenLight have collaborated to develop 100G/200G electro-optical interfaces that enable low power, low latency data centers. This electro-optical interface offers pluggable direct drive or linear or non-retimed interfaces. It enables data centers to choose high-speed connectivity options that suit their specific performance and power efficiency requirements, fostering flexibility and scalability in their network architecture.

Demo of 100G Electro-Optical Interface with TDECQ of 1.46dB

At the 2023 European Conference on Optical Communication (ECOC), Synopsys demonstrated its 112G Ethernet PHY IP Electrical-Optical-Electrical (E-O-E) interoperability success with OpenLight’s PIC. The eye diagram showed a TDECQ of 1.46dB, which is excellent. TDECQ stands for “Total Differential Eye Closure Quaternary,” a parameter used in optical communication systems to assess the quality of the received signal. TDECQ quantifies the amount of signal distortion or closure of the eye diagram in a digital communication system.

As shown in the block diagram below, the host PHY is driving the optical engine directly, avoiding the use of secondary PHY and DSP in the module. This approach is called linear drive or direct optical drive and leads to a 25% to 35% reduction in power consumption over a traditional optical module approach.

OpenLight recently unveiled the test results for the 200G Electro-Absorption-Modulator (EAM). This is a significant milestone toward enabling a 200G direct optical drive soon.

The Path to Success with Co-Simulation

The intricate interplay between optics and electronics requires seamless coordination to ensure optimal performance. One of the essential steps in harnessing the full potential of optical interconnects and high-speed SerDes is co-simulation. In a recent webinar, Synopsys emphasized the importance of co-simulation between optics and electronics and highlighted the comprehensive tool suite it offers to its customers.

Synopsys’ Photonic IC Design Solution

The Photonic IC Design Solution provides a suite of powerful design and simulation tools tailored for photonic devices. Engineers can create, analyze, and fine-tune a wide array of photonic components and circuits, including waveguides, modulators, detectors, and switches, with precision and accuracy. Its extensive library of pre-designed photonic building blocks, significantly expedites the design process by reducing the need to construct components from scratch.

The Synopsys solution promotes co-design, enabling seamless integration between electronic and photonic components. This ensures that both the electrical and optical aspects of a system are optimized for enhanced overall performance. Advanced simulation capabilities, including wave-optics and electromagnetic simulations, empower engineers to predict and understand the behavior of photonic components under varying conditions. Designers can iteratively refine their designs based on specific performance parameters like bandwidth, power consumption, and signal-to-noise ratio.

Synopsys’ OptSim

OptSim is a cutting-edge photonic system and circuit simulator designed to address the unique challenges and complexities of modeling and simulating photonic devices and systems. The simulator offers sophisticated optical modeling capabilities, enabling engineers to accurately model the behavior of light in various optical components and systems. OptSim seamlessly integrates with Synopsys’ electronic design automation (EDA) tools, allowing for co-simulation between photonic and electronic circuits.

Summary

As the demand for higher bandwidth and innovative data center architectures continues to surge, optical links are emerging as a pivotal solution. By embracing optical interconnects and leveraging high-speed SerDes solutions, data centers can achieve higher bandwidth, lower latency, more power-efficient data centers. The collaboration between Synopsys and OpenLight is leading the way in transforming data centers by harnessing the power of optical links. The successful EOE demonstrations substantiate the robustness of these next-gen optical link solutions. The emergence of standards-compliant technologies like 112G LR, VSR, XSR/Direct-drive, and the next-generation 224G is poised to revolutionize optical links, making them the ideal choice for 800G/1.6T data transmission. Co-simulation between optics and electronics is the key to unlocking the full potential of this transformative technology. Synopsys equips designers with a comprehensive set of tools to seamlessly implement, analyze, and verify their optical link designs.

For more details,

visit www.synopsys.com/ethernet

visit www.synopsys.com/photonic-solutions/optsim.html

Also Read:

Qualcomm Insights into Unreachability Analysis

Synopsys Panel Updates on the State of Multi-Die Systems

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
by Daniel Nenni on 10-20-2023 at 10:00 am

Dan is joined by Anand Thiruvengadam, director of product and business management and head of the Solutions and Go-to-Market functions for the memory market segment at Synopsys.

Anand discusses the substantial demands experienced by memory designers due to trends such as big data analytics. He describes how these demands impact the design flow both during the design phase as well as after tapeout, creating a full silicon lifecycle management requirement, New effects that must be modeled such as aging and radiation are also discussed.

Against this backdrop Anand outlines the full-stack approach Synopsys has taken to address these design challenges. The company-wide focus on memory design as well as the addition of new AI techniques are presented.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?

ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?
by Robert Maire on 10-20-2023 at 8:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services
1 Comment

ASML Monopoly
  • ASML reports in-line QTR but future looks flat for 2024
  • Downcycle finally hits litho leader- ASML monopoly solid as ever
  • Memory remains bleak – New China sanctions unclear
  • Recovery timing is unclear but planning for an up 2025
In Line Quarter and year as expected

Overall revenues came in at Euro6.7B with EPS at Euro4.81, more or less in line with guidance and expectations. The company appears on track for its previously guided 30% growth in 2023 over 2022.

The obvious issue was that orders were down (-42%) significantly to Euro 2.6B with only Euro0.5B in EUV bookings which suggest weakness at leading edge and sustaining business at trailing technology.

Overall the company is looking at a flat 2024 over 2023……..

Length & Depth of downturn confirmed as it finally hits ASML

In the many years we have followed the semiconductor industry, it has always been the case that lithography tools were the last to be canceled/slowed while most other tools saw an immediate impact.

If the current downcycle were a year or less or limited to just the memory sector, its likely that ASML would have skated over the downcycle without impact while others got hit.

The length and depth of the current downturn is much deeper and longer than most previous cycles and thus has finally caught up with ASML. Customers are obviously less concerned about canceling and delaying orders as they are getting off the order queue that usually lasts well over a year. They are likely more confident that they will be able to get the tools whenever the recovery actually recovers.

This also seems to suggest that the recovery cycle will be longer and slower than prior recoveries otherwise customers would want to have equipment to be ready, and wouldn’t slow ASML orders.

A three or four year downcycle?

The downcycle started in the spring of 2022. If we assume that we are coming close to a bottom at the end of 2023 (as ASML suggests) we have spent the last year and nine months on the way down to the bottom.

If we assume a slow recovery (which already seems indicated) we won’t see a recovery back to prior levels until some time in 2025 (at best).

That would peg the current downcycle at 3 to 4 years making it one of the worst overall.

We were more negative than most every analyst going into the downturn and unfortunately we have been proven correct at the length and depth even though we had hoped to be wrong.

Monopoly remains solid

Despite recent hysteria and bad information there is no threat to ASML’s position on the horizon whatsoever.

The primary threat remains market health and demand. Sanctions are a secondary threat but less impactful than demand related issues.

China sanctions initially sound less impactful

Although ASML is still reading recently released sanctions from the US to figure out the impact, it appears at first blush that the impact is less than what could have otherwise been.

It looks like enough ARFi tools will be shipped into China to help out ASML’s revenues while “bad actors” in China will still be on the “verboten” list.

Final export licenses and approvals remain to be seen but so far “draconian” sanctions appear to be off the table.

Looks like Gina took the slap in the face and didn’t respond as much as could have been, showing restraint. Maybe Biden wants to have a better meeting with Xi.

High NA likely to be a bright spot in 2024

The roll out of High NA tools at the end of 2023 and going into 2024 is likely to be a significant portion of business and new orders when the industry does actually start to recover probably in 2025.

Importantly the company has not cut back on R&D or leading technology efforts as it represents the future of the company.

We think orders and revenues on High NA tools will be one of the things that elevates ASML out of the downturn faster than others in the industry.

At $400M or so a pop, it doesn’t take a lot of orders to add up to real money.

Timing of CHIPS Act & fab construction just sucks

Unfortunately the last thing you want to do in an oversupply based downcycle is build more capacity……

The CHIPS act aims to do just that…..All the new fabs announced in the US, if brought on line in the previously expected timeline would tank the industry again.

Its quite clear that delays TSMC Arizona, Intel and others are more due to the current oversupply/downcycle than any other issue.

We would expect at least a 2-3 year delay if not more, of many of these projects. Chip companies are simply not stupid enough to spend money on new capacity when they are already swimming in it.

This is obviously unfortunate as it delays the US reshoring effort and dependence on Asia remains without a reasonable solution…..

The Stock

As expected, a longer cycle that has impacted ASML’s 2024 will weigh down the stock as no growth in 2024 over 2023 is clearly disappointing.

However, the longer term remains strong. ASML’s position remains strong. Not much has changed about the overall dynamics of the semiconductor industry.

We do see collateral damage to other chip equipment stocks as the length of the downcycle impacts others more so than ASML.

We will likely hear more of that through the rest of earnings season….

Most other chip equipment makers will likely try to put a good face on it but the reality is that this is a longer than expected and worse downturn.

When even ASML catches a cold the rest of the equipment makers catch pneumonia….

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity

SPIE- EUV & Photomask conference- Anticipating high NA- Mask Size Matters- China

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper