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Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC

Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC
by Paul McLellan on 01-14-2014 at 7:00 pm

I spent the day at the SEMI Industry Strategy Symposium in Half Moon Bay. The early part of the day was devoted to technology challenges. Obviously everyone did not say exactly the same things, and had a little bit of a different spin depending on what business they are in. But there was a lot of commonality between Intel, IBM, Xilinx and GlobalFoundries. There were also presentations by the Global450mm Consortium and from Handel Jones of IBS. I will cover what they said in separate blogs later in the week.

Firstly, everyone pretty much agrees that there are no insurmountable technical challenges getting to 7nm. We know how to do it. Or at least we know what we have to do to get there, and it is engineering rather than basic research.

However, everyone agrees there are economic challenges in the sense that the costs of wafers are going up so fast that they overwhelm the savings that we get from increased scaling and as a result the cost per transistor is at best flat or at worse rising. Of course we get lots of other good things from the new process generations, such as reduced power, increased circuit complexity, increased performance. But, as I’ve said many times before, we don’t get a reduction in cost. If you are cost sensitive then 28nm still looks like the best process if you can get away without needing the features that only come from 20nm and below. Many of the speakers expressed confidence that the cost challenges would be addressed and we would get back on the nirvana of Moore’s Law but there was little hard data to back this up.

There was a healthy skepticism about EUV lithography. The source light is currently around 50W and 250W is required for it to be economic to use. Defect density on masks (remember these are actually multi-layer mirrors) is about 100 per mask and needs to be under 10 to make it feasible to take corrective measures.

Everyone agreed that stacking technologies of all kinds that allow us to get into the 3rd dimension will be increasingly important. Memory stacks, organic interposers, glass interposers, silicon interposers, and true 3D SoC (where a whole design is partitioned onto multiple die).

Michael Mayberry of Intel talked about Delivering Complexity to the Leading Edge. His basic premise was that we have to suck up the complexity in order to deliver simple user experiences. For example, a modern process (I think he was talking about 14nm) there are a billion transistors per square centimete (or 100 billion memory bits) and that requires 60 billion features across the design process and, in turn, with the complex RET needed for lithography, that is a trillion mask features across the mask set.

The big challenges are:

  • granularity (when you can count the atoms everything is granular)
  • size is limited by electrical behavior
  • voltage scaling limited by mobility
  • interconnect limits performance

Bryan Rice of GlobalFoundries talked about The Foundry Answer to Technology, Cost and Moore Scaling. His list of challenges was:

  • device architectures and scaling: FDSOI, FinFETs, nanowires, III-V materials
  • litho/EUV: cost, multipattern immersion, EUV power source, tool availability
  • packaging: normal economics are dead, value proposition moving to PPC, alternatives
  • 450mm: G450 Consortium, driven by immersion initally, EUV later

Ivo Bolsen discussed Programmable Platforms Essential to Leverage Further Logic Scaling. He talked less about process details but did talk a lot about 3D packaging where Xilinx is one of the leaders with a family of interposer-based parts already in production. But his bigger point was that the building blocks need to get bigger and, increasingly systems need to be designed in a hardware/software neutral way and automatically put into the fabric. His bet is OpenCL which allows designs to be compiled into code that runs in the normal software eocsystem (ARM etc) and accelerators that are automatically created in the FPGA fabric to handle the algorithms where power or performance mean that it cannot simply be implemented in software.

An Steegen of IMEC talked about Scalling Beyond 10nm. She ran through so many technologies where IMEC is doing research, some of which I had never heard of such as spin wave devices. But her big point was that there are three types of scaling going on: lithography enabled scaling, materials and device architecture scaling, and 3D enabled scaling.

Jon Casey of IBM focused on big data, System Scaling Technologies and Opportunities for Future IT Workloads and Systems. His big point was that a huge amount of power is dissipated just moving data around. Systems needed to get smaller so that less power was wasted and data could move faster and this means stacking chips, interposers and memory stacks (IBM is partner with Micron on the HMC). This is what he termed volumetric scaling.

So a huge amount of overlap. I’m still not convinced that we have any idea how to get back on the cost curve, or that EUV is going to work. But I’m pretty certain that 2014 and 2015 is going to be the year of 3D.

More articles by Paul McLellan…


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