3DIC in Burlingame

3DIC in Burlingame
by Paul McLellan on 12-01-2014 at 7:00 am

Every year in December is what I think of as the main 3D IC conference where you can get up to speed on all the latest. Officially it is called 3D Architectures for Semiconductor and Packaging or 3D ASIP. It is held in the Hyatt Regency in Burlingame (the one right by 101 near the airport). This year it is from December 10-12th.

The first… Read More


GSA 3DIC

GSA 3DIC
by Paul McLellan on 04-10-2014 at 6:27 pm

At the GSA Silicon Summit this afternoon there was a discussion of 3D IC and 2.5D IC. The session was moderated by Javier DeLaCruz of eSilicon and the panelists were:

  • Calvin Cheung of ASE (an OSAT)
  • Gil Lvey of OptimalTest (a test house)
  • Bob Patti of Tezzaron (semiconductor company specializing in TSV-based designs)
  • Riko Radojcic
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Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC

Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC
by Paul McLellan on 01-14-2014 at 7:00 pm

I spent the day at the SEMI Industry Strategy Symposium in Half Moon Bay. The early part of the day was devoted to technology challenges. Obviously everyone did not say exactly the same things, and had a little bit of a different spin depending on what business they are in. But there was a lot of commonality between Intel, IBM, Xilinx… Read More


GSA Silicon Summit

GSA Silicon Summit
by Paul McLellan on 01-13-2014 at 2:50 pm

Every year the GSA holds the GSA Silicon Summit. This year it is on April 10th at the Computer History Museum. It runs from 9am until 2.15pm. This year the focus is mostly on technologies other than simply scaling semiconductor technology. The meeting is divided into 3 sessions, each of which starts with a presentation and then is … Read More


3D: Atlanta and Burlingame

3D: Atlanta and Burlingame
by Paul McLellan on 12-04-2013 at 12:44 pm

Two conferences on 3D, one just over and one coming up next week. The one that was just over was hosted by Georgia Tech, the 3rd Annual Global Interposer Technology Workshop (GIT). I wasn’t there but my ex-colleague from VLSI Technology Herb Reiter was. Herb has become very much associated with all things 3D since he led the … Read More


GSA Silicon Summit: More than Moore

GSA Silicon Summit: More than Moore
by Paul McLellan on 04-05-2013 at 2:32 pm

The theme of this year’s GSA Silicon Summit is More than Moore. This has become a sort of catchall phrase for technologies other than simply moving to the next process node. The summit is on April 18th at the computer history museum (1401 Shoreline Blvd). Registration takes place at 9am and the actual sessions start at 9.45am.… Read More


EDPS: 3D ICs, part II

EDPS: 3D ICs, part II
by Paul McLellan on 04-12-2012 at 10:00 pm

Part I is here.

In the panel session at EDPS on 3D IC a number of major issues got highlighted (highlit?).

The first is the problem of known-good-die (KDG) which is what killed off the promising multi-chip-module approach, perhaps the earliest type of interposer. The KDG problem is that with a single die in a package it doesn’t… Read More