When it comes to extremely power sensitive applications such as IoT and edge devices, there is literally an arsenal of power saving techniques that could be used. The tricky part is figuring out which ones to use and how to use them for maximum benefit. This is coupled with the need to not hamper device performance or functionality.… Read More
VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone SurvivesSandra Rivera, Chair of VSORA, joined Bloomberg’s The…Read More
Intel’s Open Software Blueprint: Why Production AI Needs More Than GPUsIntel’s strategic argument about enterprise AI is that…Read More
CTO Interview with Dr. Zakir Syed of ClockEdgeDr. Zakir Syed is Co-founder and Chief Technology…Read More
Overcoming the Edge AI Power Wall with Low-Voltage Foundation IPAs artificial intelligence (AI) workloads migrate to endpoint…Read More
Keysight Advances its Design Software with Agentic AIKeysight Technologies is opening a new route for…Read MorePLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay… Read More
What a Difference an Architecture Makes: Optimizing AI for IoT
Last week Mentor hosted a virtual event on designing an AI accelerator with HLS, integrating it together with an Arm Corstone SSE-200 platform and characterizing/optimizing for performance and power. Though in some ways a recap of earlier presentations, there were some added insights in this session, particularly in characterizing… Read More
The Growing Relevance of IP-XACT in Today’s Complex Designs
The life of a SoC designer is an unenviable one. Not only does he have to work in a landscape where competition is intense but he also has to collaborate effectively with globally dispersed teams to ensure the design meets the project timeline. Then there are also the risks, more so in the current pandemic! There is the constant fear… Read More
Is the Worst Over for Semiconductors?
The worldwide economic outlook is chaotic due to the ongoing COVID-19 pandemic. The outlook for the semiconductor market is also very uncertain. 1Q 2020 revenue versus 4Q 2019 was mixed for major semiconductor companies, ranging from a 19% decline for STMicroelectronics to 9.9% growth from Kioxia (previously Toshiba Semiconductor).
Effect of Design on Transistor Density
I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes… Read More
Design in the Time of COVID
There’s a lot of debate about how and when we are going to emerge from the worldwide economic downturn triggered by the pandemic. Everyone agrees we will emerge. This isn’t humanity’s first pandemic, nor will it be our last. But do we come out quickly or slowly? And what does the economy look like on the other side, particularly for … Read More
CEO Interview: Robert Blake of Achronix
Achronix came to SemiWiki in 2017 and we added a chapter on the history of Achronix in our update version of “Fabless: The Transformation of the Semiconductor Industry”. So yes we know quite a bit about Achronix and the FPGA business so it was a pleasure to do a CEO Q&A with Robert Blake. First lets take a look at his … Read More
China’s Position in the Global Semiconductor Value Chain
In this third article about China’s role in the global semiconductor industry I analyse the current state of affairs of the Chinese semiconductor industry in different segments. In the previous articles, I looked at the possible effects of a US-China decoupling in the semiconductor industry and the impact of the Big … Read More
Contact Resistance: The Silent Device Scaling Barrier
Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.


Terafab’s Single Roof: Why Packaging, Not Lithography, Decides High Volume